Lines Matching refs:size
74 explicit SimStack(size_t size) : usable_size_(size) {}
79 void SetBaseGuardSize(size_t size) { base_guard_size_ = size; }
81 // Guard against stack overflows. The size should be large enough to detect
84 void SetLimitGuardSize(size_t size) { limit_guard_size_ = size; }
86 // The minimum usable size of the stack.
88 void SetUsableSize(size_t size) { usable_size_ = size; }
116 bool IsAccessInGuardRegion(const T* base, size_t size) const {
117 VIXL_ASSERT(size > 0);
120 const char* end = start + size - 1;
143 size_t size = l + u + b;
146 size_t alloc_size = (align_to - 1) + size;
150 reinterpret_cast<char*>(std::align(align_to, size, data, alloc_size));
271 size_t GetTotalCountMTE() { return metadata_mte_.size(); }
678 // The bit assignment is zero-extended to fill the size of predicate element.
865 unsigned size = RegisterSizeInBytesFromFormat(vform);
866 for (unsigned i = size; i < register_.GetSizeInBytes(); i++) {
1194 void MarkExclusive(uint64_t address, size_t size) {
1196 size_ = size;
1201 bool IsExclusive(uint64_t address, size_t size) {
1202 VIXL_ASSERT(size > 0);
1203 // Be pedantic: Require both the address and the size to match.
1204 return (size == size_) && (address == address_);
1223 bool IsExclusive(uint64_t address, size_t size) {
1224 USE(address, size);
1556 // As above, with parameterized size and return type. The value is
1559 T ReadRegister(unsigned size,
1563 switch (size) {
1583 T reg(unsigned size,
1586 return ReadRegister<T>(size, code, r31mode);
1590 int64_t ReadRegister(unsigned size,
1593 return ReadRegister<int64_t>(size, code, r31mode);
1596 int64_t reg(unsigned size,
1599 return ReadRegister(size, code, r31mode);
1687 // As above, with parameterized size and type. The value is either
1690 void WriteRegister(unsigned size,
1701 switch (size) {
1715 void set_reg(unsigned size,
1720 WriteRegister(size, code, value, log_mode, r31mode);
1830 // As above, with parameterized size and return type. The value is
1833 T ReadVRegister(unsigned size, unsigned code) const {
1837 switch (size) {
1855 VIXL_DEPRECATED("ReadVRegister", T vreg(unsigned size, unsigned code) const) {
1856 return ReadVRegister<T>(size, code);
2158 // The lane size.
2171 // The overall register size.
2197 #define VIXL_DECL_PRINT_REG_SCALAR(size) \
2198 kPrint##size##Reg = kPrintRegLaneSize##size | kPrintRegAsScalar, \
2199 kPrint##size##RegPartial = kPrintRegLaneSize##size | kPrintRegPartial
2200 #define VIXL_DECL_PRINT_REG_SCALAR_FP(size) \
2201 VIXL_DECL_PRINT_REG_SCALAR(size) \
2202 , kPrint##size##RegFP = kPrint##size##Reg | kPrintRegAsFP, \
2203 kPrint##size##RegPartialFP = kPrint##size##RegPartial | kPrintRegAsFP
2213 #define VIXL_DECL_PRINT_REG_NEON(count, type, size) \
2214 kPrintReg##count##type = kPrintRegLaneSize##type | kPrintRegAs##size, \
2216 #define VIXL_DECL_PRINT_REG_NEON_FP(count, type, size) \
2217 VIXL_DECL_PRINT_REG_NEON(count, type, size) \
2262 // Keep the FP and lane size fields.
2269 // combination of FP and lane size that SVE formats do.
2353 PrintRegisterFormat GetPrintRegisterFormatForSize(unsigned size) {
2354 return GetPrintRegisterFormatForSize(size, size);
2357 PrintRegisterFormat GetPrintRegisterFormatForSizeFP(unsigned size) {
2358 switch (size) {
2380 PrintRegisterFormat GetPrintRegisterFormatForSizeTryFP(unsigned size) {
2381 return GetPrintRegisterFormatTryFP(GetPrintRegisterFormatForSize(size));
2641 // lane size is not respected when interpreting lane_mask: unaligned bits
2657 // the size of each access, and to format the accessed value.
2670 // The size of the register being accessed. This helper is usually used
3002 // Configure the simulated value of 'VL', which is the size of a Z register.
5179 bool CanReadMemory(uintptr_t address, size_t size);
5274 // A configurable size of SVE vector registers.