Lines Matching defs:src
564 void WriteLane(T src, int lane) {
566 VIXL_ASSERT((sizeof(src) + (lane * sizeof(src))) <= GetSizeInBytes());
567 memcpy(&value_[lane * sizeof(src)], &src, sizeof(src));
580 void WriteLane(vixl::internal::SimFloat16 src, int lane) {
581 WriteLane(Float16ToRawbits(src), lane);
806 void SetIntArray(VectorFormat vform, const int64_t* src) const {
809 SetInt(vform, i, src[i]);
834 void SetUintArray(VectorFormat vform, const uint64_t* src) const {
837 SetUint(vform, i, src[i]);
2082 void StoreLane(const LogicVRegister& src,
2087 MemWrite(msize_in_bytes, addr, src.Uint(vform, index));
2565 void LogMemTransfer(uintptr_t dst, uintptr_t src, uint8_t value) {
2566 if (ShouldTraceWrites()) PrintMemTransfer(dst, src, value);
2579 void PrintMemTransfer(uintptr_t dst, uintptr_t src, uint8_t value);
2848 int src,
3377 void st1(VectorFormat vform, LogicVRegister src, uint64_t addr);
3378 void st1(VectorFormat vform, LogicVRegister src, int index, uint64_t addr);
3380 LogicVRegister src,
3384 LogicVRegister src,
3389 LogicVRegister src,
3394 LogicVRegister src,
3400 LogicVRegister src,
3406 LogicVRegister src,
3621 const LogicVRegister& src,
3638 const LogicVRegister& src);
3641 const LogicVRegister& src);
3644 const LogicVRegister& src);
3647 const LogicVRegister& src);
3650 const LogicVRegister& src);
3653 const LogicVRegister& src);
3656 const LogicVRegister& src);
3659 const LogicVRegister& src,
3663 const LogicVRegister& src);
3666 const LogicVRegister& src);
3669 const LogicVRegister& src);
3672 const LogicVRegister& src,
3677 const LogicVRegister& src);
3680 const LogicVRegister& src);
3683 const LogicVRegister& src);
3686 const LogicVRegister& src);
3689 const LogicVRegister& src,
3698 const LogicVRegister& src,
3735 const LogicVRegister& src);
3739 const LogicVRegister& src);
3781 const LogicVRegister& src,
3790 const LogicVRegister& src,
3794 const LogicVRegister& src,
3805 const LogicVRegister& src);
3806 LogicPRegister mov(LogicPRegister dst, const LogicPRegister& src);
3810 const LogicVRegister& src);
3814 const LogicVRegister& src);
3817 const LogicVRegister& src,
3821 const LogicPRegister& src);
3824 const LogicPRegister& src);
3829 const LogicVRegister& src,
3865 const LogicVRegister& src);
3908 const LogicVRegister& src);
3911 const LogicVRegister& src);
3914 const LogicVRegister& src);
3917 const LogicVRegister& src);
3921 const LogicVRegister& src,
3925 const LogicVRegister& src);
3928 const LogicVRegister& src);
3931 const LogicVRegister& src,
3935 const LogicVRegister& src);
3938 const LogicVRegister& src,
3942 const LogicVRegister& src);
3945 const LogicVRegister& src,
3949 const LogicVRegister& src,
4096 const LogicVRegister& src,
4100 const LogicVRegister& src);
4103 const LogicVRegister& src);
4130 const LogicVRegister& src,
4137 const LogicVRegister& src,
4142 const LogicVRegister& src,
4150 const LogicVRegister& src,
4155 const LogicVRegister& src,
4160 const LogicVRegister& src,
4164 const LogicVRegister& src,
4168 const LogicVRegister& src);
4171 const LogicVRegister& src);
4174 const LogicVRegister& src,
4178 const LogicVRegister& src,
4182 const LogicVRegister& src,
4186 const LogicVRegister& src,
4190 const LogicVRegister& src,
4194 const LogicVRegister& src,
4198 const LogicVRegister& src,
4202 const LogicVRegister& src,
4206 const LogicVRegister& src,
4210 const LogicVRegister& src,
4222 const LogicVRegister& src,
4226 const LogicVRegister& src,
4230 const LogicVRegister& src,
4234 const LogicVRegister& src);
4237 const LogicVRegister& src);
4241 const LogicVRegister& src,
4245 const LogicVRegister& src);
4248 const LogicVRegister& src);
4251 const LogicVRegister& src);
4254 const LogicVRegister& src);
4270 const LogicVRegister& src,
4274 const LogicVRegister& src,
4278 const LogicVRegister& src,
4282 const LogicVRegister& src,
4286 const LogicVRegister& src,
4290 const LogicVRegister& src,
4294 const LogicVRegister& src,
4298 const LogicVRegister& src,
4302 const LogicVRegister& src,
4306 const LogicVRegister& src,
4310 const LogicVRegister& src,
4314 const LogicVRegister& src,
4318 const LogicVRegister& src,
4322 const LogicVRegister& src,
4326 const LogicVRegister& src,
4330 const LogicVRegister& src,
4510 const LogicVRegister& src);
4600 const LogicVRegister& src,
4606 const LogicVRegister& src);
4609 const LogicVRegister& src);
4613 const LogicVRegister& src);
4616 const LogicVRegister& src);
4632 const LogicVRegister& src);
4635 const LogicVRegister& src);
4648 const LogicVRegister& src);
4651 const LogicVRegister& src);
4658 const LogicVRegister& src,
4666 const LogicVRegister& src);
4672 const LogicVRegister& src,
4677 const LogicVRegister& src,
4685 const LogicVRegister& src,
4690 const LogicVRegister& src,
4695 const LogicVRegister& src);
4698 const LogicVRegister& src);
4701 const LogicVRegister& src);
4704 const LogicVRegister& src);
4707 const LogicVRegister& src);
4710 const LogicVRegister& src);
4713 const LogicVRegister& src);
4716 const LogicVRegister& src);
4719 const LogicVRegister& src,
4723 const LogicVRegister& src);
4726 const LogicVRegister& src);
4731 const LogicPRegister& src);
4736 const LogicPRegister& src);
4746 const LogicVRegister& src);
4750 const LogicVRegister& src);
4754 const LogicVRegister& src);
4758 const LogicVRegister& src);
4762 const LogicVRegister& src);
4766 const LogicVRegister& src);
4770 const LogicVRegister& src);
4774 const LogicVRegister& src);
4778 const LogicVRegister& src);
4782 const LogicVRegister& src);
4792 const LogicVRegister& src,
4799 const LogicVRegister& src,
4807 const LogicVRegister& src);
4810 const LogicVRegister& src);
4813 const LogicVRegister& src);
4816 const LogicVRegister& src);
4819 const LogicVRegister& src);
4845 double FixedToDouble(int64_t src, int fbits, FPRounding round_mode);
4846 double UFixedToDouble(uint64_t src, int fbits, FPRounding round_mode);
4847 float FixedToFloat(int64_t src, int fbits, FPRounding round_mode);
4848 float UFixedToFloat(uint64_t src, int fbits, FPRounding round_mode);
4849 ::vixl::internal::SimFloat16 FixedToFloat16(int64_t src,
4852 ::vixl::internal::SimFloat16 UFixedToFloat16(uint64_t src,
5029 const LogicVRegister& src);
5035 const LogicVRegister& src);