Lines Matching defs:bits
177 uint64_t bits = (uint64_t)address;
178 return (T)(bits & ~kAddressTagMask);
501 // 0 represents the least significant bits.
615 // Set a conveniently-sized block to 16 bits as the minimum predicate length
616 // is 16 bits and allow to be increased to multiples of 16 bits.
653 ChunkType bits = GetUintMask(chunk_size);
657 SetChunk(lane, bits);
682 int bits = value ? 1 : 0;
685 AssignBit(byte, index, bits);
688 AssignBits(byte, index, 0x03, bits);
691 AssignBits(byte, index, 0x0f, bits);
694 AssignBits(byte, index, 0xff, bits);
860 // bits of the register must be cleared.
1114 // The default constructor represents a register which has no writable bits.
1142 void SetBits(int msb, int lsb, uint32_t bits);
1150 void Set##Name(uint32_t bits) { SetBits(HighBit, LowBit, bits); }
1160 // Most system registers only implement a few of the bits in the word. Other
1161 // bits are "read-as-zero, write-ignored". The write_ignore_mask argument
1162 // describes the bits which are not modifiable.
2108 // the width of the value to write is smaller than 64 bits, the unused
2109 // bits may contain unrelated values that the code following this write
2111 // Here we fill the unused bits with a predefined pattern to catch issues
2183 // With this flag, print helpers won't check that the upper bits are zero.
2442 // but such formats indicate that the unprinted high-order bits are zero and
2641 // lane size is not respected when interpreting lane_mask: unaligned bits
3045 const LogicPRegister& bits) {
3048 return bits.IsActive(vform, i);
3056 const LogicPRegister& bits) {
3058 if (mask.IsActive(vform, i) && bits.IsActive(vform, i)) {
3067 const LogicPRegister& bits) {
3070 return bits.IsActive(vform, i);
3078 const LogicPRegister& bits) {
3079 ReadNzcv().SetN(IsFirstActive(vform, mask, bits));
3080 ReadNzcv().SetZ(AreNoneActive(vform, mask, bits));
3081 ReadNzcv().SetC(!IsLastActive(vform, mask, bits));
4909 // for cumulative exception bits or floating-point exceptions.
4926 // sign-extend. Initial `acc` bits outside `n` are ignored, but the delta must
5092 // A pseudo SVE predicate register with all bits set to true.
5096 // bits[31, 27]: Condition flags N, Z, C, and V.