Lines Matching refs:rt_code
1540 void Simulator::PrintVRegistersForStructuredAccess(int rt_code,
1550 int code = (rt_code + r) % kNumberOfVRegisters;
1559 void Simulator::PrintZRegistersForStructuredAccess(int rt_code,
1573 const uint8_t* value = vregisters_[rt_code].GetBytes() + byte_index;
1574 VIXL_ASSERT((byte_index + size) <= vregisters_[rt_code].GetSizeInBytes());
1577 int code = (rt_code + r) % kNumberOfZRegisters;
1851 void Simulator::PrintVStructAccess(int rt_code,
1865 PrintVRegistersForStructuredAccess(rt_code, reg_count, lane_mask, format);
1881 void Simulator::PrintVSingleStructAccess(int rt_code,
1896 PrintVRegistersForStructuredAccess(rt_code, reg_count, lane_mask, format);
1900 void Simulator::PrintVReplicatingStructAccess(int rt_code,
1914 PrintVRegistersForStructuredAccess(rt_code, reg_count, lane_mask, format);
1918 void Simulator::PrintZAccess(int rt_code, const char* op, uintptr_t address) {
1932 PrintPartialZRegister(rt_code, q_index, kPrintRegVnQPartial, "");
1943 void Simulator::PrintZStructAccess(int rt_code,
1971 PrintZRegistersForStructuredAccess(rt_code,
1998 vregisters_[(rt_code + i) % kNumberOfZRegisters].NotifyRegisterLogged();
2045 void Simulator::PrintRead(int rt_code,
2049 if (rt_code != kZeroRegCode) {
2050 registers_[rt_code].NotifyRegisterLogged();
2052 PrintAccess(rt_code, format, "<-", address);
2055 void Simulator::PrintExtendingRead(int rt_code,
2062 PrintRead(rt_code, format, address);
2070 if (rt_code != kZeroRegCode) {
2071 registers_[rt_code].NotifyRegisterLogged();
2073 PrintRegister(rt_code, format);
2083 void Simulator::PrintVRead(int rt_code,
2087 vregisters_[rt_code].NotifyRegisterLogged();
2088 PrintVAccess(rt_code, format, "<-", address);
2091 void Simulator::PrintWrite(int rt_code,
2098 if (rt_code != kZeroRegCode) {
2099 registers_[rt_code].NotifyRegisterLogged();
2101 PrintAccess(rt_code, format, "->", address);
2104 void Simulator::PrintVWrite(int rt_code,
2113 PrintVAccess(rt_code, format, "->", address);