Lines Matching refs:_h
75 {"smlal_asimdelem_l"_h, &Simulator::SimulateNEONMulByElementLong},
76 {"smlsl_asimdelem_l"_h, &Simulator::SimulateNEONMulByElementLong},
77 {"smull_asimdelem_l"_h, &Simulator::SimulateNEONMulByElementLong},
78 {"sqdmlal_asimdelem_l"_h, &Simulator::SimulateNEONMulByElementLong},
79 {"sqdmlsl_asimdelem_l"_h, &Simulator::SimulateNEONMulByElementLong},
80 {"sqdmull_asimdelem_l"_h, &Simulator::SimulateNEONMulByElementLong},
81 {"umlal_asimdelem_l"_h, &Simulator::SimulateNEONMulByElementLong},
82 {"umlsl_asimdelem_l"_h, &Simulator::SimulateNEONMulByElementLong},
83 {"umull_asimdelem_l"_h, &Simulator::SimulateNEONMulByElementLong},
84 {"fcmla_asimdelem_c_h"_h, &Simulator::SimulateNEONComplexMulByElement},
85 {"fcmla_asimdelem_c_s"_h, &Simulator::SimulateNEONComplexMulByElement},
86 {"fmlal2_asimdelem_lh"_h, &Simulator::SimulateNEONFPMulByElementLong},
87 {"fmlal_asimdelem_lh"_h, &Simulator::SimulateNEONFPMulByElementLong},
88 {"fmlsl2_asimdelem_lh"_h, &Simulator::SimulateNEONFPMulByElementLong},
89 {"fmlsl_asimdelem_lh"_h, &Simulator::SimulateNEONFPMulByElementLong},
90 {"fmla_asimdelem_rh_h"_h, &Simulator::SimulateNEONFPMulByElement},
91 {"fmls_asimdelem_rh_h"_h, &Simulator::SimulateNEONFPMulByElement},
92 {"fmulx_asimdelem_rh_h"_h, &Simulator::SimulateNEONFPMulByElement},
93 {"fmul_asimdelem_rh_h"_h, &Simulator::SimulateNEONFPMulByElement},
94 {"fmla_asimdelem_r_sd"_h, &Simulator::SimulateNEONFPMulByElement},
95 {"fmls_asimdelem_r_sd"_h, &Simulator::SimulateNEONFPMulByElement},
96 {"fmulx_asimdelem_r_sd"_h, &Simulator::SimulateNEONFPMulByElement},
97 {"fmul_asimdelem_r_sd"_h, &Simulator::SimulateNEONFPMulByElement},
98 {"sdot_asimdelem_d"_h, &Simulator::SimulateNEONDotProdByElement},
99 {"udot_asimdelem_d"_h, &Simulator::SimulateNEONDotProdByElement},
100 {"adclb_z_zzz"_h, &Simulator::SimulateSVEAddSubCarry},
101 {"adclt_z_zzz"_h, &Simulator::SimulateSVEAddSubCarry},
102 {"addhnb_z_zz"_h, &Simulator::SimulateSVEAddSubHigh},
103 {"addhnt_z_zz"_h, &Simulator::SimulateSVEAddSubHigh},
104 {"addp_z_p_zz"_h, &Simulator::SimulateSVEIntArithPair},
105 {"bcax_z_zzz"_h, &Simulator::SimulateSVEBitwiseTernary},
106 {"bdep_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmT},
107 {"bext_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmT},
108 {"bgrp_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmT},
109 {"bsl1n_z_zzz"_h, &Simulator::SimulateSVEBitwiseTernary},
110 {"bsl2n_z_zzz"_h, &Simulator::SimulateSVEBitwiseTernary},
111 {"bsl_z_zzz"_h, &Simulator::SimulateSVEBitwiseTernary},
112 {"cadd_z_zz"_h, &Simulator::Simulate_ZdnT_ZdnT_ZmT_const},
113 {"cdot_z_zzz"_h, &Simulator::SimulateSVEComplexDotProduct},
114 {"cdot_z_zzzi_d"_h, &Simulator::SimulateSVEComplexDotProduct},
115 {"cdot_z_zzzi_s"_h, &Simulator::SimulateSVEComplexDotProduct},
116 {"cmla_z_zzz"_h, &Simulator::SimulateSVEComplexIntMulAdd},
117 {"cmla_z_zzzi_h"_h, &Simulator::SimulateSVEComplexIntMulAdd},
118 {"cmla_z_zzzi_s"_h, &Simulator::SimulateSVEComplexIntMulAdd},
119 {"eor3_z_zzz"_h, &Simulator::SimulateSVEBitwiseTernary},
120 {"eorbt_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmT},
121 {"eortb_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmT},
122 {"ext_z_zi_con"_h, &Simulator::Simulate_ZdB_Zn1B_Zn2B_imm},
123 {"faddp_z_p_zz"_h, &Simulator::Simulate_ZdnT_PgM_ZdnT_ZmT},
124 {"fcvtlt_z_p_z_h2s"_h, &Simulator::SimulateSVEFPConvertLong},
125 {"fcvtlt_z_p_z_s2d"_h, &Simulator::SimulateSVEFPConvertLong},
126 {"fcvtnt_z_p_z_d2s"_h, &Simulator::Simulate_ZdS_PgM_ZnD},
127 {"fcvtnt_z_p_z_s2h"_h, &Simulator::Simulate_ZdH_PgM_ZnS},
128 {"fcvtx_z_p_z_d2s"_h, &Simulator::Simulate_ZdS_PgM_ZnD},
129 {"fcvtxnt_z_p_z_d2s"_h, &Simulator::Simulate_ZdS_PgM_ZnD},
130 {"flogb_z_p_z"_h, &Simulator::Simulate_ZdT_PgM_ZnT},
131 {"fmaxnmp_z_p_zz"_h, &Simulator::Simulate_ZdnT_PgM_ZdnT_ZmT},
132 {"fmaxp_z_p_zz"_h, &Simulator::Simulate_ZdnT_PgM_ZdnT_ZmT},
133 {"fminnmp_z_p_zz"_h, &Simulator::Simulate_ZdnT_PgM_ZdnT_ZmT},
134 {"fminp_z_p_zz"_h, &Simulator::Simulate_ZdnT_PgM_ZdnT_ZmT},
135 {"fmlalb_z_zzz"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH},
136 {"fmlalb_z_zzzi_s"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH_imm},
137 {"fmlalt_z_zzz"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH},
138 {"fmlalt_z_zzzi_s"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH_imm},
139 {"fmlslb_z_zzz"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH},
140 {"fmlslb_z_zzzi_s"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH_imm},
141 {"fmlslt_z_zzz"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH},
142 {"fmlslt_z_zzzi_s"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH_imm},
143 {"histcnt_z_p_zz"_h, &Simulator::Simulate_ZdT_PgZ_ZnT_ZmT},
144 {"histseg_z_zz"_h, &Simulator::Simulate_ZdB_ZnB_ZmB},
145 {"ldnt1b_z_p_ar_d_64_unscaled"_h, &Simulator::Simulate_ZtD_PgZ_ZnD_Xm},
146 {"ldnt1b_z_p_ar_s_x32_unscaled"_h, &Simulator::Simulate_ZtS_PgZ_ZnS_Xm},
147 {"ldnt1d_z_p_ar_d_64_unscaled"_h, &Simulator::Simulate_ZtD_PgZ_ZnD_Xm},
148 {"ldnt1h_z_p_ar_d_64_unscaled"_h, &Simulator::Simulate_ZtD_PgZ_ZnD_Xm},
149 {"ldnt1h_z_p_ar_s_x32_unscaled"_h, &Simulator::Simulate_ZtS_PgZ_ZnS_Xm},
150 {"ldnt1sb_z_p_ar_d_64_unscaled"_h, &Simulator::Simulate_ZtD_PgZ_ZnD_Xm},
151 {"ldnt1sb_z_p_ar_s_x32_unscaled"_h, &Simulator::Simulate_ZtS_PgZ_ZnS_Xm},
152 {"ldnt1sh_z_p_ar_d_64_unscaled"_h, &Simulator::Simulate_ZtD_PgZ_ZnD_Xm},
153 {"ldnt1sh_z_p_ar_s_x32_unscaled"_h, &Simulator::Simulate_ZtS_PgZ_ZnS_Xm},
154 {"ldnt1sw_z_p_ar_d_64_unscaled"_h, &Simulator::Simulate_ZtD_PgZ_ZnD_Xm},
155 {"ldnt1w_z_p_ar_d_64_unscaled"_h, &Simulator::Simulate_ZtD_PgZ_ZnD_Xm},
156 {"ldnt1w_z_p_ar_s_x32_unscaled"_h, &Simulator::Simulate_ZtS_PgZ_ZnS_Xm},
157 {"match_p_p_zz"_h, &Simulator::Simulate_PdT_PgZ_ZnT_ZmT},
158 {"mla_z_zzzi_d"_h, &Simulator::SimulateSVEMlaMlsIndex},
159 {"mla_z_zzzi_h"_h, &Simulator::SimulateSVEMlaMlsIndex},
160 {"mla_z_zzzi_s"_h, &Simulator::SimulateSVEMlaMlsIndex},
161 {"mls_z_zzzi_d"_h, &Simulator::SimulateSVEMlaMlsIndex},
162 {"mls_z_zzzi_h"_h, &Simulator::SimulateSVEMlaMlsIndex},
163 {"mls_z_zzzi_s"_h, &Simulator::SimulateSVEMlaMlsIndex},
164 {"mul_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmT},
165 {"mul_z_zzi_d"_h, &Simulator::SimulateSVEMulIndex},
166 {"mul_z_zzi_h"_h, &Simulator::SimulateSVEMulIndex},
167 {"mul_z_zzi_s"_h, &Simulator::SimulateSVEMulIndex},
168 {"nbsl_z_zzz"_h, &Simulator::SimulateSVEBitwiseTernary},
169 {"nmatch_p_p_zz"_h, &Simulator::Simulate_PdT_PgZ_ZnT_ZmT},
170 {"pmul_z_zz"_h, &Simulator::Simulate_ZdB_ZnB_ZmB},
171 {"pmullb_z_zz"_h, &Simulator::SimulateSVEIntMulLongVec},
172 {"pmullt_z_zz"_h, &Simulator::SimulateSVEIntMulLongVec},
173 {"raddhnb_z_zz"_h, &Simulator::SimulateSVEAddSubHigh},
174 {"raddhnt_z_zz"_h, &Simulator::SimulateSVEAddSubHigh},
175 {"rshrnb_z_zi"_h, &Simulator::SimulateSVENarrow},
176 {"rshrnt_z_zi"_h, &Simulator::SimulateSVENarrow},
177 {"rsubhnb_z_zz"_h, &Simulator::SimulateSVEAddSubHigh},
178 {"rsubhnt_z_zz"_h, &Simulator::SimulateSVEAddSubHigh},
179 {"saba_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnT_ZmT},
180 {"sabalb_z_zzz"_h, &Simulator::SimulateSVEInterleavedArithLong},
181 {"sabalt_z_zzz"_h, &Simulator::SimulateSVEInterleavedArithLong},
182 {"sabdlb_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
183 {"sabdlt_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
184 {"sadalp_z_p_z"_h, &Simulator::Simulate_ZdaT_PgM_ZnTb},
185 {"saddlb_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
186 {"saddlbt_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
187 {"saddlt_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
188 {"saddwb_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmTb},
189 {"saddwt_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmTb},
190 {"sbclb_z_zzz"_h, &Simulator::SimulateSVEAddSubCarry},
191 {"sbclt_z_zzz"_h, &Simulator::SimulateSVEAddSubCarry},
192 {"shadd_z_p_zz"_h, &Simulator::SimulateSVEHalvingAddSub},
193 {"shrnb_z_zi"_h, &Simulator::SimulateSVENarrow},
194 {"shrnt_z_zi"_h, &Simulator::SimulateSVENarrow},
195 {"shsub_z_p_zz"_h, &Simulator::SimulateSVEHalvingAddSub},
196 {"shsubr_z_p_zz"_h, &Simulator::SimulateSVEHalvingAddSub},
197 {"sli_z_zzi"_h, &Simulator::Simulate_ZdT_ZnT_const},
198 {"smaxp_z_p_zz"_h, &Simulator::SimulateSVEIntArithPair},
199 {"sminp_z_p_zz"_h, &Simulator::SimulateSVEIntArithPair},
200 {"smlalb_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
201 {"smlalb_z_zzzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
202 {"smlalb_z_zzzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
203 {"smlalt_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
204 {"smlalt_z_zzzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
205 {"smlalt_z_zzzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
206 {"smlslb_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
207 {"smlslb_z_zzzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
208 {"smlslb_z_zzzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
209 {"smlslt_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
210 {"smlslt_z_zzzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
211 {"smlslt_z_zzzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
212 {"smulh_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmT},
213 {"smullb_z_zz"_h, &Simulator::SimulateSVEIntMulLongVec},
214 {"smullb_z_zzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
215 {"smullb_z_zzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
216 {"smullt_z_zz"_h, &Simulator::SimulateSVEIntMulLongVec},
217 {"smullt_z_zzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
218 {"smullt_z_zzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
219 {"splice_z_p_zz_con"_h, &Simulator::VisitSVEVectorSplice},
220 {"sqabs_z_p_z"_h, &Simulator::Simulate_ZdT_PgM_ZnT},
221 {"sqadd_z_p_zz"_h, &Simulator::SimulateSVESaturatingArithmetic},
222 {"sqcadd_z_zz"_h, &Simulator::Simulate_ZdnT_ZdnT_ZmT_const},
223 {"sqdmlalb_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
224 {"sqdmlalb_z_zzzi_d"_h, &Simulator::Simulate_ZdaD_ZnS_ZmS_imm},
225 {"sqdmlalb_z_zzzi_s"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH_imm},
226 {"sqdmlalbt_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
227 {"sqdmlalt_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
228 {"sqdmlalt_z_zzzi_d"_h, &Simulator::Simulate_ZdaD_ZnS_ZmS_imm},
229 {"sqdmlalt_z_zzzi_s"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH_imm},
230 {"sqdmlslb_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
231 {"sqdmlslb_z_zzzi_d"_h, &Simulator::Simulate_ZdaD_ZnS_ZmS_imm},
232 {"sqdmlslb_z_zzzi_s"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH_imm},
233 {"sqdmlslbt_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
234 {"sqdmlslt_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
235 {"sqdmlslt_z_zzzi_d"_h, &Simulator::Simulate_ZdaD_ZnS_ZmS_imm},
236 {"sqdmlslt_z_zzzi_s"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH_imm},
237 {"sqdmulh_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmT},
238 {"sqdmulh_z_zzi_d"_h, &Simulator::SimulateSVESaturatingMulHighIndex},
239 {"sqdmulh_z_zzi_h"_h, &Simulator::SimulateSVESaturatingMulHighIndex},
240 {"sqdmulh_z_zzi_s"_h, &Simulator::SimulateSVESaturatingMulHighIndex},
241 {"sqdmullb_z_zz"_h, &Simulator::SimulateSVEIntMulLongVec},
242 {"sqdmullb_z_zzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
243 {"sqdmullb_z_zzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
244 {"sqdmullt_z_zz"_h, &Simulator::SimulateSVEIntMulLongVec},
245 {"sqdmullt_z_zzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
246 {"sqdmullt_z_zzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
247 {"sqneg_z_p_z"_h, &Simulator::Simulate_ZdT_PgM_ZnT},
248 {"sqrdcmlah_z_zzz"_h, &Simulator::SimulateSVEComplexIntMulAdd},
249 {"sqrdcmlah_z_zzzi_h"_h, &Simulator::SimulateSVEComplexIntMulAdd},
250 {"sqrdcmlah_z_zzzi_s"_h, &Simulator::SimulateSVEComplexIntMulAdd},
251 {"sqrdmlah_z_zzz"_h, &Simulator::SimulateSVESaturatingMulAddHigh},
252 {"sqrdmlah_z_zzzi_d"_h, &Simulator::SimulateSVESaturatingMulAddHigh},
253 {"sqrdmlah_z_zzzi_h"_h, &Simulator::SimulateSVESaturatingMulAddHigh},
254 {"sqrdmlah_z_zzzi_s"_h, &Simulator::SimulateSVESaturatingMulAddHigh},
255 {"sqrdmlsh_z_zzz"_h, &Simulator::SimulateSVESaturatingMulAddHigh},
256 {"sqrdmlsh_z_zzzi_d"_h, &Simulator::SimulateSVESaturatingMulAddHigh},
257 {"sqrdmlsh_z_zzzi_h"_h, &Simulator::SimulateSVESaturatingMulAddHigh},
258 {"sqrdmlsh_z_zzzi_s"_h, &Simulator::SimulateSVESaturatingMulAddHigh},
259 {"sqrdmulh_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmT},
260 {"sqrdmulh_z_zzi_d"_h, &Simulator::SimulateSVESaturatingMulHighIndex},
261 {"sqrdmulh_z_zzi_h"_h, &Simulator::SimulateSVESaturatingMulHighIndex},
262 {"sqrdmulh_z_zzi_s"_h, &Simulator::SimulateSVESaturatingMulHighIndex},
263 {"sqrshl_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
264 {"sqrshlr_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
265 {"sqrshrnb_z_zi"_h, &Simulator::SimulateSVENarrow},
266 {"sqrshrnt_z_zi"_h, &Simulator::SimulateSVENarrow},
267 {"sqrshrunb_z_zi"_h, &Simulator::SimulateSVENarrow},
268 {"sqrshrunt_z_zi"_h, &Simulator::SimulateSVENarrow},
269 {"sqshl_z_p_zi"_h, &Simulator::Simulate_ZdnT_PgM_ZdnT_const},
270 {"sqshl_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
271 {"sqshlr_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
272 {"sqshlu_z_p_zi"_h, &Simulator::Simulate_ZdnT_PgM_ZdnT_const},
273 {"sqshrnb_z_zi"_h, &Simulator::SimulateSVENarrow},
274 {"sqshrnt_z_zi"_h, &Simulator::SimulateSVENarrow},
275 {"sqshrunb_z_zi"_h, &Simulator::SimulateSVENarrow},
276 {"sqshrunt_z_zi"_h, &Simulator::SimulateSVENarrow},
277 {"sqsub_z_p_zz"_h, &Simulator::SimulateSVESaturatingArithmetic},
278 {"sqsubr_z_p_zz"_h, &Simulator::SimulateSVESaturatingArithmetic},
279 {"sqxtnb_z_zz"_h, &Simulator::SimulateSVENarrow},
280 {"sqxtnt_z_zz"_h, &Simulator::SimulateSVENarrow},
281 {"sqxtunb_z_zz"_h, &Simulator::SimulateSVENarrow},
282 {"sqxtunt_z_zz"_h, &Simulator::SimulateSVENarrow},
283 {"srhadd_z_p_zz"_h, &Simulator::SimulateSVEHalvingAddSub},
284 {"sri_z_zzi"_h, &Simulator::Simulate_ZdT_ZnT_const},
285 {"srshl_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
286 {"srshlr_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
287 {"srshr_z_p_zi"_h, &Simulator::Simulate_ZdnT_PgM_ZdnT_const},
288 {"srsra_z_zi"_h, &Simulator::Simulate_ZdaT_ZnT_const},
289 {"sshllb_z_zi"_h, &Simulator::SimulateSVEShiftLeftImm},
290 {"sshllt_z_zi"_h, &Simulator::SimulateSVEShiftLeftImm},
291 {"ssra_z_zi"_h, &Simulator::Simulate_ZdaT_ZnT_const},
292 {"ssublb_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
293 {"ssublbt_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
294 {"ssublt_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
295 {"ssubltb_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
296 {"ssubwb_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmTb},
297 {"ssubwt_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmTb},
298 {"stnt1b_z_p_ar_d_64_unscaled"_h, &Simulator::Simulate_ZtD_Pg_ZnD_Xm},
299 {"stnt1b_z_p_ar_s_x32_unscaled"_h, &Simulator::Simulate_ZtS_Pg_ZnS_Xm},
300 {"stnt1d_z_p_ar_d_64_unscaled"_h, &Simulator::Simulate_ZtD_Pg_ZnD_Xm},
301 {"stnt1h_z_p_ar_d_64_unscaled"_h, &Simulator::Simulate_ZtD_Pg_ZnD_Xm},
302 {"stnt1h_z_p_ar_s_x32_unscaled"_h, &Simulator::Simulate_ZtS_Pg_ZnS_Xm},
303 {"stnt1w_z_p_ar_d_64_unscaled"_h, &Simulator::Simulate_ZtD_Pg_ZnD_Xm},
304 {"stnt1w_z_p_ar_s_x32_unscaled"_h, &Simulator::Simulate_ZtS_Pg_ZnS_Xm},
305 {"subhnb_z_zz"_h, &Simulator::SimulateSVEAddSubHigh},
306 {"subhnt_z_zz"_h, &Simulator::SimulateSVEAddSubHigh},
307 {"suqadd_z_p_zz"_h, &Simulator::SimulateSVESaturatingArithmetic},
308 {"tbl_z_zz_2"_h, &Simulator::VisitSVETableLookup},
309 {"tbx_z_zz"_h, &Simulator::VisitSVETableLookup},
310 {"uaba_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnT_ZmT},
311 {"uabalb_z_zzz"_h, &Simulator::SimulateSVEInterleavedArithLong},
312 {"uabalt_z_zzz"_h, &Simulator::SimulateSVEInterleavedArithLong},
313 {"uabdlb_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
314 {"uabdlt_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
315 {"uadalp_z_p_z"_h, &Simulator::Simulate_ZdaT_PgM_ZnTb},
316 {"uaddlb_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
317 {"uaddlt_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
318 {"uaddwb_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmTb},
319 {"uaddwt_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmTb},
320 {"uhadd_z_p_zz"_h, &Simulator::SimulateSVEHalvingAddSub},
321 {"uhsub_z_p_zz"_h, &Simulator::SimulateSVEHalvingAddSub},
322 {"uhsubr_z_p_zz"_h, &Simulator::SimulateSVEHalvingAddSub},
323 {"umaxp_z_p_zz"_h, &Simulator::SimulateSVEIntArithPair},
324 {"uminp_z_p_zz"_h, &Simulator::SimulateSVEIntArithPair},
325 {"umlalb_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
326 {"umlalb_z_zzzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
327 {"umlalb_z_zzzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
328 {"umlalt_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
329 {"umlalt_z_zzzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
330 {"umlalt_z_zzzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
331 {"umlslb_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
332 {"umlslb_z_zzzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
333 {"umlslb_z_zzzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
334 {"umlslt_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
335 {"umlslt_z_zzzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
336 {"umlslt_z_zzzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
337 {"umulh_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmT},
338 {"umullb_z_zz"_h, &Simulator::SimulateSVEIntMulLongVec},
339 {"umullb_z_zzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
340 {"umullb_z_zzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
341 {"umullt_z_zz"_h, &Simulator::SimulateSVEIntMulLongVec},
342 {"umullt_z_zzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
343 {"umullt_z_zzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
344 {"uqadd_z_p_zz"_h, &Simulator::SimulateSVESaturatingArithmetic},
345 {"uqrshl_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
346 {"uqrshlr_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
347 {"uqrshrnb_z_zi"_h, &Simulator::SimulateSVENarrow},
348 {"uqrshrnt_z_zi"_h, &Simulator::SimulateSVENarrow},
349 {"uqshl_z_p_zi"_h, &Simulator::Simulate_ZdnT_PgM_ZdnT_const},
350 {"uqshl_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
351 {"uqshlr_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
352 {"uqshrnb_z_zi"_h, &Simulator::SimulateSVENarrow},
353 {"uqshrnt_z_zi"_h, &Simulator::SimulateSVENarrow},
354 {"uqsub_z_p_zz"_h, &Simulator::SimulateSVESaturatingArithmetic},
355 {"uqsubr_z_p_zz"_h, &Simulator::SimulateSVESaturatingArithmetic},
356 {"uqxtnb_z_zz"_h, &Simulator::SimulateSVENarrow},
357 {"uqxtnt_z_zz"_h, &Simulator::SimulateSVENarrow},
358 {"urecpe_z_p_z"_h, &Simulator::Simulate_ZdS_PgM_ZnS},
359 {"urhadd_z_p_zz"_h, &Simulator::SimulateSVEHalvingAddSub},
360 {"urshl_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
361 {"urshlr_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
362 {"urshr_z_p_zi"_h, &Simulator::Simulate_ZdnT_PgM_ZdnT_const},
363 {"ursqrte_z_p_z"_h, &Simulator::Simulate_ZdS_PgM_ZnS},
364 {"ursra_z_zi"_h, &Simulator::Simulate_ZdaT_ZnT_const},
365 {"ushllb_z_zi"_h, &Simulator::SimulateSVEShiftLeftImm},
366 {"ushllt_z_zi"_h, &Simulator::SimulateSVEShiftLeftImm},
367 {"usqadd_z_p_zz"_h, &Simulator::SimulateSVESaturatingArithmetic},
368 {"usra_z_zi"_h, &Simulator::Simulate_ZdaT_ZnT_const},
369 {"usublb_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
370 {"usublt_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
371 {"usubwb_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmTb},
372 {"usubwt_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmTb},
373 {"whilege_p_p_rr"_h, &Simulator::VisitSVEIntCompareScalarCountAndLimit},
374 {"whilegt_p_p_rr"_h, &Simulator::VisitSVEIntCompareScalarCountAndLimit},
375 {"whilehi_p_p_rr"_h, &Simulator::VisitSVEIntCompareScalarCountAndLimit},
376 {"whilehs_p_p_rr"_h, &Simulator::VisitSVEIntCompareScalarCountAndLimit},
377 {"whilerw_p_rr"_h, &Simulator::Simulate_PdT_Xn_Xm},
378 {"whilewr_p_rr"_h, &Simulator::Simulate_PdT_Xn_Xm},
379 {"xar_z_zzi"_h, &Simulator::SimulateSVEExclusiveOrRotate},
380 {"smmla_z_zzz"_h, &Simulator::SimulateMatrixMul},
381 {"ummla_z_zzz"_h, &Simulator::SimulateMatrixMul},
382 {"usmmla_z_zzz"_h, &Simulator::SimulateMatrixMul},
383 {"smmla_asimdsame2_g"_h, &Simulator::SimulateMatrixMul},
384 {"ummla_asimdsame2_g"_h, &Simulator::SimulateMatrixMul},
385 {"usmmla_asimdsame2_g"_h, &Simulator::SimulateMatrixMul},
386 {"fmmla_z_zzz_s"_h, &Simulator::SimulateSVEFPMatrixMul},
387 {"fmmla_z_zzz_d"_h, &Simulator::SimulateSVEFPMatrixMul},
388 {"ld1row_z_p_bi_u32"_h,
390 {"ld1row_z_p_br_contiguous"_h,
392 {"ld1rod_z_p_bi_u64"_h,
394 {"ld1rod_z_p_br_contiguous"_h,
396 {"ld1rob_z_p_bi_u8"_h,
398 {"ld1rob_z_p_br_contiguous"_h,
400 {"ld1roh_z_p_bi_u16"_h,
402 {"ld1roh_z_p_br_contiguous"_h,
404 {"usdot_z_zzz_s"_h, &Simulator::VisitSVEIntMulAddUnpredicated},
405 {"sudot_z_zzzi_s"_h, &Simulator::VisitSVEMulIndex},
406 {"usdot_z_zzzi_s"_h, &Simulator::VisitSVEMulIndex},
407 {"usdot_asimdsame2_d"_h, &Simulator::VisitNEON3SameExtra},
408 {"sudot_asimdelem_d"_h, &Simulator::SimulateNEONDotProdByElement},
409 {"usdot_asimdelem_d"_h, &Simulator::SimulateNEONDotProdByElement},
410 {"addg_64_addsub_immtags"_h, &Simulator::SimulateMTEAddSubTag},
411 {"gmi_64g_dp_2src"_h, &Simulator::SimulateMTETagMaskInsert},
412 {"irg_64i_dp_2src"_h, &Simulator::Simulate_XdSP_XnSP_Xm},
413 {"ldg_64loffset_ldsttags"_h, &Simulator::SimulateMTELoadTag},
414 {"st2g_64soffset_ldsttags"_h, &Simulator::Simulator::SimulateMTEStoreTag},
415 {"st2g_64spost_ldsttags"_h, &Simulator::Simulator::SimulateMTEStoreTag},
416 {"st2g_64spre_ldsttags"_h, &Simulator::Simulator::SimulateMTEStoreTag},
417 {"stgp_64_ldstpair_off"_h, &Simulator::SimulateMTEStoreTagPair},
418 {"stgp_64_ldstpair_post"_h, &Simulator::SimulateMTEStoreTagPair},
419 {"stgp_64_ldstpair_pre"_h, &Simulator::SimulateMTEStoreTagPair},
420 {"stg_64soffset_ldsttags"_h, &Simulator::Simulator::SimulateMTEStoreTag},
421 {"stg_64spost_ldsttags"_h, &Simulator::Simulator::SimulateMTEStoreTag},
422 {"stg_64spre_ldsttags"_h, &Simulator::Simulator::SimulateMTEStoreTag},
423 {"stz2g_64soffset_ldsttags"_h,
425 {"stz2g_64spost_ldsttags"_h, &Simulator::Simulator::SimulateMTEStoreTag},
426 {"stz2g_64spre_ldsttags"_h, &Simulator::Simulator::SimulateMTEStoreTag},
427 {"stzg_64soffset_ldsttags"_h, &Simulator::Simulator::SimulateMTEStoreTag},
428 {"stzg_64spost_ldsttags"_h, &Simulator::Simulator::SimulateMTEStoreTag},
429 {"stzg_64spre_ldsttags"_h, &Simulator::Simulator::SimulateMTEStoreTag},
430 {"subg_64_addsub_immtags"_h, &Simulator::SimulateMTEAddSubTag},
431 {"subps_64s_dp_2src"_h, &Simulator::SimulateMTESubPointer},
432 {"subp_64s_dp_2src"_h, &Simulator::SimulateMTESubPointer},
433 {"cpyen_cpy_memcms"_h, &Simulator::SimulateCpyE},
434 {"cpyern_cpy_memcms"_h, &Simulator::SimulateCpyE},
435 {"cpyewn_cpy_memcms"_h, &Simulator::SimulateCpyE},
436 {"cpye_cpy_memcms"_h, &Simulator::SimulateCpyE},
437 {"cpyfen_cpy_memcms"_h, &Simulator::SimulateCpyE},
438 {"cpyfern_cpy_memcms"_h, &Simulator::SimulateCpyE},
439 {"cpyfewn_cpy_memcms"_h, &Simulator::SimulateCpyE},
440 {"cpyfe_cpy_memcms"_h, &Simulator::SimulateCpyE},
441 {"cpyfmn_cpy_memcms"_h, &Simulator::SimulateCpyM},
442 {"cpyfmrn_cpy_memcms"_h, &Simulator::SimulateCpyM},
443 {"cpyfmwn_cpy_memcms"_h, &Simulator::SimulateCpyM},
444 {"cpyfm_cpy_memcms"_h, &Simulator::SimulateCpyM},
445 {"cpyfpn_cpy_memcms"_h, &Simulator::SimulateCpyFP},
446 {"cpyfprn_cpy_memcms"_h, &Simulator::SimulateCpyFP},
447 {"cpyfpwn_cpy_memcms"_h, &Simulator::SimulateCpyFP},
448 {"cpyfp_cpy_memcms"_h, &Simulator::SimulateCpyFP},
449 {"cpymn_cpy_memcms"_h, &Simulator::SimulateCpyM},
450 {"cpymrn_cpy_memcms"_h, &Simulator::SimulateCpyM},
451 {"cpymwn_cpy_memcms"_h, &Simulator::SimulateCpyM},
452 {"cpym_cpy_memcms"_h, &Simulator::SimulateCpyM},
453 {"cpypn_cpy_memcms"_h, &Simulator::SimulateCpyP},
454 {"cpyprn_cpy_memcms"_h, &Simulator::SimulateCpyP},
455 {"cpypwn_cpy_memcms"_h, &Simulator::SimulateCpyP},
456 {"cpyp_cpy_memcms"_h, &Simulator::SimulateCpyP},
457 {"setp_set_memcms"_h, &Simulator::SimulateSetP},
458 {"setpn_set_memcms"_h, &Simulator::SimulateSetP},
459 {"setgp_set_memcms"_h, &Simulator::SimulateSetGP},
460 {"setgpn_set_memcms"_h, &Simulator::SimulateSetGP},
461 {"setm_set_memcms"_h, &Simulator::SimulateSetM},
462 {"setmn_set_memcms"_h, &Simulator::SimulateSetM},
463 {"setgm_set_memcms"_h, &Simulator::SimulateSetGM},
464 {"setgmn_set_memcms"_h, &Simulator::SimulateSetGM},
465 {"sete_set_memcms"_h, &Simulator::SimulateSetE},
466 {"seten_set_memcms"_h, &Simulator::SimulateSetE},
467 {"setge_set_memcms"_h, &Simulator::SimulateSetE},
468 {"setgen_set_memcms"_h, &Simulator::SimulateSetE},
469 {"abs_32_dp_1src"_h, &Simulator::VisitDataProcessing1Source},
470 {"abs_64_dp_1src"_h, &Simulator::VisitDataProcessing1Source},
471 {"cnt_32_dp_1src"_h, &Simulator::VisitDataProcessing1Source},
472 {"cnt_64_dp_1src"_h, &Simulator::VisitDataProcessing1Source},
473 {"ctz_32_dp_1src"_h, &Simulator::VisitDataProcessing1Source},
474 {"ctz_64_dp_1src"_h, &Simulator::VisitDataProcessing1Source},
475 {"smax_32_dp_2src"_h, &Simulator::SimulateSignedMinMax},
476 {"smax_64_dp_2src"_h, &Simulator::SimulateSignedMinMax},
477 {"smin_32_dp_2src"_h, &Simulator::SimulateSignedMinMax},
478 {"smin_64_dp_2src"_h, &Simulator::SimulateSignedMinMax},
479 {"smax_32_minmax_imm"_h, &Simulator::SimulateSignedMinMax},
480 {"smax_64_minmax_imm"_h, &Simulator::SimulateSignedMinMax},
481 {"smin_32_minmax_imm"_h, &Simulator::SimulateSignedMinMax},
482 {"smin_64_minmax_imm"_h, &Simulator::SimulateSignedMinMax},
483 {"umax_32_dp_2src"_h, &Simulator::SimulateUnsignedMinMax},
484 {"umax_64_dp_2src"_h, &Simulator::SimulateUnsignedMinMax},
485 {"umin_32_dp_2src"_h, &Simulator::SimulateUnsignedMinMax},
486 {"umin_64_dp_2src"_h, &Simulator::SimulateUnsignedMinMax},
487 {"umax_32u_minmax_imm"_h, &Simulator::SimulateUnsignedMinMax},
488 {"umax_64u_minmax_imm"_h, &Simulator::SimulateUnsignedMinMax},
489 {"umin_32u_minmax_imm"_h, &Simulator::SimulateUnsignedMinMax},
490 {"umin_64u_minmax_imm"_h, &Simulator::SimulateUnsignedMinMax},
2148 case "match_p_p_zz"_h:
2151 case "nmatch_p_p_zz"_h:
2172 case "whilerw_p_rr"_h:
2175 case "whilewr_p_rr"_h:
2193 VIXL_ASSERT(form_hash_ == "ext_z_zi_con"_h);
2212 case "histseg_z_zz"_h:
2224 case "pmul_z_zz"_h:
2242 VIXL_ASSERT((form_hash_ == "mul_z_zzi_d"_h) ||
2243 (form_hash_ == "mul_z_zzi_h"_h) ||
2244 (form_hash_ == "mul_z_zzi_s"_h));
2262 (form_hash_ == "mla_z_zzzi_d"_h) || (form_hash_ == "mla_z_zzzi_h"_h) ||
2263 (form_hash_ == "mla_z_zzzi_s"_h) || (form_hash_ == "mls_z_zzzi_d"_h) ||
2264 (form_hash_ == "mls_z_zzzi_h"_h) || (form_hash_ == "mls_z_zzzi_s"_h));
2290 case "sqdmulh_z_zzi_h"_h:
2291 case "sqdmulh_z_zzi_s"_h:
2292 case "sqdmulh_z_zzi_d"_h:
2295 case "sqrdmulh_z_zzi_h"_h:
2296 case "sqrdmulh_z_zzi_s"_h:
2297 case "sqrdmulh_z_zzi_d"_h:
2323 case "smullb_z_zzi_s"_h:
2324 case "smullb_z_zzi_d"_h:
2327 case "smullt_z_zzi_s"_h:
2328 case "smullt_z_zzi_d"_h:
2331 case "sqdmullb_z_zzi_d"_h:
2334 case "sqdmullt_z_zzi_d"_h:
2337 case "umullb_z_zzi_s"_h:
2338 case "umullb_z_zzi_d"_h:
2341 case "umullt_z_zzi_s"_h:
2342 case "umullt_z_zzi_d"_h:
2345 case "sqdmullb_z_zzi_s"_h:
2348 case "sqdmullt_z_zzi_s"_h:
2351 case "smlalb_z_zzzi_s"_h:
2352 case "smlalb_z_zzzi_d"_h:
2355 case "smlalt_z_zzzi_s"_h:
2356 case "smlalt_z_zzzi_d"_h:
2359 case "smlslb_z_zzzi_s"_h:
2360 case "smlslb_z_zzzi_d"_h:
2363 case "smlslt_z_zzzi_s"_h:
2364 case "smlslt_z_zzzi_d"_h:
2367 case "umlalb_z_zzzi_s"_h:
2368 case "umlalb_z_zzzi_d"_h:
2371 case "umlalt_z_zzzi_s"_h:
2372 case "umlalt_z_zzzi_d"_h:
2375 case "umlslb_z_zzzi_s"_h:
2376 case "umlslb_z_zzzi_d"_h:
2379 case "umlslt_z_zzzi_s"_h:
2380 case "umlslt_z_zzzi_d"_h:
2397 case "fcvtnt_z_p_z_s2h"_h:
2418 case "fcvtnt_z_p_z_d2s"_h:
2423 case "fcvtx_z_p_z_d2s"_h:
2427 case "fcvtxnt_z_p_z_d2s"_h:
2444 case "fcvtlt_z_p_z_h2s"_h:
2448 case "fcvtlt_z_p_z_s2d"_h:
2469 case "urecpe_z_p_z"_h:
2472 case "ursqrte_z_p_z"_h:
2489 case "flogb_z_p_z"_h:
2493 case "sqabs_z_p_z"_h:
2496 case "sqneg_z_p_z"_h:
2513 VIXL_ASSERT(form_hash_ == "histcnt_z_p_zz"_h);
2531 case "bdep_z_zz"_h:
2534 case "bext_z_zz"_h:
2537 case "bgrp_z_zz"_h:
2540 case "eorbt_z_zz"_h:
2545 case "eortb_z_zz"_h:
2550 case "mul_z_zz"_h:
2553 case "smulh_z_zz"_h:
2556 case "sqdmulh_z_zz"_h:
2559 case "sqrdmulh_z_zz"_h:
2562 case "umulh_z_zz"_h:
2582 case "saddwb_z_zz"_h:
2585 case "saddwt_z_zz"_h:
2588 case "ssubwb_z_zz"_h:
2591 case "ssubwt_z_zz"_h:
2594 case "uaddwb_z_zz"_h:
2597 case "uaddwt_z_zz"_h:
2600 case "usubwb_z_zz"_h:
2603 case "usubwt_z_zz"_h:
2624 case "sli_z_zzi"_h:
2630 case "sri_z_zzi"_h:
2653 case "sqxtnt_z_zz"_h:
2656 case "sqxtnb_z_zz"_h:
2659 case "sqxtunt_z_zz"_h:
2662 case "sqxtunb_z_zz"_h:
2665 case "uqxtnt_z_zz"_h:
2668 case "uqxtnb_z_zz"_h:
2671 case "rshrnt_z_zi"_h:
2674 case "rshrnb_z_zi"_h:
2677 case "shrnt_z_zi"_h:
2680 case "shrnb_z_zi"_h:
2683 case "sqrshrnt_z_zi"_h:
2686 case "sqrshrnb_z_zi"_h:
2689 case "sqrshrunt_z_zi"_h:
2692 case "sqrshrunb_z_zi"_h:
2695 case "sqshrnt_z_zi"_h:
2698 case "sqshrnb_z_zi"_h:
2701 case "sqshrunt_z_zi"_h:
2704 case "sqshrunb_z_zi"_h:
2707 case "uqrshrnt_z_zi"_h:
2710 case "uqrshrnb_z_zi"_h:
2713 case "uqshrnt_z_zi"_h:
2716 case "uqshrnb_z_zi"_h:
2751 case "sabdlb_z_zz"_h:
2754 case "sabdlt_z_zz"_h:
2757 case "saddlb_z_zz"_h:
2760 case "saddlbt_z_zz"_h:
2763 case "saddlt_z_zz"_h:
2766 case "ssublb_z_zz"_h:
2769 case "ssublbt_z_zz"_h:
2772 case "ssublt_z_zz"_h:
2775 case "ssubltb_z_zz"_h:
2778 case "uabdlb_z_zz"_h:
2781 case "uabdlt_z_zz"_h:
2784 case "uaddlb_z_zz"_h:
2787 case "uaddlt_z_zz"_h:
2790 case "usublb_z_zz"_h:
2793 case "usublt_z_zz"_h:
2796 case "sabalb_z_zzz"_h:
2799 case "sabalt_z_zzz"_h:
2802 case "uabalb_z_zzz"_h:
2805 case "uabalt_z_zzz"_h:
2826 case "pmullb_z_zz"_h:
2833 case "pmullt_z_zz"_h:
2840 case "smullb_z_zz"_h:
2843 case "smullt_z_zz"_h:
2846 case "sqdmullb_z_zz"_h:
2849 case "sqdmullt_z_zz"_h:
2852 case "umullb_z_zz"_h:
2855 case "umullt_z_zz"_h:
2877 case "addhnt_z_zz"_h:
2880 case "addhnb_z_zz"_h:
2883 case "raddhnt_z_zz"_h:
2886 case "raddhnb_z_zz"_h:
2889 case "rsubhnt_z_zz"_h:
2892 case "rsubhnb_z_zz"_h:
2895 case "subhnt_z_zz"_h:
2898 case "subhnb_z_zz"_h:
2938 case "sshllb_z_zi"_h:
2941 case "sshllt_z_zi"_h:
2944 case "ushllb_z_zi"_h:
2947 case "ushllt_z_zi"_h:
2964 case "sqrdmlah_z_zzz"_h:
2967 case "sqrdmlsh_z_zzz"_h:
2970 case "sqrdmlah_z_zzzi_h"_h:
2973 case "sqrdmlsh_z_zzzi_h"_h:
2978 case "sqrdmlah_z_zzzi_s"_h:
2981 case "sqrdmlsh_z_zzzi_s"_h:
2986 case "sqrdmlah_z_zzzi_d"_h:
2989 case "sqrdmlsh_z_zzzi_d"_h:
3024 case "sqdmlalb_z_zzzi_d"_h:
3027 case "sqdmlalt_z_zzzi_d"_h:
3030 case "sqdmlslb_z_zzzi_d"_h:
3033 case "sqdmlslt_z_zzzi_d"_h:
3053 case "fmlalb_z_zzz"_h:
3056 case "fmlalt_z_zzz"_h:
3059 case "fmlslb_z_zzz"_h:
3062 case "fmlslt_z_zzz"_h:
3083 case "fmlalb_z_zzzi_s"_h:
3086 case "fmlalt_z_zzzi_s"_h:
3089 case "fmlslb_z_zzzi_s"_h:
3092 case "fmlslt_z_zzzi_s"_h:
3095 case "sqdmlalb_z_zzzi_s"_h:
3098 case "sqdmlalt_z_zzzi_s"_h:
3101 case "sqdmlslb_z_zzzi_s"_h:
3104 case "sqdmlslt_z_zzzi_s"_h:
3120 case "sadalp_z_p_z"_h:
3123 case "uadalp_z_p_z"_h:
3142 case "adclb_z_zzz"_h:
3145 case "adclt_z_zzz"_h:
3148 case "sbclb_z_zzz"_h:
3151 case "sbclt_z_zzz"_h:
3166 case "saba_z_zzz"_h:
3169 case "uaba_z_zzz"_h:
3192 case "cmla_z_zzz"_h:
3195 case "cmla_z_zzzi_h"_h:
3198 case "cmla_z_zzzi_s"_h:
3201 case "sqrdcmlah_z_zzz"_h:
3204 case "sqrdcmlah_z_zzzi_h"_h:
3207 case "sqrdcmlah_z_zzzi_s"_h:
3228 case "srsra_z_zi"_h:
3231 case "ssra_z_zi"_h:
3234 case "ursra_z_zi"_h:
3237 case "usra_z_zi"_h:
3261 case "smlalb_z_zzz"_h:
3264 case "smlalt_z_zzz"_h:
3267 case "smlslb_z_zzz"_h:
3270 case "smlslt_z_zzz"_h:
3273 case "sqdmlalb_z_zzz"_h:
3276 case "sqdmlalbt_z_zzz"_h:
3279 case "sqdmlalt_z_zzz"_h:
3282 case "sqdmlslb_z_zzz"_h:
3285 case "sqdmlslbt_z_zzz"_h:
3288 case "sqdmlslt_z_zzz"_h:
3291 case "umlalb_z_zzz"_h:
3294 case "umlalt_z_zzz"_h:
3297 case "umlslb_z_zzz"_h:
3300 case "umlslt_z_zzz"_h:
3317 case "cdot_z_zzz"_h:
3320 case "cdot_z_zzzi_s"_h:
3324 case "cdot_z_zzzi_d"_h:
3346 case "bcax_z_zzz"_h:
3350 case "bsl1n_z_zzz"_h:
3354 case "bsl2n_z_zzz"_h:
3358 case "bsl_z_zzz"_h:
3361 case "eor3_z_zzz"_h:
3365 case "nbsl_z_zzz"_h:
3382 case "shadd_z_p_zz"_h:
3385 case "shsub_z_p_zz"_h:
3388 case "shsubr_z_p_zz"_h:
3391 case "srhadd_z_p_zz"_h:
3394 case "uhadd_z_p_zz"_h:
3397 case "uhsub_z_p_zz"_h:
3400 case "uhsubr_z_p_zz"_h:
3403 case "urhadd_z_p_zz"_h:
3421 case "sqadd_z_p_zz"_h:
3424 case "sqsub_z_p_zz"_h:
3427 case "sqsubr_z_p_zz"_h:
3430 case "suqadd_z_p_zz"_h:
3433 case "uqadd_z_p_zz"_h:
3436 case "uqsub_z_p_zz"_h:
3439 case "uqsubr_z_p_zz"_h:
3442 case "usqadd_z_p_zz"_h:
3460 case "addp_z_p_zz"_h:
3463 case "smaxp_z_p_zz"_h:
3466 case "sminp_z_p_zz"_h:
3469 case "umaxp_z_p_zz"_h:
3472 case "uminp_z_p_zz"_h:
3490 case "faddp_z_p_zz"_h:
3493 case "fmaxnmp_z_p_zz"_h:
3496 case "fmaxp_z_p_zz"_h:
3499 case "fminnmp_z_p_zz"_h:
3502 case "fminp_z_p_zz"_h:
3524 case "sqshl_z_p_zi"_h:
3527 case "sqshlu_z_p_zi"_h:
3530 case "srshr_z_p_zi"_h:
3533 case "uqshl_z_p_zi"_h:
3536 case "urshr_z_p_zi"_h:
3546 VIXL_ASSERT(form_hash_ == "xar_z_zzi"_h);
3568 case "cadd_z_zz"_h:
3571 case "sqcadd_z_zz"_h:
3589 case "ldnt1b_z_p_ar_d_64_unscaled"_h:
3592 case "ldnt1d_z_p_ar_d_64_unscaled"_h:
3595 case "ldnt1h_z_p_ar_d_64_unscaled"_h:
3598 case "ldnt1sb_z_p_ar_d_64_unscaled"_h:
3602 case "ldnt1sh_z_p_ar_d_64_unscaled"_h:
3606 case "ldnt1sw_z_p_ar_d_64_unscaled"_h:
3610 case "ldnt1w_z_p_ar_d_64_unscaled"_h:
3626 VIXL_ASSERT((form_hash_ == "stnt1b_z_p_ar_d_64_unscaled"_h) ||
3627 (form_hash_ == "stnt1d_z_p_ar_d_64_unscaled"_h) ||
3628 (form_hash_ == "stnt1h_z_p_ar_d_64_unscaled"_h) ||
3629 (form_hash_ == "stnt1w_z_p_ar_d_64_unscaled"_h));
3646 case "ldnt1b_z_p_ar_s_x32_unscaled"_h:
3649 case "ldnt1h_z_p_ar_s_x32_unscaled"_h:
3652 case "ldnt1sb_z_p_ar_s_x32_unscaled"_h:
3656 case "ldnt1sh_z_p_ar_s_x32_unscaled"_h:
3660 case "ldnt1w_z_p_ar_s_x32_unscaled"_h:
3676 VIXL_ASSERT((form_hash_ == "stnt1b_z_p_ar_s_x32_unscaled"_h) ||
3677 (form_hash_ == "stnt1h_z_p_ar_s_x32_unscaled"_h) ||
3678 (form_hash_ == "stnt1w_z_p_ar_s_x32_unscaled"_h));
5319 case "pac" #SUF0 "z" #SUF1 "_64z_dp_1src"_h: \
5323 case "pac" #SUF0 #SUF1 "_64p_dp_1src"_h: { \
5329 case "aut" #SUF0 "z" #SUF1 "_64z_dp_1src"_h: \
5333 case "aut" #SUF0 #SUF1 "_64p_dp_1src"_h: { \
5342 case "xpaci_64z_dp_1src"_h:
5345 case "xpacd_64z_dp_1src"_h:
5348 case "rbit_32_dp_1src"_h:
5351 case "rbit_64_dp_1src"_h:
5354 case "rev16_32_dp_1src"_h:
5357 case "rev16_64_dp_1src"_h:
5360 case "rev_32_dp_1src"_h:
5363 case "rev32_64_dp_1src"_h:
5366 case "rev_64_dp_1src"_h:
5369 case "clz_32_dp_1src"_h:
5372 case "clz_64_dp_1src"_h:
5375 case "cls_32_dp_1src"_h:
5378 case "cls_64_dp_1src"_h:
5381 case "abs_32_dp_1src"_h:
5384 case "abs_64_dp_1src"_h:
5387 case "cnt_32_dp_1src"_h:
5390 case "cnt_64_dp_1src"_h:
5393 case "ctz_32_dp_1src"_h:
5396 case "ctz_64_dp_1src"_h:
5587 case "smax_64_minmax_imm"_h:
5588 case "smin_64_minmax_imm"_h:
5591 case "smax_32_minmax_imm"_h:
5592 case "smin_32_minmax_imm"_h:
5598 case "smax_32_minmax_imm"_h:
5599 case "smax_32_dp_2src"_h:
5602 case "smax_64_minmax_imm"_h:
5603 case "smax_64_dp_2src"_h:
5606 case "smin_32_minmax_imm"_h:
5607 case "smin_32_dp_2src"_h:
5610 case "smin_64_minmax_imm"_h:
5611 case "smin_64_dp_2src"_h:
5624 case "umax_64u_minmax_imm"_h:
5625 case "umax_32u_minmax_imm"_h:
5626 case "umin_64u_minmax_imm"_h:
5627 case "umin_32u_minmax_imm"_h:
5633 case "umax_32u_minmax_imm"_h:
5634 case "umax_32_dp_2src"_h:
5638 case "umax_64u_minmax_imm"_h:
5639 case "umax_64_dp_2src"_h:
5642 case "umin_32u_minmax_imm"_h:
5643 case "umin_32_dp_2src"_h:
5647 case "umin_64u_minmax_imm"_h:
5648 case "umin_64_dp_2src"_h:
6712 case "cfinv_m_pstate"_h:
6715 case "axflag_m_pstate"_h:
6721 case "xaflag_m_pstate"_h: {
6733 case "xpaclri_hi_hints"_h:
6736 case "clrex_bn_barriers"_h:
6740 case "msr_sr_systemmove"_h:
6754 case "mrs_rs_systemmove"_h:
6779 case "nop_hi_hints"_h:
6780 case "esb_hi_hints"_h:
6781 case "csdb_hi_hints"_h:
6783 case "bti_hb_hints"_h:
6807 case "pacib1716_hi_hints"_h:
6810 case "pacia1716_hi_hints"_h:
6813 case "pacibsp_hi_hints"_h:
6816 case "paciasp_hi_hints"_h:
6833 case "pacibz_hi_hints"_h:
6836 case "paciaz_hi_hints"_h:
6839 case "autib1716_hi_hints"_h:
6842 case "autia1716_hi_hints"_h:
6845 case "autibsp_hi_hints"_h:
6848 case "autiasp_hi_hints"_h:
6851 case "autibz_hi_hints"_h:
6854 case "autiaz_hi_hints"_h:
6857 case "dsb_bo_barriers"_h:
6858 case "dmb_bo_barriers"_h:
6859 case "isb_bi_barriers"_h:
6862 case "sys_cr_systeminstrs"_h:
7670 case "fcmla_asimdsame2_c"_h:
7674 case "fcadd_asimdsame2_c"_h:
7678 case "sdot_asimdsame2_d"_h:
7681 case "udot_asimdsame2_d"_h:
7684 case "usdot_asimdsame2_d"_h:
7687 case "sqrdmlah_asimdsame2_only"_h:
7690 case "sqrdmlsh_asimdsame2_only"_h:
7969 case "smull_asimdelem_l"_h:
7972 case "umull_asimdelem_l"_h:
7975 case "smlal_asimdelem_l"_h:
7978 case "umlal_asimdelem_l"_h:
7981 case "smlsl_asimdelem_l"_h:
7984 case "umlsl_asimdelem_l"_h:
7987 case "sqdmull_asimdelem_l"_h:
7990 case "sqdmlal_asimdelem_l"_h:
7993 case "sqdmlsl_asimdelem_l"_h:
8011 case "fmlal_asimdelem_lh"_h:
8014 case "fmlal2_asimdelem_lh"_h:
8017 case "fmlsl_asimdelem_lh"_h:
8020 case "fmlsl2_asimdelem_lh"_h:
8055 case "fmul_asimdelem_rh_h"_h:
8056 case "fmul_asimdelem_r_sd"_h:
8059 case "fmla_asimdelem_rh_h"_h:
8060 case "fmla_asimdelem_r_sd"_h:
8063 case "fmls_asimdelem_rh_h"_h:
8064 case "fmls_asimdelem_r_sd"_h:
8067 case "fmulx_asimdelem_rh_h"_h:
8068 case "fmulx_asimdelem_r_sd"_h:
8084 case "fcmla_asimdelem_c_s"_h:
8088 case "fcmla_asimdelem_c_h"_h:
8110 case "sdot_asimdelem_d"_h:
8113 case "udot_asimdelem_d"_h:
8116 case "sudot_asimdelem_d"_h:
8119 case "usdot_asimdelem_d"_h:
8143 case "mul_asimdelem_r"_h:
8146 case "mla_asimdelem_r"_h:
8149 case "mls_asimdelem_r"_h:
8152 case "sqdmulh_asimdelem_r"_h:
8155 case "sqrdmulh_asimdelem_r"_h:
8158 case "sqrdmlah_asimdelem_r"_h:
8161 case "sqrdmlsh_asimdelem_r"_h:
9796 case "asrr_z_p_zz"_h:
9799 case "asr_z_p_zz"_h:
9802 case "lslr_z_p_zz"_h:
9805 case "lsl_z_p_zz"_h:
9808 case "lsrr_z_p_zz"_h:
9811 case "lsr_z_p_zz"_h:
9814 case "sqrshl_z_p_zz"_h:
9819 case "sqrshlr_z_p_zz"_h:
9824 case "sqshl_z_p_zz"_h:
9827 case "sqshlr_z_p_zz"_h:
9830 case "srshl_z_p_zz"_h:
9833 case "srshlr_z_p_zz"_h:
9836 case "uqrshl_z_p_zz"_h:
9841 case "uqrshlr_z_p_zz"_h:
9846 case "uqshl_z_p_zz"_h:
9849 case "uqshlr_z_p_zz"_h:
9852 case "urshl_z_p_zz"_h:
9855 case "urshlr_z_p_zz"_h:
11300 bool reverse = (form_hash_ == "whilege_p_p_rr"_h) ||
11301 (form_hash_ == "whilegt_p_p_rr"_h) ||
11302 (form_hash_ == "whilehi_p_p_rr"_h) ||
11303 (form_hash_ == "whilehs_p_p_rr"_h);
11313 case "whilele_p_p_rr"_h:
11316 case "whilelo_p_p_rr"_h:
11319 case "whilels_p_p_rr"_h:
11322 case "whilelt_p_p_rr"_h:
11325 case "whilege_p_p_rr"_h:
11328 case "whilegt_p_p_rr"_h:
11331 case "whilehi_p_p_rr"_h:
11334 case "whilehs_p_p_rr"_h:
11616 case "sdot_z_zzz"_h:
11619 case "udot_z_zzz"_h:
11622 case "usdot_z_zzz_s"_h:
12472 if ((form_hash_ == "ld1rob_z_p_bi_u8"_h) ||
12473 (form_hash_ == "ld1roh_z_p_bi_u16"_h) ||
12474 (form_hash_ == "ld1row_z_p_bi_u32"_h) ||
12475 (form_hash_ == "ld1rod_z_p_bi_u64"_h)) {
12500 if ((form_hash_ == "ld1rob_z_p_br_contiguous"_h) ||
12501 (form_hash_ == "ld1roh_z_p_br_contiguous"_h) ||
12502 (form_hash_ == "ld1row_z_p_br_contiguous"_h) ||
12503 (form_hash_ == "ld1rod_z_p_br_contiguous"_h)) {
13079 case "sdot_z_zzzi_d"_h:
13080 case "sdot_z_zzzi_s"_h:
13083 case "udot_z_zzzi_d"_h:
13084 case "udot_z_zzzi_s"_h:
13087 case "sudot_z_zzzi_s"_h:
13090 case "usdot_z_zzzi_s"_h:
13108 case "smmla_asimdsame2_g"_h:
13111 case "smmla_z_zzz"_h:
13114 case "ummla_asimdsame2_g"_h:
13117 case "ummla_z_zzz"_h:
13120 case "usmmla_asimdsame2_g"_h:
13123 case "usmmla_z_zzz"_h:
13140 case "fmmla_z_zzz_s"_h:
13141 case "fmmla_z_zzz_d"_h:
13593 case "splice_z_p_zz_des"_h:
13596 case "splice_z_p_zz_con"_h:
13712 case "tbl_z_zz_1"_h:
13715 case "tbl_z_zz_2"_h:
13718 case "tbx_z_zz"_h:
14295 MOPSPHelper<"cpy"_h>(instr);
14300 MOPSPHelper<"cpy"_h>(instr);
14329 VIXL_ASSERT(instr->IsConsistentMOPSTriplet<"cpy"_h>());
14330 VIXL_ASSERT(instr->IsMOPSMainOf(GetLastExecutedInstruction(), "cpy"_h));
14368 VIXL_ASSERT(instr->IsConsistentMOPSTriplet<"cpy"_h>());
14369 VIXL_ASSERT(instr->IsMOPSEpilogueOf(GetLastExecutedInstruction(), "cpy"_h));
14375 MOPSPHelper<"set"_h>(instr);
14380 VIXL_ASSERT(instr->IsConsistentMOPSTriplet<"set"_h>());
14381 VIXL_ASSERT(instr->IsMOPSMainOf(GetLastExecutedInstruction(), "set"_h));
14397 VIXL_ASSERT(instr->IsConsistentMOPSTriplet<"set"_h>());
14398 VIXL_ASSERT(instr->IsMOPSEpilogueOf(GetLastExecutedInstruction(), "set"_h));
14404 MOPSPHelper<"setg"_h>(instr);