Lines Matching refs:Simulator
43 const Instruction* Simulator::kEndOfSimAddress = NULL;
71 const Simulator::FormToVisitorFnMap* Simulator::GetFormToVisitorFnMap() {
73 DEFAULT_FORM_TO_VISITOR_MAP(Simulator),
74 SIM_AUD_VISITOR_MAP(Simulator),
75 {"smlal_asimdelem_l"_h, &Simulator::SimulateNEONMulByElementLong},
76 {"smlsl_asimdelem_l"_h, &Simulator::SimulateNEONMulByElementLong},
77 {"smull_asimdelem_l"_h, &Simulator::SimulateNEONMulByElementLong},
78 {"sqdmlal_asimdelem_l"_h, &Simulator::SimulateNEONMulByElementLong},
79 {"sqdmlsl_asimdelem_l"_h, &Simulator::SimulateNEONMulByElementLong},
80 {"sqdmull_asimdelem_l"_h, &Simulator::SimulateNEONMulByElementLong},
81 {"umlal_asimdelem_l"_h, &Simulator::SimulateNEONMulByElementLong},
82 {"umlsl_asimdelem_l"_h, &Simulator::SimulateNEONMulByElementLong},
83 {"umull_asimdelem_l"_h, &Simulator::SimulateNEONMulByElementLong},
84 {"fcmla_asimdelem_c_h"_h, &Simulator::SimulateNEONComplexMulByElement},
85 {"fcmla_asimdelem_c_s"_h, &Simulator::SimulateNEONComplexMulByElement},
86 {"fmlal2_asimdelem_lh"_h, &Simulator::SimulateNEONFPMulByElementLong},
87 {"fmlal_asimdelem_lh"_h, &Simulator::SimulateNEONFPMulByElementLong},
88 {"fmlsl2_asimdelem_lh"_h, &Simulator::SimulateNEONFPMulByElementLong},
89 {"fmlsl_asimdelem_lh"_h, &Simulator::SimulateNEONFPMulByElementLong},
90 {"fmla_asimdelem_rh_h"_h, &Simulator::SimulateNEONFPMulByElement},
91 {"fmls_asimdelem_rh_h"_h, &Simulator::SimulateNEONFPMulByElement},
92 {"fmulx_asimdelem_rh_h"_h, &Simulator::SimulateNEONFPMulByElement},
93 {"fmul_asimdelem_rh_h"_h, &Simulator::SimulateNEONFPMulByElement},
94 {"fmla_asimdelem_r_sd"_h, &Simulator::SimulateNEONFPMulByElement},
95 {"fmls_asimdelem_r_sd"_h, &Simulator::SimulateNEONFPMulByElement},
96 {"fmulx_asimdelem_r_sd"_h, &Simulator::SimulateNEONFPMulByElement},
97 {"fmul_asimdelem_r_sd"_h, &Simulator::SimulateNEONFPMulByElement},
98 {"sdot_asimdelem_d"_h, &Simulator::SimulateNEONDotProdByElement},
99 {"udot_asimdelem_d"_h, &Simulator::SimulateNEONDotProdByElement},
100 {"adclb_z_zzz"_h, &Simulator::SimulateSVEAddSubCarry},
101 {"adclt_z_zzz"_h, &Simulator::SimulateSVEAddSubCarry},
102 {"addhnb_z_zz"_h, &Simulator::SimulateSVEAddSubHigh},
103 {"addhnt_z_zz"_h, &Simulator::SimulateSVEAddSubHigh},
104 {"addp_z_p_zz"_h, &Simulator::SimulateSVEIntArithPair},
105 {"bcax_z_zzz"_h, &Simulator::SimulateSVEBitwiseTernary},
106 {"bdep_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmT},
107 {"bext_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmT},
108 {"bgrp_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmT},
109 {"bsl1n_z_zzz"_h, &Simulator::SimulateSVEBitwiseTernary},
110 {"bsl2n_z_zzz"_h, &Simulator::SimulateSVEBitwiseTernary},
111 {"bsl_z_zzz"_h, &Simulator::SimulateSVEBitwiseTernary},
112 {"cadd_z_zz"_h, &Simulator::Simulate_ZdnT_ZdnT_ZmT_const},
113 {"cdot_z_zzz"_h, &Simulator::SimulateSVEComplexDotProduct},
114 {"cdot_z_zzzi_d"_h, &Simulator::SimulateSVEComplexDotProduct},
115 {"cdot_z_zzzi_s"_h, &Simulator::SimulateSVEComplexDotProduct},
116 {"cmla_z_zzz"_h, &Simulator::SimulateSVEComplexIntMulAdd},
117 {"cmla_z_zzzi_h"_h, &Simulator::SimulateSVEComplexIntMulAdd},
118 {"cmla_z_zzzi_s"_h, &Simulator::SimulateSVEComplexIntMulAdd},
119 {"eor3_z_zzz"_h, &Simulator::SimulateSVEBitwiseTernary},
120 {"eorbt_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmT},
121 {"eortb_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmT},
122 {"ext_z_zi_con"_h, &Simulator::Simulate_ZdB_Zn1B_Zn2B_imm},
123 {"faddp_z_p_zz"_h, &Simulator::Simulate_ZdnT_PgM_ZdnT_ZmT},
124 {"fcvtlt_z_p_z_h2s"_h, &Simulator::SimulateSVEFPConvertLong},
125 {"fcvtlt_z_p_z_s2d"_h, &Simulator::SimulateSVEFPConvertLong},
126 {"fcvtnt_z_p_z_d2s"_h, &Simulator::Simulate_ZdS_PgM_ZnD},
127 {"fcvtnt_z_p_z_s2h"_h, &Simulator::Simulate_ZdH_PgM_ZnS},
128 {"fcvtx_z_p_z_d2s"_h, &Simulator::Simulate_ZdS_PgM_ZnD},
129 {"fcvtxnt_z_p_z_d2s"_h, &Simulator::Simulate_ZdS_PgM_ZnD},
130 {"flogb_z_p_z"_h, &Simulator::Simulate_ZdT_PgM_ZnT},
131 {"fmaxnmp_z_p_zz"_h, &Simulator::Simulate_ZdnT_PgM_ZdnT_ZmT},
132 {"fmaxp_z_p_zz"_h, &Simulator::Simulate_ZdnT_PgM_ZdnT_ZmT},
133 {"fminnmp_z_p_zz"_h, &Simulator::Simulate_ZdnT_PgM_ZdnT_ZmT},
134 {"fminp_z_p_zz"_h, &Simulator::Simulate_ZdnT_PgM_ZdnT_ZmT},
135 {"fmlalb_z_zzz"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH},
136 {"fmlalb_z_zzzi_s"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH_imm},
137 {"fmlalt_z_zzz"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH},
138 {"fmlalt_z_zzzi_s"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH_imm},
139 {"fmlslb_z_zzz"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH},
140 {"fmlslb_z_zzzi_s"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH_imm},
141 {"fmlslt_z_zzz"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH},
142 {"fmlslt_z_zzzi_s"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH_imm},
143 {"histcnt_z_p_zz"_h, &Simulator::Simulate_ZdT_PgZ_ZnT_ZmT},
144 {"histseg_z_zz"_h, &Simulator::Simulate_ZdB_ZnB_ZmB},
145 {"ldnt1b_z_p_ar_d_64_unscaled"_h, &Simulator::Simulate_ZtD_PgZ_ZnD_Xm},
146 {"ldnt1b_z_p_ar_s_x32_unscaled"_h, &Simulator::Simulate_ZtS_PgZ_ZnS_Xm},
147 {"ldnt1d_z_p_ar_d_64_unscaled"_h, &Simulator::Simulate_ZtD_PgZ_ZnD_Xm},
148 {"ldnt1h_z_p_ar_d_64_unscaled"_h, &Simulator::Simulate_ZtD_PgZ_ZnD_Xm},
149 {"ldnt1h_z_p_ar_s_x32_unscaled"_h, &Simulator::Simulate_ZtS_PgZ_ZnS_Xm},
150 {"ldnt1sb_z_p_ar_d_64_unscaled"_h, &Simulator::Simulate_ZtD_PgZ_ZnD_Xm},
151 {"ldnt1sb_z_p_ar_s_x32_unscaled"_h, &Simulator::Simulate_ZtS_PgZ_ZnS_Xm},
152 {"ldnt1sh_z_p_ar_d_64_unscaled"_h, &Simulator::Simulate_ZtD_PgZ_ZnD_Xm},
153 {"ldnt1sh_z_p_ar_s_x32_unscaled"_h, &Simulator::Simulate_ZtS_PgZ_ZnS_Xm},
154 {"ldnt1sw_z_p_ar_d_64_unscaled"_h, &Simulator::Simulate_ZtD_PgZ_ZnD_Xm},
155 {"ldnt1w_z_p_ar_d_64_unscaled"_h, &Simulator::Simulate_ZtD_PgZ_ZnD_Xm},
156 {"ldnt1w_z_p_ar_s_x32_unscaled"_h, &Simulator::Simulate_ZtS_PgZ_ZnS_Xm},
157 {"match_p_p_zz"_h, &Simulator::Simulate_PdT_PgZ_ZnT_ZmT},
158 {"mla_z_zzzi_d"_h, &Simulator::SimulateSVEMlaMlsIndex},
159 {"mla_z_zzzi_h"_h, &Simulator::SimulateSVEMlaMlsIndex},
160 {"mla_z_zzzi_s"_h, &Simulator::SimulateSVEMlaMlsIndex},
161 {"mls_z_zzzi_d"_h, &Simulator::SimulateSVEMlaMlsIndex},
162 {"mls_z_zzzi_h"_h, &Simulator::SimulateSVEMlaMlsIndex},
163 {"mls_z_zzzi_s"_h, &Simulator::SimulateSVEMlaMlsIndex},
164 {"mul_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmT},
165 {"mul_z_zzi_d"_h, &Simulator::SimulateSVEMulIndex},
166 {"mul_z_zzi_h"_h, &Simulator::SimulateSVEMulIndex},
167 {"mul_z_zzi_s"_h, &Simulator::SimulateSVEMulIndex},
168 {"nbsl_z_zzz"_h, &Simulator::SimulateSVEBitwiseTernary},
169 {"nmatch_p_p_zz"_h, &Simulator::Simulate_PdT_PgZ_ZnT_ZmT},
170 {"pmul_z_zz"_h, &Simulator::Simulate_ZdB_ZnB_ZmB},
171 {"pmullb_z_zz"_h, &Simulator::SimulateSVEIntMulLongVec},
172 {"pmullt_z_zz"_h, &Simulator::SimulateSVEIntMulLongVec},
173 {"raddhnb_z_zz"_h, &Simulator::SimulateSVEAddSubHigh},
174 {"raddhnt_z_zz"_h, &Simulator::SimulateSVEAddSubHigh},
175 {"rshrnb_z_zi"_h, &Simulator::SimulateSVENarrow},
176 {"rshrnt_z_zi"_h, &Simulator::SimulateSVENarrow},
177 {"rsubhnb_z_zz"_h, &Simulator::SimulateSVEAddSubHigh},
178 {"rsubhnt_z_zz"_h, &Simulator::SimulateSVEAddSubHigh},
179 {"saba_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnT_ZmT},
180 {"sabalb_z_zzz"_h, &Simulator::SimulateSVEInterleavedArithLong},
181 {"sabalt_z_zzz"_h, &Simulator::SimulateSVEInterleavedArithLong},
182 {"sabdlb_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
183 {"sabdlt_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
184 {"sadalp_z_p_z"_h, &Simulator::Simulate_ZdaT_PgM_ZnTb},
185 {"saddlb_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
186 {"saddlbt_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
187 {"saddlt_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
188 {"saddwb_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmTb},
189 {"saddwt_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmTb},
190 {"sbclb_z_zzz"_h, &Simulator::SimulateSVEAddSubCarry},
191 {"sbclt_z_zzz"_h, &Simulator::SimulateSVEAddSubCarry},
192 {"shadd_z_p_zz"_h, &Simulator::SimulateSVEHalvingAddSub},
193 {"shrnb_z_zi"_h, &Simulator::SimulateSVENarrow},
194 {"shrnt_z_zi"_h, &Simulator::SimulateSVENarrow},
195 {"shsub_z_p_zz"_h, &Simulator::SimulateSVEHalvingAddSub},
196 {"shsubr_z_p_zz"_h, &Simulator::SimulateSVEHalvingAddSub},
197 {"sli_z_zzi"_h, &Simulator::Simulate_ZdT_ZnT_const},
198 {"smaxp_z_p_zz"_h, &Simulator::SimulateSVEIntArithPair},
199 {"sminp_z_p_zz"_h, &Simulator::SimulateSVEIntArithPair},
200 {"smlalb_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
201 {"smlalb_z_zzzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
202 {"smlalb_z_zzzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
203 {"smlalt_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
204 {"smlalt_z_zzzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
205 {"smlalt_z_zzzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
206 {"smlslb_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
207 {"smlslb_z_zzzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
208 {"smlslb_z_zzzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
209 {"smlslt_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
210 {"smlslt_z_zzzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
211 {"smlslt_z_zzzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
212 {"smulh_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmT},
213 {"smullb_z_zz"_h, &Simulator::SimulateSVEIntMulLongVec},
214 {"smullb_z_zzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
215 {"smullb_z_zzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
216 {"smullt_z_zz"_h, &Simulator::SimulateSVEIntMulLongVec},
217 {"smullt_z_zzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
218 {"smullt_z_zzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
219 {"splice_z_p_zz_con"_h, &Simulator::VisitSVEVectorSplice},
220 {"sqabs_z_p_z"_h, &Simulator::Simulate_ZdT_PgM_ZnT},
221 {"sqadd_z_p_zz"_h, &Simulator::SimulateSVESaturatingArithmetic},
222 {"sqcadd_z_zz"_h, &Simulator::Simulate_ZdnT_ZdnT_ZmT_const},
223 {"sqdmlalb_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
224 {"sqdmlalb_z_zzzi_d"_h, &Simulator::Simulate_ZdaD_ZnS_ZmS_imm},
225 {"sqdmlalb_z_zzzi_s"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH_imm},
226 {"sqdmlalbt_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
227 {"sqdmlalt_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
228 {"sqdmlalt_z_zzzi_d"_h, &Simulator::Simulate_ZdaD_ZnS_ZmS_imm},
229 {"sqdmlalt_z_zzzi_s"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH_imm},
230 {"sqdmlslb_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
231 {"sqdmlslb_z_zzzi_d"_h, &Simulator::Simulate_ZdaD_ZnS_ZmS_imm},
232 {"sqdmlslb_z_zzzi_s"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH_imm},
233 {"sqdmlslbt_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
234 {"sqdmlslt_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
235 {"sqdmlslt_z_zzzi_d"_h, &Simulator::Simulate_ZdaD_ZnS_ZmS_imm},
236 {"sqdmlslt_z_zzzi_s"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH_imm},
237 {"sqdmulh_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmT},
238 {"sqdmulh_z_zzi_d"_h, &Simulator::SimulateSVESaturatingMulHighIndex},
239 {"sqdmulh_z_zzi_h"_h, &Simulator::SimulateSVESaturatingMulHighIndex},
240 {"sqdmulh_z_zzi_s"_h, &Simulator::SimulateSVESaturatingMulHighIndex},
241 {"sqdmullb_z_zz"_h, &Simulator::SimulateSVEIntMulLongVec},
242 {"sqdmullb_z_zzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
243 {"sqdmullb_z_zzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
244 {"sqdmullt_z_zz"_h, &Simulator::SimulateSVEIntMulLongVec},
245 {"sqdmullt_z_zzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
246 {"sqdmullt_z_zzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
247 {"sqneg_z_p_z"_h, &Simulator::Simulate_ZdT_PgM_ZnT},
248 {"sqrdcmlah_z_zzz"_h, &Simulator::SimulateSVEComplexIntMulAdd},
249 {"sqrdcmlah_z_zzzi_h"_h, &Simulator::SimulateSVEComplexIntMulAdd},
250 {"sqrdcmlah_z_zzzi_s"_h, &Simulator::SimulateSVEComplexIntMulAdd},
251 {"sqrdmlah_z_zzz"_h, &Simulator::SimulateSVESaturatingMulAddHigh},
252 {"sqrdmlah_z_zzzi_d"_h, &Simulator::SimulateSVESaturatingMulAddHigh},
253 {"sqrdmlah_z_zzzi_h"_h, &Simulator::SimulateSVESaturatingMulAddHigh},
254 {"sqrdmlah_z_zzzi_s"_h, &Simulator::SimulateSVESaturatingMulAddHigh},
255 {"sqrdmlsh_z_zzz"_h, &Simulator::SimulateSVESaturatingMulAddHigh},
256 {"sqrdmlsh_z_zzzi_d"_h, &Simulator::SimulateSVESaturatingMulAddHigh},
257 {"sqrdmlsh_z_zzzi_h"_h, &Simulator::SimulateSVESaturatingMulAddHigh},
258 {"sqrdmlsh_z_zzzi_s"_h, &Simulator::SimulateSVESaturatingMulAddHigh},
259 {"sqrdmulh_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmT},
260 {"sqrdmulh_z_zzi_d"_h, &Simulator::SimulateSVESaturatingMulHighIndex},
261 {"sqrdmulh_z_zzi_h"_h, &Simulator::SimulateSVESaturatingMulHighIndex},
262 {"sqrdmulh_z_zzi_s"_h, &Simulator::SimulateSVESaturatingMulHighIndex},
263 {"sqrshl_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
264 {"sqrshlr_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
265 {"sqrshrnb_z_zi"_h, &Simulator::SimulateSVENarrow},
266 {"sqrshrnt_z_zi"_h, &Simulator::SimulateSVENarrow},
267 {"sqrshrunb_z_zi"_h, &Simulator::SimulateSVENarrow},
268 {"sqrshrunt_z_zi"_h, &Simulator::SimulateSVENarrow},
269 {"sqshl_z_p_zi"_h, &Simulator::Simulate_ZdnT_PgM_ZdnT_const},
270 {"sqshl_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
271 {"sqshlr_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
272 {"sqshlu_z_p_zi"_h, &Simulator::Simulate_ZdnT_PgM_ZdnT_const},
273 {"sqshrnb_z_zi"_h, &Simulator::SimulateSVENarrow},
274 {"sqshrnt_z_zi"_h, &Simulator::SimulateSVENarrow},
275 {"sqshrunb_z_zi"_h, &Simulator::SimulateSVENarrow},
276 {"sqshrunt_z_zi"_h, &Simulator::SimulateSVENarrow},
277 {"sqsub_z_p_zz"_h, &Simulator::SimulateSVESaturatingArithmetic},
278 {"sqsubr_z_p_zz"_h, &Simulator::SimulateSVESaturatingArithmetic},
279 {"sqxtnb_z_zz"_h, &Simulator::SimulateSVENarrow},
280 {"sqxtnt_z_zz"_h, &Simulator::SimulateSVENarrow},
281 {"sqxtunb_z_zz"_h, &Simulator::SimulateSVENarrow},
282 {"sqxtunt_z_zz"_h, &Simulator::SimulateSVENarrow},
283 {"srhadd_z_p_zz"_h, &Simulator::SimulateSVEHalvingAddSub},
284 {"sri_z_zzi"_h, &Simulator::Simulate_ZdT_ZnT_const},
285 {"srshl_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
286 {"srshlr_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
287 {"srshr_z_p_zi"_h, &Simulator::Simulate_ZdnT_PgM_ZdnT_const},
288 {"srsra_z_zi"_h, &Simulator::Simulate_ZdaT_ZnT_const},
289 {"sshllb_z_zi"_h, &Simulator::SimulateSVEShiftLeftImm},
290 {"sshllt_z_zi"_h, &Simulator::SimulateSVEShiftLeftImm},
291 {"ssra_z_zi"_h, &Simulator::Simulate_ZdaT_ZnT_const},
292 {"ssublb_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
293 {"ssublbt_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
294 {"ssublt_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
295 {"ssubltb_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
296 {"ssubwb_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmTb},
297 {"ssubwt_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmTb},
298 {"stnt1b_z_p_ar_d_64_unscaled"_h, &Simulator::Simulate_ZtD_Pg_ZnD_Xm},
299 {"stnt1b_z_p_ar_s_x32_unscaled"_h, &Simulator::Simulate_ZtS_Pg_ZnS_Xm},
300 {"stnt1d_z_p_ar_d_64_unscaled"_h, &Simulator::Simulate_ZtD_Pg_ZnD_Xm},
301 {"stnt1h_z_p_ar_d_64_unscaled"_h, &Simulator::Simulate_ZtD_Pg_ZnD_Xm},
302 {"stnt1h_z_p_ar_s_x32_unscaled"_h, &Simulator::Simulate_ZtS_Pg_ZnS_Xm},
303 {"stnt1w_z_p_ar_d_64_unscaled"_h, &Simulator::Simulate_ZtD_Pg_ZnD_Xm},
304 {"stnt1w_z_p_ar_s_x32_unscaled"_h, &Simulator::Simulate_ZtS_Pg_ZnS_Xm},
305 {"subhnb_z_zz"_h, &Simulator::SimulateSVEAddSubHigh},
306 {"subhnt_z_zz"_h, &Simulator::SimulateSVEAddSubHigh},
307 {"suqadd_z_p_zz"_h, &Simulator::SimulateSVESaturatingArithmetic},
308 {"tbl_z_zz_2"_h, &Simulator::VisitSVETableLookup},
309 {"tbx_z_zz"_h, &Simulator::VisitSVETableLookup},
310 {"uaba_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnT_ZmT},
311 {"uabalb_z_zzz"_h, &Simulator::SimulateSVEInterleavedArithLong},
312 {"uabalt_z_zzz"_h, &Simulator::SimulateSVEInterleavedArithLong},
313 {"uabdlb_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
314 {"uabdlt_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
315 {"uadalp_z_p_z"_h, &Simulator::Simulate_ZdaT_PgM_ZnTb},
316 {"uaddlb_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
317 {"uaddlt_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
318 {"uaddwb_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmTb},
319 {"uaddwt_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmTb},
320 {"uhadd_z_p_zz"_h, &Simulator::SimulateSVEHalvingAddSub},
321 {"uhsub_z_p_zz"_h, &Simulator::SimulateSVEHalvingAddSub},
322 {"uhsubr_z_p_zz"_h, &Simulator::SimulateSVEHalvingAddSub},
323 {"umaxp_z_p_zz"_h, &Simulator::SimulateSVEIntArithPair},
324 {"uminp_z_p_zz"_h, &Simulator::SimulateSVEIntArithPair},
325 {"umlalb_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
326 {"umlalb_z_zzzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
327 {"umlalb_z_zzzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
328 {"umlalt_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
329 {"umlalt_z_zzzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
330 {"umlalt_z_zzzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
331 {"umlslb_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
332 {"umlslb_z_zzzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
333 {"umlslb_z_zzzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
334 {"umlslt_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
335 {"umlslt_z_zzzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
336 {"umlslt_z_zzzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
337 {"umulh_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmT},
338 {"umullb_z_zz"_h, &Simulator::SimulateSVEIntMulLongVec},
339 {"umullb_z_zzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
340 {"umullb_z_zzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
341 {"umullt_z_zz"_h, &Simulator::SimulateSVEIntMulLongVec},
342 {"umullt_z_zzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
343 {"umullt_z_zzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
344 {"uqadd_z_p_zz"_h, &Simulator::SimulateSVESaturatingArithmetic},
345 {"uqrshl_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
346 {"uqrshlr_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
347 {"uqrshrnb_z_zi"_h, &Simulator::SimulateSVENarrow},
348 {"uqrshrnt_z_zi"_h, &Simulator::SimulateSVENarrow},
349 {"uqshl_z_p_zi"_h, &Simulator::Simulate_ZdnT_PgM_ZdnT_const},
350 {"uqshl_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
351 {"uqshlr_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
352 {"uqshrnb_z_zi"_h, &Simulator::SimulateSVENarrow},
353 {"uqshrnt_z_zi"_h, &Simulator::SimulateSVENarrow},
354 {"uqsub_z_p_zz"_h, &Simulator::SimulateSVESaturatingArithmetic},
355 {"uqsubr_z_p_zz"_h, &Simulator::SimulateSVESaturatingArithmetic},
356 {"uqxtnb_z_zz"_h, &Simulator::SimulateSVENarrow},
357 {"uqxtnt_z_zz"_h, &Simulator::SimulateSVENarrow},
358 {"urecpe_z_p_z"_h, &Simulator::Simulate_ZdS_PgM_ZnS},
359 {"urhadd_z_p_zz"_h, &Simulator::SimulateSVEHalvingAddSub},
360 {"urshl_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
361 {"urshlr_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
362 {"urshr_z_p_zi"_h, &Simulator::Simulate_ZdnT_PgM_ZdnT_const},
363 {"ursqrte_z_p_z"_h, &Simulator::Simulate_ZdS_PgM_ZnS},
364 {"ursra_z_zi"_h, &Simulator::Simulate_ZdaT_ZnT_const},
365 {"ushllb_z_zi"_h, &Simulator::SimulateSVEShiftLeftImm},
366 {"ushllt_z_zi"_h, &Simulator::SimulateSVEShiftLeftImm},
367 {"usqadd_z_p_zz"_h, &Simulator::SimulateSVESaturatingArithmetic},
368 {"usra_z_zi"_h, &Simulator::Simulate_ZdaT_ZnT_const},
369 {"usublb_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
370 {"usublt_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
371 {"usubwb_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmTb},
372 {"usubwt_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmTb},
373 {"whilege_p_p_rr"_h, &Simulator::VisitSVEIntCompareScalarCountAndLimit},
374 {"whilegt_p_p_rr"_h, &Simulator::VisitSVEIntCompareScalarCountAndLimit},
375 {"whilehi_p_p_rr"_h, &Simulator::VisitSVEIntCompareScalarCountAndLimit},
376 {"whilehs_p_p_rr"_h, &Simulator::VisitSVEIntCompareScalarCountAndLimit},
377 {"whilerw_p_rr"_h, &Simulator::Simulate_PdT_Xn_Xm},
378 {"whilewr_p_rr"_h, &Simulator::Simulate_PdT_Xn_Xm},
379 {"xar_z_zzi"_h, &Simulator::SimulateSVEExclusiveOrRotate},
380 {"smmla_z_zzz"_h, &Simulator::SimulateMatrixMul},
381 {"ummla_z_zzz"_h, &Simulator::SimulateMatrixMul},
382 {"usmmla_z_zzz"_h, &Simulator::SimulateMatrixMul},
383 {"smmla_asimdsame2_g"_h, &Simulator::SimulateMatrixMul},
384 {"ummla_asimdsame2_g"_h, &Simulator::SimulateMatrixMul},
385 {"usmmla_asimdsame2_g"_h, &Simulator::SimulateMatrixMul},
386 {"fmmla_z_zzz_s"_h, &Simulator::SimulateSVEFPMatrixMul},
387 {"fmmla_z_zzz_d"_h, &Simulator::SimulateSVEFPMatrixMul},
389 &Simulator::VisitSVELoadAndBroadcastQOWord_ScalarPlusImm},
391 &Simulator::VisitSVELoadAndBroadcastQOWord_ScalarPlusScalar},
393 &Simulator::VisitSVELoadAndBroadcastQOWord_ScalarPlusImm},
395 &Simulator::VisitSVELoadAndBroadcastQOWord_ScalarPlusScalar},
397 &Simulator::VisitSVELoadAndBroadcastQOWord_ScalarPlusImm},
399 &Simulator::VisitSVELoadAndBroadcastQOWord_ScalarPlusScalar},
401 &Simulator::VisitSVELoadAndBroadcastQOWord_ScalarPlusImm},
403 &Simulator::VisitSVELoadAndBroadcastQOWord_ScalarPlusScalar},
404 {"usdot_z_zzz_s"_h, &Simulator::VisitSVEIntMulAddUnpredicated},
405 {"sudot_z_zzzi_s"_h, &Simulator::VisitSVEMulIndex},
406 {"usdot_z_zzzi_s"_h, &Simulator::VisitSVEMulIndex},
407 {"usdot_asimdsame2_d"_h, &Simulator::VisitNEON3SameExtra},
408 {"sudot_asimdelem_d"_h, &Simulator::SimulateNEONDotProdByElement},
409 {"usdot_asimdelem_d"_h, &Simulator::SimulateNEONDotProdByElement},
410 {"addg_64_addsub_immtags"_h, &Simulator::SimulateMTEAddSubTag},
411 {"gmi_64g_dp_2src"_h, &Simulator::SimulateMTETagMaskInsert},
412 {"irg_64i_dp_2src"_h, &Simulator::Simulate_XdSP_XnSP_Xm},
413 {"ldg_64loffset_ldsttags"_h, &Simulator::SimulateMTELoadTag},
414 {"st2g_64soffset_ldsttags"_h, &Simulator::Simulator::SimulateMTEStoreTag},
415 {"st2g_64spost_ldsttags"_h, &Simulator::Simulator::SimulateMTEStoreTag},
416 {"st2g_64spre_ldsttags"_h, &Simulator::Simulator::SimulateMTEStoreTag},
417 {"stgp_64_ldstpair_off"_h, &Simulator::SimulateMTEStoreTagPair},
418 {"stgp_64_ldstpair_post"_h, &Simulator::SimulateMTEStoreTagPair},
419 {"stgp_64_ldstpair_pre"_h, &Simulator::SimulateMTEStoreTagPair},
420 {"stg_64soffset_ldsttags"_h, &Simulator::Simulator::SimulateMTEStoreTag},
421 {"stg_64spost_ldsttags"_h, &Simulator::Simulator::SimulateMTEStoreTag},
422 {"stg_64spre_ldsttags"_h, &Simulator::Simulator::SimulateMTEStoreTag},
424 &Simulator::Simulator::SimulateMTEStoreTag},
425 {"stz2g_64spost_ldsttags"_h, &Simulator::Simulator::SimulateMTEStoreTag},
426 {"stz2g_64spre_ldsttags"_h, &Simulator::Simulator::SimulateMTEStoreTag},
427 {"stzg_64soffset_ldsttags"_h, &Simulator::Simulator::SimulateMTEStoreTag},
428 {"stzg_64spost_ldsttags"_h, &Simulator::Simulator::SimulateMTEStoreTag},
429 {"stzg_64spre_ldsttags"_h, &Simulator::Simulator::SimulateMTEStoreTag},
430 {"subg_64_addsub_immtags"_h, &Simulator::SimulateMTEAddSubTag},
431 {"subps_64s_dp_2src"_h, &Simulator::SimulateMTESubPointer},
432 {"subp_64s_dp_2src"_h, &Simulator::SimulateMTESubPointer},
433 {"cpyen_cpy_memcms"_h, &Simulator::SimulateCpyE},
434 {"cpyern_cpy_memcms"_h, &Simulator::SimulateCpyE},
435 {"cpyewn_cpy_memcms"_h, &Simulator::SimulateCpyE},
436 {"cpye_cpy_memcms"_h, &Simulator::SimulateCpyE},
437 {"cpyfen_cpy_memcms"_h, &Simulator::SimulateCpyE},
438 {"cpyfern_cpy_memcms"_h, &Simulator::SimulateCpyE},
439 {"cpyfewn_cpy_memcms"_h, &Simulator::SimulateCpyE},
440 {"cpyfe_cpy_memcms"_h, &Simulator::SimulateCpyE},
441 {"cpyfmn_cpy_memcms"_h, &Simulator::SimulateCpyM},
442 {"cpyfmrn_cpy_memcms"_h, &Simulator::SimulateCpyM},
443 {"cpyfmwn_cpy_memcms"_h, &Simulator::SimulateCpyM},
444 {"cpyfm_cpy_memcms"_h, &Simulator::SimulateCpyM},
445 {"cpyfpn_cpy_memcms"_h, &Simulator::SimulateCpyFP},
446 {"cpyfprn_cpy_memcms"_h, &Simulator::SimulateCpyFP},
447 {"cpyfpwn_cpy_memcms"_h, &Simulator::SimulateCpyFP},
448 {"cpyfp_cpy_memcms"_h, &Simulator::SimulateCpyFP},
449 {"cpymn_cpy_memcms"_h, &Simulator::SimulateCpyM},
450 {"cpymrn_cpy_memcms"_h, &Simulator::SimulateCpyM},
451 {"cpymwn_cpy_memcms"_h, &Simulator::SimulateCpyM},
452 {"cpym_cpy_memcms"_h, &Simulator::SimulateCpyM},
453 {"cpypn_cpy_memcms"_h, &Simulator::SimulateCpyP},
454 {"cpyprn_cpy_memcms"_h, &Simulator::SimulateCpyP},
455 {"cpypwn_cpy_memcms"_h, &Simulator::SimulateCpyP},
456 {"cpyp_cpy_memcms"_h, &Simulator::SimulateCpyP},
457 {"setp_set_memcms"_h, &Simulator::SimulateSetP},
458 {"setpn_set_memcms"_h, &Simulator::SimulateSetP},
459 {"setgp_set_memcms"_h, &Simulator::SimulateSetGP},
460 {"setgpn_set_memcms"_h, &Simulator::SimulateSetGP},
461 {"setm_set_memcms"_h, &Simulator::SimulateSetM},
462 {"setmn_set_memcms"_h, &Simulator::SimulateSetM},
463 {"setgm_set_memcms"_h, &Simulator::SimulateSetGM},
464 {"setgmn_set_memcms"_h, &Simulator::SimulateSetGM},
465 {"sete_set_memcms"_h, &Simulator::SimulateSetE},
466 {"seten_set_memcms"_h, &Simulator::SimulateSetE},
467 {"setge_set_memcms"_h, &Simulator::SimulateSetE},
468 {"setgen_set_memcms"_h, &Simulator::SimulateSetE},
469 {"abs_32_dp_1src"_h, &Simulator::VisitDataProcessing1Source},
470 {"abs_64_dp_1src"_h, &Simulator::VisitDataProcessing1Source},
471 {"cnt_32_dp_1src"_h, &Simulator::VisitDataProcessing1Source},
472 {"cnt_64_dp_1src"_h, &Simulator::VisitDataProcessing1Source},
473 {"ctz_32_dp_1src"_h, &Simulator::VisitDataProcessing1Source},
474 {"ctz_64_dp_1src"_h, &Simulator::VisitDataProcessing1Source},
475 {"smax_32_dp_2src"_h, &Simulator::SimulateSignedMinMax},
476 {"smax_64_dp_2src"_h, &Simulator::SimulateSignedMinMax},
477 {"smin_32_dp_2src"_h, &Simulator::SimulateSignedMinMax},
478 {"smin_64_dp_2src"_h, &Simulator::SimulateSignedMinMax},
479 {"smax_32_minmax_imm"_h, &Simulator::SimulateSignedMinMax},
480 {"smax_64_minmax_imm"_h, &Simulator::SimulateSignedMinMax},
481 {"smin_32_minmax_imm"_h, &Simulator::SimulateSignedMinMax},
482 {"smin_64_minmax_imm"_h, &Simulator::SimulateSignedMinMax},
483 {"umax_32_dp_2src"_h, &Simulator::SimulateUnsignedMinMax},
484 {"umax_64_dp_2src"_h, &Simulator::SimulateUnsignedMinMax},
485 {"umin_32_dp_2src"_h, &Simulator::SimulateUnsignedMinMax},
486 {"umin_64_dp_2src"_h, &Simulator::SimulateUnsignedMinMax},
487 {"umax_32u_minmax_imm"_h, &Simulator::SimulateUnsignedMinMax},
488 {"umax_64u_minmax_imm"_h, &Simulator::SimulateUnsignedMinMax},
489 {"umin_32u_minmax_imm"_h, &Simulator::SimulateUnsignedMinMax},
490 {"umin_64u_minmax_imm"_h, &Simulator::SimulateUnsignedMinMax},
496 Simulator::Simulator(Decoder* decoder, FILE* stream, SimStack::Allocated stack)
501 Simulator::Simulator(PandaAllocator* allocator, Decoder* decoder, SimStack::Allocated stack, FILE* stream)
529 // The Simulator and Disassembler share the same available list, held by the
572 void Simulator::ResetSystemRegisters() {
579 void Simulator::ResetRegisters() {
583 // Returning to address 0 exits the Simulator.
587 void Simulator::ResetVRegisters() {
606 void Simulator::ResetPRegisters() {
622 void Simulator::ResetFFR() {
628 void Simulator::ResetState() {
646 void Simulator::SetVectorLengthInBits(unsigned vector_length) {
666 Simulator::~Simulator() {
678 void Simulator::Run() {
702 void Simulator::RunFrom(const Instruction* first) {
709 const char* Simulator::xreg_names[] = {"x0", "x1", "x2", "x3", "x4", "x5",
716 const char* Simulator::wreg_names[] = {"w0", "w1", "w2", "w3", "w4", "w5",
723 const char* Simulator::breg_names[] = {"b0", "b1", "b2", "b3", "b4", "b5",
730 const char* Simulator::hreg_names[] = {"h0", "h1", "h2", "h3", "h4", "h5",
737 const char* Simulator::sreg_names[] = {"s0", "s1", "s2", "s3", "s4", "s5",
744 const char* Simulator::dreg_names[] = {"d0", "d1", "d2", "d3", "d4", "d5",
751 const char* Simulator::vreg_names[] = {"v0", "v1", "v2", "v3", "v4", "v5",
758 const char* Simulator::zreg_names[] = {"z0", "z1", "z2", "z3", "z4", "z5",
765 const char* Simulator::preg_names[] = {"p0", "p1", "p2", "p3", "p4", "p5",
771 const char* Simulator::WRegNameForCode(unsigned code, Reg31Mode mode) {
782 const char* Simulator::XRegNameForCode(unsigned code, Reg31Mode mode) {
793 const char* Simulator::BRegNameForCode(unsigned code) {
799 const char* Simulator::HRegNameForCode(unsigned code) {
805 const char* Simulator::SRegNameForCode(unsigned code) {
811 const char* Simulator::DRegNameForCode(unsigned code) {
817 const char* Simulator::VRegNameForCode(unsigned code) {
823 const char* Simulator::ZRegNameForCode(unsigned code) {
829 const char* Simulator::PRegNameForCode(unsigned code) {
834 SimVRegister Simulator::ExpandToSimVRegister(const SimPRegister& pg) {
841 void Simulator::ExtractFromSimVRegister(VectorFormat vform,
868 void Simulator::SetColouredTrace(bool value) {
896 void Simulator::SetTraceParameters(int parameters) {
911 uint64_t Simulator::AddWithCarry(unsigned reg_size,
929 std::pair<uint64_t, uint8_t> Simulator::AddWithCarry(unsigned reg_size,
966 vixl_uint128_t Simulator::Add128(vixl_uint128_t x, vixl_uint128_t y) {
975 vixl_uint128_t Simulator::Neg128(vixl_uint128_t x) {
983 vixl_uint128_t Simulator::Mul64(uint64_t x, uint64_t y) {
1013 int64_t Simulator::ShiftOperand(unsigned reg_size,
1065 int64_t Simulator::ExtendValue(unsigned reg_size,
1107 void Simulator::FPCompare(double val0, double val1, FPTrapFlags trap) {
1133 uint64_t Simulator::ComputeMemOperandAddress(const MemOperand& mem_op) const {
1153 Simulator::PrintRegisterFormat Simulator::GetPrintRegisterFormatForSize(
1202 Simulator::PrintRegisterFormat Simulator::GetPrintRegisterFormat(
1246 Simulator::PrintRegisterFormat Simulator::GetPrintRegisterFormatFP(
1273 void Simulator::PrintRegisters() {
1280 void Simulator::PrintVRegisters() {
1286 void Simulator::PrintZRegisters() {
1292 void Simulator::PrintWrittenRegisters() {
1301 void Simulator::PrintWrittenVRegisters() {
1316 void Simulator::PrintWrittenPRegisters() {
1328 void Simulator::PrintSystemRegisters() {
1333 void Simulator::PrintRegisterValue(const uint8_t* value,
1351 void Simulator::PrintRegisterValueFPAnnotations(const uint8_t* value,
1411 void Simulator::PrintRegister(int code,
1472 void Simulator::PrintVRegister(int code,
1540 void Simulator::PrintVRegistersForStructuredAccess(int rt_code,
1559 void Simulator::PrintZRegistersForStructuredAccess(int rt_code,
1586 void Simulator::PrintZRegister(int code, PrintRegisterFormat format) {
1598 void Simulator::PrintPRegister(int code, PrintRegisterFormat format) {
1610 void Simulator::PrintFFR(PrintRegisterFormat format) {
1623 void Simulator::PrintPartialZRegister(int code,
1663 void Simulator::PrintPartialPRegister(const char* name,
1701 void Simulator::PrintPartialPRegister(int code,
1713 void Simulator::PrintSystemRegister(SystemRegister id) {
1748 uint16_t Simulator::PrintPartialAccess(uint16_t access_mask,
1808 void Simulator::PrintAccess(int code,
1832 void Simulator::PrintVAccess(int code,
1851 void Simulator::PrintVStructAccess(int rt_code,
1881 void Simulator::PrintVSingleStructAccess(int rt_code,
1900 void Simulator::PrintVReplicatingStructAccess(int rt_code,
1918 void Simulator::PrintZAccess(int rt_code, const char* op, uintptr_t address) {
1943 void Simulator::PrintZStructAccess(int rt_code,
2002 void Simulator::PrintPAccess(int code, const char* op, uintptr_t address) {
2027 void Simulator::PrintMemTransfer(uintptr_t dst, uintptr_t src, uint8_t value) {
2045 void Simulator::PrintRead(int rt_code,
2055 void Simulator::PrintExtendingRead(int rt_code,
2083 void Simulator::PrintVRead(int rt_code,
2091 void Simulator::PrintWrite(int rt_code,
2104 void Simulator::PrintVWrite(int rt_code,
2116 void Simulator::PrintTakenBranch(const Instruction* target) {
2127 void Simulator::Visit(Metadata* metadata, const Instruction* instr) {
2131 const FormToVisitorFnMap* fv = Simulator::GetFormToVisitorFnMap();
2140 void Simulator::Simulate_PdT_PgZ_ZnT_ZmT(const Instruction* instr) {
2161 void Simulator::Simulate_PdT_Xn_Xm(const Instruction* instr) {
2192 void Simulator::Simulate_ZdB_Zn1B_Zn2B_imm(const Instruction* instr) {
2206 void Simulator::Simulate_ZdB_ZnB_ZmB(const Instruction* instr) {
2232 void Simulator::SimulateSVEMulIndex(const Instruction* instr) {
2251 void Simulator::SimulateSVEMlaMlsIndex(const Instruction* instr) {
2275 void Simulator::SimulateSVESaturatingMulHighIndex(const Instruction* instr) {
2305 void Simulator::SimulateSVESaturatingIntMulLongIdx(const Instruction* instr) {
2388 void Simulator::Simulate_ZdH_PgM_ZnS(const Instruction* instr) {
2408 void Simulator::Simulate_ZdS_PgM_ZnD(const Instruction* instr) {
2437 void Simulator::SimulateSVEFPConvertLong(const Instruction* instr) {
2457 void Simulator::Simulate_ZdS_PgM_ZnS(const Instruction* instr) {
2481 void Simulator::Simulate_ZdT_PgM_ZnT(const Instruction* instr) {
2505 void Simulator::Simulate_ZdT_PgZ_ZnT_ZmT(const Instruction* instr) {
2522 void Simulator::Simulate_ZdT_ZnT_ZmT(const Instruction* instr) {
2570 void Simulator::Simulate_ZdT_ZnT_ZmTb(const Instruction* instr) {
2611 void Simulator::Simulate_ZdT_ZnT_const(const Instruction* instr) {
2638 void Simulator::SimulateSVENarrow(const Instruction* instr) {
2735 void Simulator::SimulateSVEInterleavedArithLong(const Instruction* instr) {
2813 void Simulator::SimulateSVEIntMulLongVec(const Instruction* instr) {
2863 void Simulator::SimulateSVEAddSubHigh(const Instruction* instr) {
2917 void Simulator::SimulateSVEShiftLeftImm(const Instruction* instr) {
2955 void Simulator::SimulateSVESaturatingMulAddHigh(const Instruction* instr) {
3011 void Simulator::Simulate_ZdaD_ZnS_ZmS_imm(const Instruction* instr) {
3041 void Simulator::Simulate_ZdaS_ZnH_ZmH(const Instruction* instr) {
3070 void Simulator::Simulate_ZdaS_ZnH_ZmH_imm(const Instruction* instr) {
3112 void Simulator::Simulate_ZdaT_PgM_ZnTb(const Instruction* instr) {
3132 void Simulator::SimulateSVEAddSubCarry(const Instruction* instr) {
3159 void Simulator::Simulate_ZdaT_ZnT_ZmT(const Instruction* instr) {
3177 void Simulator::SimulateSVEComplexIntMulAdd(const Instruction* instr) {
3215 void Simulator::Simulate_ZdaT_ZnT_const(const Instruction* instr) {
3245 void Simulator::Simulate_ZdaT_ZnTb_ZmTb(const Instruction* instr) {
3308 void Simulator::SimulateSVEComplexDotProduct(const Instruction* instr) {
3338 void Simulator::SimulateSVEBitwiseTernary(const Instruction* instr) {
3374 void Simulator::SimulateSVEHalvingAddSub(const Instruction* instr) {
3413 void Simulator::SimulateSVESaturatingArithmetic(const Instruction* instr) {
3452 void Simulator::SimulateSVEIntArithPair(const Instruction* instr) {
3482 void Simulator::Simulate_ZdnT_PgM_ZdnT_ZmT(const Instruction* instr) {
3511 void Simulator::Simulate_ZdnT_PgM_ZdnT_const(const Instruction* instr) {
3545 void Simulator::SimulateSVEExclusiveOrRotate(const Instruction* instr) {
3561 void Simulator::Simulate_ZdnT_ZdnT_ZmT_const(const Instruction* instr) {
3579 void Simulator::Simulate_ZtD_PgZ_ZnD_Xm(const Instruction* instr) {
3620 void Simulator::Simulate_ZtD_Pg_ZnD_Xm(const Instruction* instr) {
3636 void Simulator::Simulate_ZtS_PgZ_ZnS_Xm(const Instruction* instr) {
3670 void Simulator::Simulate_ZtS_Pg_ZnS_Xm(const Instruction* instr) {
3685 void Simulator::VisitReserved(const Instruction* instr) {
3696 void Simulator::VisitUnimplemented(const Instruction* instr) {
3704 void Simulator::VisitUnallocated(const Instruction* instr) {
3712 void Simulator::VisitPCRelAddressing(const Instruction* instr) {
3720 void Simulator::VisitUnconditionalBranch(const Instruction* instr) {
3734 void Simulator::VisitConditionalBranch(const Instruction* instr) {
3741 BType Simulator::GetBTypeFromInstruction(const Instruction* instr) const {
3763 void Simulator::VisitUnconditionalBranchToRegister(const Instruction* instr) {
3844 void Simulator::VisitTestBranch(const Instruction* instr) {
3865 void Simulator::VisitCompareBranch(const Instruction* instr) {
3890 void Simulator::AddSubHelper(const Instruction* instr, int64_t op2) {
3930 void Simulator::VisitAddSubShifted(const Instruction* instr) {
3943 void Simulator::VisitAddSubImmediate(const Instruction* instr) {
3950 void Simulator::VisitAddSubExtended(const Instruction* instr) {
3960 void Simulator::VisitAddSubWithCarry(const Instruction* instr) {
3980 void Simulator::VisitRotateRightIntoFlags(const Instruction* instr) {
3995 void Simulator::VisitEvaluateIntoFlags(const Instruction* instr) {
4007 void Simulator::VisitLogicalShifted(const Instruction* instr) {
4022 void Simulator::VisitLogicalImmediate(const Instruction* instr) {
4031 void Simulator::LogicalHelper(const Instruction* instr, int64_t op2) {
4072 void Simulator::VisitConditionalCompareRegister(const Instruction* instr) {
4078 void Simulator::VisitConditionalCompareImmediate(const Instruction* instr) {
4083 void Simulator::ConditionalCompareHelper(const Instruction* instr,
4105 void Simulator::VisitLoadStoreUnsignedOffset(const Instruction* instr) {
4111 void Simulator::VisitLoadStoreUnscaledOffset(const Instruction* instr) {
4116 void Simulator::VisitLoadStorePreIndex(const Instruction* instr) {
4121 void Simulator::VisitLoadStorePostIndex(const Instruction* instr) {
4127 void Simulator::LoadAcquireRCpcUnscaledOffsetHelper(const Instruction* instr) {
4154 void Simulator::StoreReleaseUnscaledOffsetHelper(const Instruction* instr) {
4180 void Simulator::VisitLoadStoreRCpcUnscaledOffset(const Instruction* instr) {
4225 void Simulator::VisitLoadStorePAC(const Instruction* instr) {
4267 void Simulator::VisitLoadStoreRegisterOffset(const Instruction* instr) {
4278 void Simulator::LoadStoreHelper(const Instruction* instr,
4414 void Simulator::VisitLoadStorePairOffset(const Instruction* instr) {
4419 void Simulator::VisitLoadStorePairPreIndex(const Instruction* instr) {
4424 void Simulator::VisitLoadStorePairPostIndex(const Instruction* instr) {
4429 void Simulator::VisitLoadStorePairNonTemporal(const Instruction* instr) {
4434 void Simulator::LoadStorePairHelper(const Instruction* instr,
4552 void Simulator::CompareAndSwapHelper(const Instruction* instr) {
4592 void Simulator::CompareAndSwapPairHelper(const Instruction* instr) {
4652 bool Simulator::CanReadMemory(uintptr_t address, size_t size) {
4712 void Simulator::PrintExclusiveAccessWarning() {
4725 void Simulator::VisitLoadStoreExclusive(const Instruction* instr) {
4930 void Simulator::AtomicMemorySimpleHelper(const Instruction* instr) {
5001 void Simulator::AtomicMemorySwapHelper(const Instruction* instr) {
5034 void Simulator::LoadAcquireRCpcHelper(const Instruction* instr) {
5063 void Simulator::VisitAtomicMemory(const Instruction* instr) {
5153 void Simulator::VisitLoadLiteral(const Instruction* instr) {
5200 uintptr_t Simulator::AddressModeHelper(unsigned addr_reg,
5232 void Simulator::VisitMoveWideImmediate(const Instruction* instr) {
5276 void Simulator::VisitConditionalSelect(const Instruction* instr) {
5312 void Simulator::VisitDataProcessing1Source(const Instruction* instr) {
5402 uint32_t Simulator::Poly32Mod2(unsigned n, uint64_t data, uint32_t poly) {
5416 uint32_t Simulator::Crc32Checksum(uint32_t acc, T val, uint32_t poly) {
5425 uint32_t Simulator::Crc32Checksum(uint32_t acc, uint64_t val, uint32_t poly) {
5433 void Simulator::VisitDataProcessing2Source(const Instruction* instr) {
5578 void Simulator::SimulateSignedMinMax(const Instruction* instr) {
5617 void Simulator::SimulateUnsignedMinMax(const Instruction* instr) {
5654 void Simulator::VisitDataProcessing3Source(const Instruction* instr) {
5704 void Simulator::VisitBitfield(const Instruction* instr) {
5766 void Simulator::VisitExtract(const Instruction* instr) {
5779 void Simulator::VisitFPImmediate(const Instruction* instr) {
5798 void Simulator::VisitFPIntegerConvert(const Instruction* instr) {
6072 void Simulator::VisitFPFixedPointConvert(const Instruction* instr) {
6198 void Simulator::VisitFPCompare(const Instruction* instr) {
6251 void Simulator::VisitFPConditionalCompare(const Instruction* instr) {
6301 void Simulator::VisitFPConditionalSelect(const Instruction* instr) {
6327 void Simulator::VisitFPDataProcessing1Source(const Instruction* instr) {
6474 void Simulator::VisitFPDataProcessing2Source(const Instruction* instr) {
6549 void Simulator::VisitFPDataProcessing3Source(const Instruction* instr) {
6638 bool Simulator::FPProcessNaNs(const Instruction* instr) {
6665 void Simulator::SysOp_W(int op, int64_t val) {
6695 void Simulator::PACHelper(int dst,
6698 decltype(&Simulator::AddPAC) pac_fn) {
6708 void Simulator::VisitSystem(const Instruction* instr) {
6811 PACHelper(17, 16, pac_key, &Simulator::AddPAC);
6817 PACHelper(30, 31, pac_key, &Simulator::AddPAC);
6837 PACHelper(30, -1, pac_key, &Simulator::AddPAC);
6843 PACHelper(17, 16, pac_key, &Simulator::AuthPAC);
6849 PACHelper(30, 31, pac_key, &Simulator::AuthPAC);
6855 PACHelper(30, -1, pac_key, &Simulator::AuthPAC);
6871 void Simulator::VisitException(const Instruction* instr) {
6928 void Simulator::VisitCrypto2RegSHA(const Instruction* instr) {
6933 void Simulator::VisitCrypto3RegSHA(const Instruction* instr) {
6938 void Simulator::VisitCryptoAES(const Instruction* instr) {
6943 void Simulator::VisitNEON2RegMisc(const Instruction* instr) {
7224 void Simulator::VisitNEON2RegMiscFP16(const Instruction* instr) {
7329 void Simulator::VisitNEON3Same(const Instruction* instr) {
7604 void Simulator::VisitNEON3SameFP16(const Instruction* instr) {
7661 void Simulator::VisitNEON3SameExtra(const Instruction* instr) {
7697 void Simulator::VisitNEON3Different(const Instruction* instr) {
7869 void Simulator::VisitNEONAcrossLanes(const Instruction* instr) {
7946 void Simulator::SimulateNEONMulByElementLong(const Instruction* instr) {
8001 void Simulator::SimulateNEONFPMulByElementLong(const Instruction* instr) {
8028 void Simulator::SimulateNEONFPMulByElement(const Instruction* instr) {
8076 void Simulator::SimulateNEONComplexMulByElement(const Instruction* instr) {
8096 void Simulator::SimulateNEONDotProdByElement(const Instruction* instr) {
8125 void Simulator::VisitNEONByIndexedElement(const Instruction* instr) {
8168 void Simulator::VisitNEONCopy(const Instruction* instr) {
8205 void Simulator::VisitNEONExtract(const Instruction* instr) {
8220 void Simulator::NEONLoadStoreMultiStructHelper(const Instruction* instr,
8385 void Simulator::VisitNEONLoadStoreMultiStruct(const Instruction* instr) {
8390 void Simulator::VisitNEONLoadStoreMultiStructPostIndex(
8396 void Simulator::NEONLoadStoreSingleStructHelper(const Instruction* instr,
8622 void Simulator::VisitNEONLoadStoreSingleStruct(const Instruction* instr) {
8627 void Simulator::VisitNEONLoadStoreSingleStructPostIndex(
8633 void Simulator::VisitNEONModifiedImmediate(const Instruction* instr) {
8745 void Simulator::VisitNEONScalar2RegMisc(const Instruction* instr) {
8885 void Simulator::VisitNEONScalar2RegMiscFP16(const Instruction* instr) {
8957 void Simulator::VisitNEONScalar3Diff(const Instruction* instr) {
8980 void Simulator::VisitNEONScalar3Same(const Instruction* instr) {
9095 void Simulator::VisitNEONScalar3SameFP16(const Instruction* instr) {
9134 void Simulator::VisitNEONScalar3SameExtra(const Instruction* instr) {
9154 void Simulator::VisitNEONScalarByIndexedElement(const Instruction* instr) {
9172 Op = &Simulator::sqdmull;
9175 Op = &Simulator::sqdmlal;
9178 Op = &Simulator::sqdmlsl;
9181 Op = &Simulator::sqdmulh;
9185 Op = &Simulator::sqrdmulh;
9189 Op = &Simulator::sqrdmlah;
9193 Op = &Simulator::sqrdmlsh;
9209 Op = &Simulator::fmul;
9213 Op = &Simulator::fmla;
9217 Op = &Simulator::fmls;
9221 Op = &Simulator::fmulx;
9232 void Simulator::VisitNEONScalarCopy(const Instruction* instr) {
9250 void Simulator::VisitNEONScalarPairwise(const Instruction* instr) {
9290 void Simulator::VisitNEONScalarShiftImmediate(const Instruction* instr) {
9398 void Simulator::VisitNEONShiftImmediate(const Instruction* instr) {
9561 void Simulator::VisitNEONTable(const Instruction* instr) {
9603 void Simulator::VisitNEONPerm(const Instruction* instr) {
9635 void Simulator::VisitSVEAddressGeneration(const Instruction* instr) {
9667 void Simulator::VisitSVEBitwiseLogicalWithImm_Unpredicated(
9691 void Simulator::VisitSVEBroadcastBitmaskImm(const Instruction* instr) {
9708 void Simulator::VisitSVEBitwiseLogicalUnpredicated(const Instruction* instr) {
9737 void Simulator::VisitSVEBitwiseShiftByImm_Predicated(const Instruction* instr) {
9784 void Simulator::VisitSVEBitwiseShiftByVector_Predicated(
9865 void Simulator::VisitSVEBitwiseShiftByWideElements_Predicated(
9897 void Simulator::VisitSVEBitwiseShiftUnpredicated(const Instruction* instr) {
9955 void Simulator::VisitSVEIncDecRegisterByElementCount(const Instruction* instr) {
9988 void Simulator::VisitSVEIncDecVectorByElementCount(const Instruction* instr) {
10024 void Simulator::VisitSVESaturatingIncDecRegisterByElementCount(
10100 void Simulator::VisitSVESaturatingIncDecVectorByElementCount(
10146 void Simulator::VisitSVEElementCount(const Instruction* instr) {
10169 void Simulator::VisitSVEFPAccumulatingReduction(const Instruction* instr) {
10187 void Simulator::VisitSVEFPArithmetic_Predicated(const Instruction* instr) {
10243 void Simulator::VisitSVEFPArithmeticWithImm_Predicated(
10295 void Simulator::VisitSVEFPTrigMulAddCoefficient(const Instruction* instr) {
10312 void Simulator::VisitSVEFPArithmeticUnpredicated(const Instruction* instr) {
10345 void Simulator::VisitSVEFPCompareVectors(const Instruction* instr) {
10386 void Simulator::VisitSVEFPCompareWithZero(const Instruction* instr) {
10426 void Simulator::VisitSVEFPComplexAddition(const Instruction* instr) {
10451 void Simulator::VisitSVEFPComplexMulAdd(const Instruction* instr) {
10477 void Simulator::VisitSVEFPComplexMulAddIndex(const Instruction* instr) {
10510 typedef LogicVRegister (Simulator::*FastReduceFn)(VectorFormat vform,
10514 void Simulator::VisitSVEFPFastReduction(const Instruction* instr) {
10528 fn = &Simulator::faddv;
10532 fn = &Simulator::fmaxnmv;
10536 fn = &Simulator::fmaxv;
10540 fn = &Simulator::fminnmv;
10544 fn = &Simulator::fminv;
10557 void Simulator::VisitSVEFPMulIndex(const Instruction* instr) {
10584 void Simulator::VisitSVEFPMulAdd(const Instruction* instr) {
10653 void Simulator::VisitSVEFPMulAddIndex(const Instruction* instr) {
10688 void Simulator::VisitSVEFPConvertToInt(const Instruction* instr) {
10748 void Simulator::VisitSVEFPConvertPrecision(const Instruction* instr) {
10788 void Simulator::VisitSVEFPUnaryOp(const Instruction* instr) {
10809 void Simulator::VisitSVEFPRoundToIntegralValue(const Instruction* instr) {
10850 void Simulator::VisitSVEIntConvertToFP(const Instruction* instr) {
10911 void Simulator::VisitSVEFPUnaryOpUnpredicated(const Instruction* instr) {
10932 void Simulator::VisitSVEIncDecByPredicateCount(const Instruction* instr) {
10996 uint64_t Simulator::IncDecN(uint64_t acc,
11048 void Simulator::VisitSVEIndexGeneration(const Instruction* instr) {
11069 void Simulator::VisitSVEIntArithmeticUnpredicated(const Instruction* instr) {
11099 void Simulator::VisitSVEIntAddSubtractVectors_Predicated(
11124 void Simulator::VisitSVEBitwiseLogical_Predicated(const Instruction* instr) {
11151 void Simulator::VisitSVEIntMulVectors_Predicated(const Instruction* instr) {
11175 void Simulator::VisitSVEIntMinMaxDifference_Predicated(
11209 void Simulator::VisitSVEIntMulImm_Unpredicated(const Instruction* instr) {
11225 void Simulator::VisitSVEIntDivideVectors_Predicated(const Instruction* instr) {
11254 void Simulator::VisitSVEIntMinMaxImm_Unpredicated(const Instruction* instr) {
11285 void Simulator::VisitSVEIntCompareScalarCountAndLimit(
11352 void Simulator::VisitSVEConditionallyTerminateScalars(
11376 void Simulator::VisitSVEIntCompareSignedImm(const Instruction* instr) {
11420 void Simulator::VisitSVEIntCompareUnsignedImm(const Instruction* instr) {
11456 void Simulator::VisitSVEIntCompareVectors(const Instruction* instr) {
11527 void Simulator::VisitSVEFPExponentialAccelerator(const Instruction* instr) {
11545 void Simulator::VisitSVEFPTrigSelectCoefficient(const Instruction* instr) {
11564 void Simulator::VisitSVEConstructivePrefix_Unpredicated(
11579 void Simulator::VisitSVEIntMulAddPredicated(const Instruction* instr) {
11609 void Simulator::VisitSVEIntMulAddUnpredicated(const Instruction* instr) {
11631 void Simulator::VisitSVEMovprfx(const Instruction* instr) {
11651 void Simulator::VisitSVEIntReduction(const Instruction* instr) {
11699 void Simulator::VisitSVEIntUnaryArithmeticPredicated(const Instruction* instr) {
11752 void Simulator::VisitSVECopyFPImm_Predicated(const Instruction* instr) {
11778 void Simulator::VisitSVEIntAddSubtractImm_Unpredicated(
11815 void Simulator::VisitSVEBroadcastIntImm_Unpredicated(const Instruction* instr) {
11838 void Simulator::VisitSVEBroadcastFPImm_Unpredicated(const Instruction* instr) {
11864 void Simulator::VisitSVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsets(
11882 void Simulator::VisitSVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets(
11905 void Simulator::VisitSVE32BitGatherLoad_VectorPlusImm(
11944 void Simulator::VisitSVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsets(
11960 void Simulator::VisitSVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsets(
11976 void Simulator::VisitSVE32BitGatherPrefetch_VectorPlusImm(
11991 void Simulator::VisitSVEContiguousPrefetch_ScalarPlusImm(
12006 void Simulator::VisitSVEContiguousPrefetch_ScalarPlusScalar(
12024 void Simulator::VisitSVELoadAndBroadcastElement(const Instruction* instr) {
12070 void Simulator::VisitSVELoadPredicateRegister(const Instruction* instr) {
12091 void Simulator::VisitSVELoadVectorRegister(const Instruction* instr) {
12112 void Simulator::VisitSVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsets(
12136 void Simulator::VisitSVE64BitGatherLoad_ScalarPlus64BitScaledOffsets(
12158 void Simulator::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets(
12186 void Simulator::VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets(
12214 void Simulator::VisitSVE64BitGatherLoad_VectorPlusImm(
12254 void Simulator::VisitSVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsets(
12270 void Simulator::
12287 void Simulator::VisitSVE64BitGatherPrefetch_VectorPlusImm(
12302 void Simulator::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar(
12350 void Simulator::VisitSVEContiguousNonFaultLoad_ScalarPlusImm(
12396 void Simulator::VisitSVEContiguousNonTemporalLoad_ScalarPlusImm(
12431 void Simulator::VisitSVEContiguousNonTemporalLoad_ScalarPlusScalar(
12465 void Simulator::VisitSVELoadAndBroadcastQOWord_ScalarPlusImm(
12493 void Simulator::VisitSVELoadAndBroadcastQOWord_ScalarPlusScalar(
12520 void Simulator::VisitSVELoadMultipleStructures_ScalarPlusImm(
12555 void Simulator::VisitSVELoadMultipleStructures_ScalarPlusScalar(
12590 void Simulator::VisitSVE32BitScatterStore_ScalarPlus32BitScaledOffsets(
12619 void Simulator::VisitSVE32BitScatterStore_ScalarPlus32BitUnscaledOffsets(
12648 void Simulator::VisitSVE32BitScatterStore_VectorPlusImm(
12674 void Simulator::VisitSVE64BitScatterStore_ScalarPlus64BitScaledOffsets(
12702 void Simulator::VisitSVE64BitScatterStore_ScalarPlus64BitUnscaledOffsets(
12730 void Simulator::VisitSVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsets(
12761 void Simulator::
12792 void Simulator::VisitSVE64BitScatterStore_VectorPlusImm(
12821 void Simulator::VisitSVEContiguousNonTemporalStore_ScalarPlusImm(
12852 void Simulator::VisitSVEContiguousNonTemporalStore_ScalarPlusScalar(
12882 void Simulator::VisitSVEContiguousStore_ScalarPlusImm(
12913 void Simulator::VisitSVEContiguousStore_ScalarPlusScalar(
12939 void Simulator::VisitSVECopySIMDFPScalarRegisterToVector_Predicated(
12956 void Simulator::VisitSVEStoreMultipleStructures_ScalarPlusImm(
12991 void Simulator::VisitSVEStoreMultipleStructures_ScalarPlusScalar(
13025 void Simulator::VisitSVEStorePredicateRegister(const Instruction* instr) {
13046 void Simulator::VisitSVEStoreVectorRegister(const Instruction* instr) {
13067 void Simulator::VisitSVEMulIndex(const Instruction* instr) {
13099 void Simulator::SimulateMatrixMul(const Instruction* instr) {
13133 void Simulator::SimulateSVEFPMatrixMul(const Instruction* instr) {
13150 void Simulator::VisitSVEPartitionBreakCondition(const Instruction* instr) {
13182 void Simulator::VisitSVEPropagateBreakToNextPartition(
13205 void Simulator::VisitSVEUnpackPredicateElements(const Instruction* instr) {
13209 SimVRegister temp = Simulator::ExpandToSimVRegister(pn);
13224 Simulator::ExtractFromSimVRegister(kFormatVnB, pd, temp);
13227 void Simulator::VisitSVEPermutePredicateElements(const Instruction* instr) {
13233 SimVRegister temp0 = Simulator::ExpandToSimVRegister(pn);
13234 SimVRegister temp1 = Simulator::ExpandToSimVRegister(pm);
13259 Simulator::ExtractFromSimVRegister(kFormatVnB, pd, temp0);
13262 void Simulator::VisitSVEReversePredicateElements(const Instruction* instr) {
13268 SimVRegister temp = Simulator::ExpandToSimVRegister(pn);
13270 Simulator::ExtractFromSimVRegister(kFormatVnB, pd, temp);
13279 void Simulator::VisitSVEPermuteVectorExtract(const Instruction* instr) {
13298 void Simulator::VisitSVEPermuteVectorInterleaving(const Instruction* instr) {
13329 void Simulator::VisitSVEConditionallyBroadcastElementToVector(
13361 void Simulator::VisitSVEConditionallyExtractElementToSIMDFPScalar(
13390 void Simulator::VisitSVEConditionallyExtractElementToGeneralRegister(
13417 void Simulator::VisitSVEExtractElementToSIMDFPScalarRegister(
13445 void Simulator::VisitSVEExtractElementToGeneralRegister(
13470 void Simulator::VisitSVECompressActiveElements(const Instruction* instr) {
13486 void Simulator::VisitSVECopyGeneralRegisterToVector_Predicated(
13505 void Simulator::VisitSVECopyIntImm_Predicated(const Instruction* instr) {
13530 void Simulator::VisitSVEReverseWithinElements(const Instruction* instr) {
13585 void Simulator::VisitSVEVectorSplice(const Instruction* instr) {
13605 void Simulator::VisitSVEBroadcastGeneralRegister(const Instruction* instr) {
13619 void Simulator::VisitSVEInsertSIMDFPScalarRegister(const Instruction* instr) {
13632 void Simulator::VisitSVEInsertGeneralRegister(const Instruction* instr) {
13645 void Simulator::VisitSVEBroadcastIndexElement(const Instruction* instr) {
13669 void Simulator::VisitSVEReverseVectorElements(const Instruction* instr) {
13682 void Simulator::VisitSVEUnpackVectorElements(const Instruction* instr) {
13704 void Simulator::VisitSVETableLookup(const Instruction* instr) {
13727 void Simulator::VisitSVEPredicateCount(const Instruction* instr) {
13743 void Simulator::VisitSVEPredicateLogical(const Instruction* instr) {
13784 void Simulator::VisitSVEPredicateFirstActive(const Instruction* instr) {
13799 void Simulator::VisitSVEPredicateInitialize(const Instruction* instr) {
13814 void Simulator::VisitSVEPredicateNextActive(const Instruction* instr) {
13828 void Simulator::VisitSVEPredicateReadFromFFR_Predicated(
13853 void Simulator::VisitSVEPredicateReadFromFFR_Unpredicated(
13867 void Simulator::VisitSVEPredicateTest(const Instruction* instr) {
13880 void Simulator::VisitSVEPredicateZero(const Instruction* instr) {
13891 void Simulator::VisitSVEPropagateBreak(const Instruction* instr) {
13921 void Simulator::VisitSVEStackFrameAdjustment(const Instruction* instr) {
13940 void Simulator::VisitSVEStackFrameSize(const Instruction* instr) {
13952 void Simulator::VisitSVEVectorSelect(const Instruction* instr) {
13966 void Simulator::VisitSVEFFRInitialise(const Instruction* instr) {
13979 void Simulator::VisitSVEFFRWriteFromPredicate(const Instruction* instr) {
14001 void Simulator::VisitSVEContiguousLoad_ScalarPlusImm(const Instruction* instr) {
14049 void Simulator::VisitSVEContiguousLoad_ScalarPlusScalar(
14096 void Simulator::DoUnreachable(const Instruction* instr) {
14106 void Simulator::Simulate_XdSP_XnSP_Xm(const Instruction* instr) {
14115 void Simulator::SimulateMTEAddSubTag(const Instruction* instr) {
14136 void Simulator::SimulateMTETagMaskInsert(const Instruction* instr) {
14145 void Simulator::SimulateMTESubPointer(const Instruction* instr) {
14159 void Simulator::SimulateMTEStoreTagPair(const Instruction* instr) {
14192 void Simulator::SimulateMTEStoreTag(const Instruction* instr) {
14277 void Simulator::SimulateMTELoadTag(const Instruction* instr) {
14294 void Simulator::SimulateCpyFP(const Instruction* instr) {
14299 void Simulator::SimulateCpyP(const Instruction* instr) {
14328 void Simulator::SimulateCpyM(const Instruction* instr) {
14366 void Simulator::SimulateCpyE(const Instruction* instr) {
14374 void Simulator::SimulateSetP(const Instruction* instr) {
14379 void Simulator::SimulateSetM(const Instruction* instr) {
14395 void Simulator::SimulateSetE(const Instruction* instr) {
14403 void Simulator::SimulateSetGP(const Instruction* instr) {
14420 void Simulator::SimulateSetGM(const Instruction* instr) {
14433 void Simulator::DoTrace(const Instruction* instr) {
14460 void Simulator::DoLog(const Instruction* instr) {
14481 void Simulator::DoPrintf(const Instruction* instr) {
14595 void Simulator::DoRuntimeCall(const Instruction* instr) {
14597 // The appropriate `Simulator::SimulateRuntimeCall()` wrapper and the function
14606 reinterpret_cast<void (*)(Simulator*, uintptr_t)>(call_wrapper_address);
14617 void Simulator::DoRuntimeCall(const Instruction* instr) {
14624 void Simulator::DoConfigureCPUFeatures(const Instruction* instr) {
14664 void Simulator::DoSaveCPUFeatures(const Instruction* instr) {
14673 void Simulator::DoRestoreCPUFeatures(const Instruction* instr) {
14682 void* Simulator::Mmap(
14704 int Simulator::Munmap(void* address, size_t length, int prot) {
14707 // managed by the Simulator.