Lines Matching refs:instr
2127 void Simulator::Visit(Metadata* metadata, const Instruction* instr) {
2134 VisitUnimplemented(instr);
2136 (it->second)(this, instr);
2140 void Simulator::Simulate_PdT_PgZ_ZnT_ZmT(const Instruction* instr) {
2141 VectorFormat vform = instr->GetSVEVectorFormat();
2142 SimPRegister& pd = ReadPRegister(instr->GetPd());
2143 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
2144 SimVRegister& zm = ReadVRegister(instr->GetRm());
2145 SimVRegister& zn = ReadVRegister(instr->GetRn());
2161 void Simulator::Simulate_PdT_Xn_Xm(const Instruction* instr) {
2162 VectorFormat vform = instr->GetSVEVectorFormat();
2163 SimPRegister& pd = ReadPRegister(instr->GetPd());
2164 uint64_t src1 = ReadXRegister(instr->GetRn());
2165 uint64_t src2 = ReadXRegister(instr->GetRm());
2192 void Simulator::Simulate_ZdB_Zn1B_Zn2B_imm(const Instruction* instr) {
2195 SimVRegister& zd = ReadVRegister(instr->GetRd());
2196 SimVRegister& zn = ReadVRegister(instr->GetRn());
2197 SimVRegister& zn2 = ReadVRegister((instr->GetRn() + 1) % kNumberOfZRegisters);
2199 int index = instr->GetSVEExtractImmediate();
2206 void Simulator::Simulate_ZdB_ZnB_ZmB(const Instruction* instr) {
2207 SimVRegister& zd = ReadVRegister(instr->GetRd());
2208 SimVRegister& zm = ReadVRegister(instr->GetRm());
2209 SimVRegister& zn = ReadVRegister(instr->GetRn());
2213 if (instr->GetSVEVectorFormat() == kFormatVnB) {
2232 void Simulator::SimulateSVEMulIndex(const Instruction* instr) {
2233 VectorFormat vform = instr->GetSVEVectorFormat();
2234 SimVRegister& zd = ReadVRegister(instr->GetRd());
2235 SimVRegister& zn = ReadVRegister(instr->GetRn());
2247 dup_elements_to_segments(vform, temp, instr->GetSVEMulZmAndIndex());
2251 void Simulator::SimulateSVEMlaMlsIndex(const Instruction* instr) {
2252 VectorFormat vform = instr->GetSVEVectorFormat();
2253 SimVRegister& zda = ReadVRegister(instr->GetRd());
2254 SimVRegister& zn = ReadVRegister(instr->GetRn());
2267 dup_elements_to_segments(vform, temp, instr->GetSVEMulZmAndIndex());
2268 if (instr->ExtractBit(10) == 0) {
2275 void Simulator::SimulateSVESaturatingMulHighIndex(const Instruction* instr) {
2276 VectorFormat vform = instr->GetSVEVectorFormat();
2277 SimVRegister& zd = ReadVRegister(instr->GetRd());
2278 SimVRegister& zn = ReadVRegister(instr->GetRn());
2288 dup_elements_to_segments(vform, temp, instr->GetSVEMulZmAndIndex());
2305 void Simulator::SimulateSVESaturatingIntMulLongIdx(const Instruction* instr) {
2306 VectorFormat vform = instr->GetSVEVectorFormat();
2307 SimVRegister& zd = ReadVRegister(instr->GetRd());
2308 SimVRegister& zn = ReadVRegister(instr->GetRn());
2316 dup_elements_to_segments(vform_half, temp, instr->GetSVEMulLongZmAndIndex());
2388 void Simulator::Simulate_ZdH_PgM_ZnS(const Instruction* instr) {
2389 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
2390 SimVRegister& zd = ReadVRegister(instr->GetRd());
2391 SimVRegister& zn = ReadVRegister(instr->GetRn());
2408 void Simulator::Simulate_ZdS_PgM_ZnD(const Instruction* instr) {
2409 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
2410 SimVRegister& zd = ReadVRegister(instr->GetRd());
2411 SimVRegister& zn = ReadVRegister(instr->GetRn());
2437 void Simulator::SimulateSVEFPConvertLong(const Instruction* instr) {
2438 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
2439 SimVRegister& zd = ReadVRegister(instr->GetRd());
2440 SimVRegister& zn = ReadVRegister(instr->GetRn());
2457 void Simulator::Simulate_ZdS_PgM_ZnS(const Instruction* instr) {
2458 VectorFormat vform = instr->GetSVEVectorFormat();
2459 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
2460 SimVRegister& zd = ReadVRegister(instr->GetRd());
2461 SimVRegister& zn = ReadVRegister(instr->GetRn());
2481 void Simulator::Simulate_ZdT_PgM_ZnT(const Instruction* instr) {
2482 VectorFormat vform = instr->GetSVEVectorFormat();
2483 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
2484 SimVRegister& zd = ReadVRegister(instr->GetRd());
2485 SimVRegister& zn = ReadVRegister(instr->GetRn());
2490 vform = instr->GetSVEVectorFormat(17);
2505 void Simulator::Simulate_ZdT_PgZ_ZnT_ZmT(const Instruction* instr) {
2506 VectorFormat vform = instr->GetSVEVectorFormat();
2507 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
2508 SimVRegister& zd = ReadVRegister(instr->GetRd());
2509 SimVRegister& zm = ReadVRegister(instr->GetRm());
2510 SimVRegister& zn = ReadVRegister(instr->GetRn());
2522 void Simulator::Simulate_ZdT_ZnT_ZmT(const Instruction* instr) {
2523 VectorFormat vform = instr->GetSVEVectorFormat();
2524 SimVRegister& zd = ReadVRegister(instr->GetRd());
2525 SimVRegister& zm = ReadVRegister(instr->GetRm());
2526 SimVRegister& zn = ReadVRegister(instr->GetRn());
2570 void Simulator::Simulate_ZdT_ZnT_ZmTb(const Instruction* instr) {
2571 VectorFormat vform = instr->GetSVEVectorFormat();
2572 SimVRegister& zd = ReadVRegister(instr->GetRd());
2573 SimVRegister& zm = ReadVRegister(instr->GetRm());
2574 SimVRegister& zn = ReadVRegister(instr->GetRn());
2611 void Simulator::Simulate_ZdT_ZnT_const(const Instruction* instr) {
2612 SimVRegister& zd = ReadVRegister(instr->GetRd());
2613 SimVRegister& zn = ReadVRegister(instr->GetRn());
2616 instr->GetSVEImmShiftAndLaneSizeLog2(/* is_predicated = */ false);
2638 void Simulator::SimulateSVENarrow(const Instruction* instr) {
2639 SimVRegister& zd = ReadVRegister(instr->GetRd());
2640 SimVRegister& zn = ReadVRegister(instr->GetRn());
2644 instr->GetSVEImmShiftAndLaneSizeLog2(/* is_predicated = */ false);
2735 void Simulator::SimulateSVEInterleavedArithLong(const Instruction* instr) {
2736 VectorFormat vform = instr->GetSVEVectorFormat();
2737 SimVRegister& zd = ReadVRegister(instr->GetRd());
2738 SimVRegister& zm = ReadVRegister(instr->GetRm());
2739 SimVRegister& zn = ReadVRegister(instr->GetRn());
2813 void Simulator::SimulateSVEIntMulLongVec(const Instruction* instr) {
2814 VectorFormat vform = instr->GetSVEVectorFormat();
2815 SimVRegister& zd = ReadVRegister(instr->GetRd());
2816 SimVRegister& zm = ReadVRegister(instr->GetRm());
2817 SimVRegister& zn = ReadVRegister(instr->GetRn());
2863 void Simulator::SimulateSVEAddSubHigh(const Instruction* instr) {
2864 SimVRegister& zd = ReadVRegister(instr->GetRd());
2865 SimVRegister& zm = ReadVRegister(instr->GetRm());
2866 SimVRegister& zn = ReadVRegister(instr->GetRn());
2870 VectorFormat vform_src = instr->GetSVEVectorFormat();
2917 void Simulator::SimulateSVEShiftLeftImm(const Instruction* instr) {
2918 SimVRegister& zd = ReadVRegister(instr->GetRd());
2919 SimVRegister& zn = ReadVRegister(instr->GetRn());
2923 instr->GetSVEImmShiftAndLaneSizeLog2(/* is_predicated = */ false);
2955 void Simulator::SimulateSVESaturatingMulAddHigh(const Instruction* instr) {
2956 VectorFormat vform = instr->GetSVEVectorFormat();
2957 SimVRegister& zda = ReadVRegister(instr->GetRd());
2958 SimVRegister& zn = ReadVRegister(instr->GetRn());
2959 unsigned zm_code = instr->GetRm();
2975 index = (instr->ExtractBit(22) << 2) | instr->ExtractBits(20, 19);
2976 zm_code = instr->ExtractBits(18, 16);
2983 index = instr->ExtractBits(20, 19);
2984 zm_code = instr->ExtractBits(18, 16);
2991 index = instr->ExtractBit(20);
2992 zm_code = instr->ExtractBits(19, 16);
3011 void Simulator::Simulate_ZdaD_ZnS_ZmS_imm(const Instruction* instr) {
3012 SimVRegister& zda = ReadVRegister(instr->GetRd());
3013 SimVRegister& zn = ReadVRegister(instr->GetRn());
3014 SimVRegister& zm = ReadVRegister(instr->ExtractBits(19, 16));
3017 Instr index = (instr->ExtractBit(20) << 1) | instr->ExtractBit(11);
3041 void Simulator::Simulate_ZdaS_ZnH_ZmH(const Instruction* instr) {
3042 SimVRegister& zda = ReadVRegister(instr->GetRd());
3043 SimVRegister& zm = ReadVRegister(instr->GetRm());
3044 SimVRegister& zn = ReadVRegister(instr->GetRn());
3070 void Simulator::Simulate_ZdaS_ZnH_ZmH_imm(const Instruction* instr) {
3071 SimVRegister& zda = ReadVRegister(instr->GetRd());
3072 SimVRegister& zn = ReadVRegister(instr->GetRn());
3073 SimVRegister& zm = ReadVRegister(instr->ExtractBits(18, 16));
3076 Instr index = (instr->ExtractBits(20, 19) << 1) | instr->ExtractBit(11);
3112 void Simulator::Simulate_ZdaT_PgM_ZnTb(const Instruction* instr) {
3113 VectorFormat vform = instr->GetSVEVectorFormat();
3114 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
3115 SimVRegister& zda = ReadVRegister(instr->GetRd());
3116 SimVRegister& zn = ReadVRegister(instr->GetRn());
3132 void Simulator::SimulateSVEAddSubCarry(const Instruction* instr) {
3133 VectorFormat vform = (instr->ExtractBit(22) == 0) ? kFormatVnS : kFormatVnD;
3134 SimVRegister& zda = ReadVRegister(instr->GetRd());
3135 SimVRegister& zm = ReadVRegister(instr->GetRm());
3136 SimVRegister& zn = ReadVRegister(instr->GetRn());
3159 void Simulator::Simulate_ZdaT_ZnT_ZmT(const Instruction* instr) {
3160 VectorFormat vform = instr->GetSVEVectorFormat();
3161 SimVRegister& zda = ReadVRegister(instr->GetRd());
3162 SimVRegister& zm = ReadVRegister(instr->GetRm());
3163 SimVRegister& zn = ReadVRegister(instr->GetRn());
3177 void Simulator::SimulateSVEComplexIntMulAdd(const Instruction* instr) {
3178 SimVRegister& zda = ReadVRegister(instr->GetRd());
3179 SimVRegister& zn = ReadVRegister(instr->GetRn());
3180 int rot = instr->ExtractBits(11, 10) * 90;
3182 VectorFormat vform = instr->GetSVEVectorFormat();
3183 SimVRegister& zm = ReadVRegister(instr->GetRm());
3186 SimVRegister& zm_h = ReadVRegister(instr->ExtractBits(18, 16));
3187 SimVRegister& zm_s = ReadVRegister(instr->ExtractBits(19, 16));
3188 int idx_h = instr->ExtractBits(20, 19);
3189 int idx_s = instr->ExtractBit(20);
3215 void Simulator::Simulate_ZdaT_ZnT_const(const Instruction* instr) {
3216 SimVRegister& zd = ReadVRegister(instr->GetRd());
3217 SimVRegister& zn = ReadVRegister(instr->GetRn());
3220 instr->GetSVEImmShiftAndLaneSizeLog2(/* is_predicated = */ false);
3245 void Simulator::Simulate_ZdaT_ZnTb_ZmTb(const Instruction* instr) {
3246 VectorFormat vform = instr->GetSVEVectorFormat();
3247 SimVRegister& zda = ReadVRegister(instr->GetRd());
3248 SimVRegister& zm = ReadVRegister(instr->GetRm());
3249 SimVRegister& zn = ReadVRegister(instr->GetRn());
3308 void Simulator::SimulateSVEComplexDotProduct(const Instruction* instr) {
3309 VectorFormat vform = instr->GetSVEVectorFormat();
3310 SimVRegister& zda = ReadVRegister(instr->GetRd());
3311 SimVRegister& zn = ReadVRegister(instr->GetRn());
3312 int rot = instr->ExtractBits(11, 10) * 90;
3313 unsigned zm_code = instr->GetRm();
3338 void Simulator::SimulateSVEBitwiseTernary(const Instruction* instr) {
3340 SimVRegister& zdn = ReadVRegister(instr->GetRd());
3341 SimVRegister& zm = ReadVRegister(instr->GetRm());
3342 SimVRegister& zk = ReadVRegister(instr->GetRn());
3374 void Simulator::SimulateSVEHalvingAddSub(const Instruction* instr) {
3375 VectorFormat vform = instr->GetSVEVectorFormat();
3376 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
3377 SimVRegister& zdn = ReadVRegister(instr->GetRd());
3378 SimVRegister& zm = ReadVRegister(instr->GetRn());
3413 void Simulator::SimulateSVESaturatingArithmetic(const Instruction* instr) {
3414 VectorFormat vform = instr->GetSVEVectorFormat();
3415 SimVRegister& zdn = ReadVRegister(instr->GetRd());
3416 SimVRegister& zm = ReadVRegister(instr->GetRn());
3417 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
3452 void Simulator::SimulateSVEIntArithPair(const Instruction* instr) {
3453 VectorFormat vform = instr->GetSVEVectorFormat();
3454 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
3455 SimVRegister& zdn = ReadVRegister(instr->GetRd());
3456 SimVRegister& zm = ReadVRegister(instr->GetRn());
3482 void Simulator::Simulate_ZdnT_PgM_ZdnT_ZmT(const Instruction* instr) {
3483 VectorFormat vform = instr->GetSVEVectorFormat();
3484 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
3485 SimVRegister& zdn = ReadVRegister(instr->GetRd());
3486 SimVRegister& zm = ReadVRegister(instr->GetRn());
3511 void Simulator::Simulate_ZdnT_PgM_ZdnT_const(const Instruction* instr) {
3512 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
3513 SimVRegister& zdn = ReadVRegister(instr->GetRd());
3516 instr->GetSVEImmShiftAndLaneSizeLog2(/* is_predicated = */ true);
3545 void Simulator::SimulateSVEExclusiveOrRotate(const Instruction* instr) {
3548 SimVRegister& zdn = ReadVRegister(instr->GetRd());
3549 SimVRegister& zm = ReadVRegister(instr->GetRn());
3552 instr->GetSVEImmShiftAndLaneSizeLog2(/* is_predicated = */ false);
3561 void Simulator::Simulate_ZdnT_ZdnT_ZmT_const(const Instruction* instr) {
3562 VectorFormat vform = instr->GetSVEVectorFormat();
3563 SimVRegister& zdn = ReadVRegister(instr->GetRd());
3564 SimVRegister& zm = ReadVRegister(instr->GetRn());
3565 int rot = (instr->ExtractBit(10) == 0) ? 90 : 270;
3579 void Simulator::Simulate_ZtD_PgZ_ZnD_Xm(const Instruction* instr) {
3580 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
3581 SimVRegister& zn = ReadVRegister(instr->GetRn());
3582 uint64_t xm = ReadXRegister(instr->GetRm());
3617 SVEStructuredLoadHelper(kFormatVnD, pg, instr->GetRt(), addr, is_signed);
3620 void Simulator::Simulate_ZtD_Pg_ZnD_Xm(const Instruction* instr) {
3621 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
3622 SimVRegister& zn = ReadVRegister(instr->GetRn());
3623 uint64_t xm = ReadXRegister(instr->GetRm());
3632 instr->GetSVEMsizeFromDtype(/* is_signed = */ false));
3633 SVEStructuredStoreHelper(kFormatVnD, pg, instr->GetRt(), addr);
3636 void Simulator::Simulate_ZtS_PgZ_ZnS_Xm(const Instruction* instr) {
3637 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
3638 SimVRegister& zn = ReadVRegister(instr->GetRn());
3639 uint64_t xm = ReadXRegister(instr->GetRm());
3667 SVEStructuredLoadHelper(kFormatVnS, pg, instr->GetRt(), addr, is_signed);
3670 void Simulator::Simulate_ZtS_Pg_ZnS_Xm(const Instruction* instr) {
3671 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
3672 SimVRegister& zn = ReadVRegister(instr->GetRn());
3673 uint64_t xm = ReadXRegister(instr->GetRm());
3681 instr->GetSVEMsizeFromDtype(/* is_signed = */ false));
3682 SVEStructuredStoreHelper(kFormatVnS, pg, instr->GetRt(), addr);
3685 void Simulator::VisitReserved(const Instruction* instr) {
3687 VIXL_ASSERT(instr->Mask(ReservedMask) == UDF);
3690 reinterpret_cast<const void*>(instr),
3691 instr->GetInstructionBits());
3696 void Simulator::VisitUnimplemented(const Instruction* instr) {
3698 reinterpret_cast<const void*>(instr),
3699 instr->GetInstructionBits());
3704 void Simulator::VisitUnallocated(const Instruction* instr) {
3706 reinterpret_cast<const void*>(instr),
3707 instr->GetInstructionBits());
3712 void Simulator::VisitPCRelAddressing(const Instruction* instr) {
3713 VIXL_ASSERT((instr->Mask(PCRelAddressingMask) == ADR) ||
3714 (instr->Mask(PCRelAddressingMask) == ADRP));
3716 WriteRegister(instr->GetRd(), instr->GetImmPCOffsetTarget());
3720 void Simulator::VisitUnconditionalBranch(const Instruction* instr) {
3721 switch (instr->Mask(UnconditionalBranchMask)) {
3723 WriteLr(instr->GetNextInstruction());
3726 WritePc(instr->GetImmPCOffsetTarget());
3734 void Simulator::VisitConditionalBranch(const Instruction* instr) {
3735 VIXL_ASSERT(instr->Mask(ConditionalBranchMask) == B_cond);
3736 if (ConditionPassed(instr->GetConditionBranch())) {
3737 WritePc(instr->GetImmPCOffsetTarget());
3741 BType Simulator::GetBTypeFromInstruction(const Instruction* instr) const {
3742 switch (instr->Mask(UnconditionalBranchToRegisterMask)) {
3754 if ((instr->GetRn() == 16) || (instr->GetRn() == 17) ||
3763 void Simulator::VisitUnconditionalBranchToRegister(const Instruction* instr) {
3767 uint64_t addr = ReadXRegister(instr->GetRn());
3770 switch (instr->Mask(UnconditionalBranchToRegisterMask)) {
3793 context = ReadXRegister(instr->GetRd());
3810 WriteLr(instr->GetNextInstruction());
3814 PACKey key = (instr->ExtractBit(10) == 0) ? kPACKeyIA : kPACKeyIB;
3839 WriteNextBType(GetBTypeFromInstruction(instr));
3844 void Simulator::VisitTestBranch(const Instruction* instr) {
3846 (instr->GetImmTestBranchBit5() << 5) | instr->GetImmTestBranchBit40();
3847 bool bit_zero = ((ReadXRegister(instr->GetRt()) >> bit_pos) & 1) == 0;
3849 switch (instr->Mask(TestBranchMask)) {
3860 WritePc(instr->GetImmPCOffsetTarget());
3865 void Simulator::VisitCompareBranch(const Instruction* instr) {
3866 unsigned rt = instr->GetRt();
3868 switch (instr->Mask(CompareBranchMask)) {
3885 WritePc(instr->GetImmPCOffsetTarget());
3890 void Simulator::AddSubHelper(const Instruction* instr, int64_t op2) {
3891 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize;
3892 bool set_flags = instr->GetFlagsUpdate();
3894 Instr operation = instr->Mask(AddSubOpMask);
3902 instr->GetRn(),
3903 instr->GetRnMode()),
3912 instr->GetRn(),
3913 instr->GetRnMode()),
3923 instr->GetRd(),
3926 instr->GetRdMode());
3930 void Simulator::VisitAddSubShifted(const Instruction* instr) {
3932 VIXL_ASSERT(instr->GetShiftDP() != ROR);
3934 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize;
3936 ReadRegister(reg_size, instr->GetRm()),
3937 static_cast<Shift>(instr->GetShiftDP()),
3938 instr->GetImmDPShift());
3939 AddSubHelper(instr, op2);
3943 void Simulator::VisitAddSubImmediate(const Instruction* instr) {
3944 int64_t op2 = instr->GetImmAddSub()
3945 << ((instr->GetImmAddSubShift() == 1) ? 12 : 0);
3946 AddSubHelper(instr, op2);
3950 void Simulator::VisitAddSubExtended(const Instruction* instr) {
3951 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize;
3953 ReadRegister(reg_size, instr->GetRm()),
3954 static_cast<Extend>(instr->GetExtendMode()),
3955 instr->GetImmExtendShift());
3956 AddSubHelper(instr, op2);
3960 void Simulator::VisitAddSubWithCarry(const Instruction* instr) {
3961 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize;
3962 int64_t op2 = ReadRegister(reg_size, instr->GetRm());
3965 if ((instr->Mask(AddSubOpMask) == SUB) ||
3966 (instr->Mask(AddSubOpMask) == SUBS)) {
3971 instr->GetFlagsUpdate(),
3972 ReadRegister(reg_size, instr->GetRn()),
3976 WriteRegister(reg_size, instr->GetRd(), new_val);
3980 void Simulator::VisitRotateRightIntoFlags(const Instruction* instr) {
3981 switch (instr->Mask(RotateRightIntoFlagsMask)) {
3983 uint64_t value = ReadRegister<uint64_t>(instr->GetRn());
3984 unsigned shift = instr->GetImmRMIFRotation();
3985 unsigned mask = instr->GetNzcv();
3995 void Simulator::VisitEvaluateIntoFlags(const Instruction* instr) {
3996 uint32_t value = ReadRegister<uint32_t>(instr->GetRn());
3997 unsigned msb = (instr->Mask(EvaluateIntoFlagsMask) == SETF16) ? 15 : 7;
4007 void Simulator::VisitLogicalShifted(const Instruction* instr) {
4008 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize;
4009 Shift shift_type = static_cast<Shift>(instr->GetShiftDP());
4010 unsigned shift_amount = instr->GetImmDPShift();
4012 ReadRegister(reg_size, instr->GetRm()),
4015 if (instr->Mask(NOT) == NOT) {
4018 LogicalHelper(instr, op2);
4022 void Simulator::VisitLogicalImmediate(const Instruction* instr) {
4023 if (instr->GetImmLogical() == 0) {
4026 LogicalHelper(instr, instr->GetImmLogical());
4031 void Simulator::LogicalHelper(const Instruction* instr, int64_t op2) {
4032 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize;
4033 int64_t op1 = ReadRegister(reg_size, instr->GetRn());
4039 switch (instr->Mask(LogicalOpMask & ~NOT)) {
4065 instr->GetRd(),
4068 instr->GetRdMode());
4072 void Simulator::VisitConditionalCompareRegister(const Instruction* instr) {
4073 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize;
4074 ConditionalCompareHelper(instr, ReadRegister(reg_size, instr->GetRm()));
4078 void Simulator::VisitConditionalCompareImmediate(const Instruction* instr) {
4079 ConditionalCompareHelper(instr, instr->GetImmCondCmp());
4083 void Simulator::ConditionalCompareHelper(const Instruction* instr,
4085 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize;
4086 int64_t op1 = ReadRegister(reg_size, instr->GetRn());
4088 if (ConditionPassed(instr->GetCondition())) {
4091 if (instr->Mask(ConditionalCompareMask) == CCMP) {
4094 VIXL_ASSERT(instr->Mask(ConditionalCompareMask) == CCMN);
4099 ReadNzcv().SetFlags(instr->GetNzcv());
4105 void Simulator::VisitLoadStoreUnsignedOffset(const Instruction* instr) {
4106 int offset = instr->GetImmLSUnsigned() << instr->GetSizeLS();
4107 LoadStoreHelper(instr, offset, Offset);
4111 void Simulator::VisitLoadStoreUnscaledOffset(const Instruction* instr) {
4112 LoadStoreHelper(instr, instr->GetImmLS(), Offset);
4116 void Simulator::VisitLoadStorePreIndex(const Instruction* instr) {
4117 LoadStoreHelper(instr, instr->GetImmLS(), PreIndex);
4121 void Simulator::VisitLoadStorePostIndex(const Instruction* instr) {
4122 LoadStoreHelper(instr, instr->GetImmLS(), PostIndex);
4127 void Simulator::LoadAcquireRCpcUnscaledOffsetHelper(const Instruction* instr) {
4128 unsigned rt = instr->GetRt();
4129 unsigned rn = instr->GetRn();
4133 int offset = instr->GetImmLS();
4154 void Simulator::StoreReleaseUnscaledOffsetHelper(const Instruction* instr) {
4155 unsigned rt = instr->GetRt();
4156 unsigned rn = instr->GetRn();
4160 int offset = instr->GetImmLS();
4180 void Simulator::VisitLoadStoreRCpcUnscaledOffset(const Instruction* instr) {
4181 switch (instr->Mask(LoadStoreRCpcUnscaledOffsetMask)) {
4183 LoadAcquireRCpcUnscaledOffsetHelper<uint8_t, uint8_t>(instr);
4186 LoadAcquireRCpcUnscaledOffsetHelper<uint16_t, uint16_t>(instr);
4189 LoadAcquireRCpcUnscaledOffsetHelper<uint32_t, uint32_t>(instr);
4192 LoadAcquireRCpcUnscaledOffsetHelper<uint64_t, uint64_t>(instr);
4195 LoadAcquireRCpcUnscaledOffsetHelper<int32_t, int8_t>(instr);
4198 LoadAcquireRCpcUnscaledOffsetHelper<int64_t, int8_t>(instr);
4201 LoadAcquireRCpcUnscaledOffsetHelper<int32_t, int16_t>(instr);
4204 LoadAcquireRCpcUnscaledOffsetHelper<int64_t, int16_t>(instr);
4207 LoadAcquireRCpcUnscaledOffsetHelper<int64_t, int32_t>(instr);
4210 StoreReleaseUnscaledOffsetHelper<uint8_t>(instr);
4213 StoreReleaseUnscaledOffsetHelper<uint16_t>(instr);
4216 StoreReleaseUnscaledOffsetHelper<uint32_t>(instr);
4219 StoreReleaseUnscaledOffsetHelper<uint64_t>(instr);
4225 void Simulator::VisitLoadStorePAC(const Instruction* instr) {
4226 unsigned dst = instr->GetRt();
4227 unsigned addr_reg = instr->GetRn();
4231 PACKey key = (instr->ExtractBit(23) == 0) ? kPACKeyDA : kPACKeyDB;
4247 int64_t offset = instr->GetImmLSPAC();
4250 if (instr->Mask(LoadStorePACPreBit) == LoadStorePACPreBit) {
4267 void Simulator::VisitLoadStoreRegisterOffset(const Instruction* instr) {
4268 Extend ext = static_cast<Extend>(instr->GetExtendMode());
4270 unsigned shift_amount = instr->GetImmShiftLS() * instr->GetSizeLS();
4273 ExtendValue(kXRegSize, ReadXRegister(instr->GetRm()), ext, shift_amount);
4274 LoadStoreHelper(instr, offset, Offset);
4278 void Simulator::LoadStoreHelper(const Instruction* instr,
4281 unsigned srcdst = instr->GetRt();
4282 uintptr_t address = AddressModeHelper(instr->GetRn(), offset, addrmode);
4286 LoadStoreOp op = static_cast<LoadStoreOp>(instr->Mask(LoadStoreMask));
4388 unsigned access_size = 1 << instr->GetSizeLS();
4394 if (instr->IsLoad()) {
4400 } else if (instr->IsStore()) {
4414 void Simulator::VisitLoadStorePairOffset(const Instruction* instr) {
4415 LoadStorePairHelper(instr, Offset);
4419 void Simulator::VisitLoadStorePairPreIndex(const Instruction* instr) {
4420 LoadStorePairHelper(instr, PreIndex);
4424 void Simulator::VisitLoadStorePairPostIndex(const Instruction* instr) {
4425 LoadStorePairHelper(instr, PostIndex);
4429 void Simulator::VisitLoadStorePairNonTemporal(const Instruction* instr) {
4430 LoadStorePairHelper(instr, Offset);
4434 void Simulator::LoadStorePairHelper(const Instruction* instr,
4436 unsigned rt = instr->GetRt();
4437 unsigned rt2 = instr->GetRt2();
4438 int element_size = 1 << instr->GetSizeLSPair();
4439 int64_t offset = instr->GetImmLSPair() * element_size;
4440 uintptr_t address = AddressModeHelper(instr->GetRn(), offset, addrmode);
4444 static_cast<LoadStorePairOp>(instr->Mask(LoadStorePairMask));
4526 if (instr->IsLoad()) {
4552 void Simulator::CompareAndSwapHelper(const Instruction* instr) {
4553 unsigned rs = instr->GetRs();
4554 unsigned rt = instr->GetRt();
4555 unsigned rn = instr->GetRn();
4562 bool is_acquire = instr->ExtractBit(22) == 1;
4563 bool is_release = instr->ExtractBit(15) == 1;
4592 void Simulator::CompareAndSwapPairHelper(const Instruction* instr) {
4594 unsigned rs = instr->GetRs();
4595 unsigned rt = instr->GetRt();
4596 unsigned rn = instr->GetRn();
4607 bool is_acquire = instr->ExtractBit(22) == 1;
4608 bool is_release = instr->ExtractBit(15) == 1;
4725 void Simulator::VisitLoadStoreExclusive(const Instruction* instr) {
4727 static_cast<LoadStoreExclusive>(instr->Mask(LoadStoreExclusiveMask));
4734 CompareAndSwapHelper<uint32_t>(instr);
4740 CompareAndSwapHelper<uint64_t>(instr);
4746 CompareAndSwapHelper<uint8_t>(instr);
4752 CompareAndSwapHelper<uint16_t>(instr);
4758 CompareAndSwapPairHelper<uint32_t>(instr);
4764 CompareAndSwapPairHelper<uint64_t>(instr);
4769 unsigned rs = instr->GetRs();
4770 unsigned rt = instr->GetRt();
4771 unsigned rt2 = instr->GetRt2();
4772 unsigned rn = instr->GetRn();
4774 bool is_exclusive = !instr->GetLdStXNotExclusive();
4776 !is_exclusive || instr->GetLdStXAcquireRelease();
4777 bool is_load = instr->GetLdStXLoad();
4778 bool is_pair = instr->GetLdStXPair();
4780 unsigned element_size = 1 << instr->GetLdStXSizeLog2();
4930 void Simulator::AtomicMemorySimpleHelper(const Instruction* instr) {
4931 unsigned rs = instr->GetRs();
4932 unsigned rt = instr->GetRt();
4933 unsigned rn = instr->GetRn();
4935 bool is_acquire = (instr->ExtractBit(23) == 1) && (rt != kZeroRegCode);
4936 bool is_release = instr->ExtractBit(22) == 1;
4953 switch (instr->Mask(AtomicMemorySimpleOpMask)) {
5001 void Simulator::AtomicMemorySwapHelper(const Instruction* instr) {
5002 unsigned rs = instr->GetRs();
5003 unsigned rt = instr->GetRt();
5004 unsigned rn = instr->GetRn();
5006 bool is_acquire = (instr->ExtractBit(23) == 1) && (rt != kZeroRegCode);
5007 bool is_release = instr->ExtractBit(22) == 1;
5034 void Simulator::LoadAcquireRCpcHelper(const Instruction* instr) {
5035 unsigned rt = instr->GetRt();
5036 unsigned rn = instr->GetRn();
5063 void Simulator::VisitAtomicMemory(const Instruction* instr) {
5064 switch (instr->Mask(AtomicMemoryMask)) {
5088 AtomicMemorySimpleHelper<uint8_t>(instr);
5091 AtomicMemorySimpleHelper<int8_t>(instr);
5094 AtomicMemorySimpleHelper<uint16_t>(instr);
5097 AtomicMemorySimpleHelper<int16_t>(instr);
5100 AtomicMemorySimpleHelper<uint32_t>(instr);
5103 AtomicMemorySimpleHelper<int32_t>(instr);
5106 AtomicMemorySimpleHelper<uint64_t>(instr);
5109 AtomicMemorySimpleHelper<int64_t>(instr);
5117 AtomicMemorySwapHelper<uint8_t>(instr);
5123 AtomicMemorySwapHelper<uint16_t>(instr);
5129 AtomicMemorySwapHelper<uint32_t>(instr);
5135 AtomicMemorySwapHelper<uint64_t>(instr);
5138 LoadAcquireRCpcHelper<uint8_t>(instr);
5141 LoadAcquireRCpcHelper<uint16_t>(instr);
5144 LoadAcquireRCpcHelper<uint32_t>(instr);
5147 LoadAcquireRCpcHelper<uint64_t>(instr);
5153 void Simulator::VisitLoadLiteral(const Instruction* instr) {
5154 unsigned rt = instr->GetRt();
5155 uint64_t address = instr->GetLiteralAddress<uint64_t>();
5160 switch (instr->Mask(LoadLiteralMask)) {
5232 void Simulator::VisitMoveWideImmediate(const Instruction* instr) {
5234 static_cast<MoveWideImmediateOp>(instr->Mask(MoveWideImmediateMask));
5237 bool is_64_bits = instr->GetSixtyFourBits() == 1;
5239 VIXL_ASSERT(is_64_bits || (instr->GetShiftMoveWide() < 2));
5242 int64_t shift = instr->GetShiftMoveWide() * 16;
5243 int64_t shifted_imm16 = static_cast<int64_t>(instr->GetImmMoveWide())
5256 unsigned reg_code = instr->GetRd();
5272 WriteXRegister(instr->GetRd(), new_xn_val);
5276 void Simulator::VisitConditionalSelect(const Instruction* instr) {
5277 uint64_t new_val = ReadXRegister(instr->GetRn());
5279 if (ConditionFailed(static_cast<Condition>(instr->GetCondition()))) {
5280 new_val = ReadXRegister(instr->GetRm());
5281 switch (instr->Mask(ConditionalSelectMask)) {
5301 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize;
5302 WriteRegister(reg_size, instr->GetRd(), new_val);
5312 void Simulator::VisitDataProcessing1Source(const Instruction* instr) {
5313 unsigned dst = instr->GetRd();
5314 unsigned src = instr->GetRn();
5433 void Simulator::VisitDataProcessing2Source(const Instruction* instr) {
5436 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize;
5438 switch (instr->Mask(DataProcessing2SourceMask)) {
5440 int32_t rn = ReadWRegister(instr->GetRn());
5441 int32_t rm = ReadWRegister(instr->GetRm());
5453 int64_t rn = ReadXRegister(instr->GetRn());
5454 int64_t rm = ReadXRegister(instr->GetRm());
5466 uint32_t rn = static_cast<uint32_t>(ReadWRegister(instr->GetRn()));
5467 uint32_t rm = static_cast<uint32_t>(ReadWRegister(instr->GetRm()));
5477 uint64_t rn = static_cast<uint64_t>(ReadXRegister(instr->GetRn()));
5478 uint64_t rm = static_cast<uint64_t>(ReadXRegister(instr->GetRm()));
5504 uint64_t dst = static_cast<uint64_t>(ReadXRegister(instr->GetRn()));
5506 ReadXRegister(instr->GetRm(), Reg31IsStackPointer));
5512 uint32_t acc = ReadRegister<uint32_t>(instr->GetRn());
5513 uint8_t val = ReadRegister<uint8_t>(instr->GetRm());
5518 uint32_t acc = ReadRegister<uint32_t>(instr->GetRn());
5519 uint16_t val = ReadRegister<uint16_t>(instr->GetRm());
5524 uint32_t acc = ReadRegister<uint32_t>(instr->GetRn());
5525 uint32_t val = ReadRegister<uint32_t>(instr->GetRm());
5530 uint32_t acc = ReadRegister<uint32_t>(instr->GetRn());
5531 uint64_t val = ReadRegister<uint64_t>(instr->GetRm());
5537 uint32_t acc = ReadRegister<uint32_t>(instr->GetRn());
5538 uint8_t val = ReadRegister<uint8_t>(instr->GetRm());
5543 uint32_t acc = ReadRegister<uint32_t>(instr->GetRn());
5544 uint16_t val = ReadRegister<uint16_t>(instr->GetRm());
5549 uint32_t acc = ReadRegister<uint32_t>(instr->GetRn());
5550 uint32_t val = ReadRegister<uint32_t>(instr->GetRm());
5555 uint32_t acc = ReadRegister<uint32_t>(instr->GetRn());
5556 uint64_t val = ReadRegister<uint64_t>(instr->GetRm());
5568 int mask = (instr->GetSixtyFourBits() == 1) ? 0x3f : 0x1f;
5569 unsigned shift = ReadWRegister(instr->GetRm()) & mask;
5571 ReadRegister(reg_size, instr->GetRn()),
5575 WriteRegister(reg_size, instr->GetRd(), result);
5578 void Simulator::SimulateSignedMinMax(const Instruction* instr) {
5579 int32_t wn = ReadWRegister(instr->GetRn());
5580 int32_t wm = ReadWRegister(instr->GetRm());
5581 int64_t xn = ReadXRegister(instr->GetRn());
5582 int64_t xm = ReadXRegister(instr->GetRm());
5583 int32_t imm = instr->ExtractSignedBits(17, 10);
5584 int dst = instr->GetRd();
5617 void Simulator::SimulateUnsignedMinMax(const Instruction* instr) {
5618 uint64_t xn = ReadXRegister(instr->GetRn());
5619 uint64_t xm = ReadXRegister(instr->GetRm());
5620 uint32_t imm = instr->ExtractBits(17, 10);
5621 int dst = instr->GetRd();
5654 void Simulator::VisitDataProcessing3Source(const Instruction* instr) {
5655 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize;
5659 uint64_t rn_u32 = ReadRegister<uint32_t>(instr->GetRn());
5660 uint64_t rm_u32 = ReadRegister<uint32_t>(instr->GetRm());
5661 int64_t rn_s32 = ReadRegister<int32_t>(instr->GetRn());
5662 int64_t rm_s32 = ReadRegister<int32_t>(instr->GetRm());
5663 uint64_t rn_u64 = ReadXRegister(instr->GetRn());
5664 uint64_t rm_u64 = ReadXRegister(instr->GetRm());
5665 switch (instr->Mask(DataProcessing3SourceMask)) {
5668 result = ReadXRegister(instr->GetRa()) + (rn_u64 * rm_u64);
5672 result = ReadXRegister(instr->GetRa()) - (rn_u64 * rm_u64);
5675 result = ReadXRegister(instr->GetRa()) +
5679 result = ReadXRegister(instr->GetRa()) -
5683 result = ReadXRegister(instr->GetRa()) + (rn_u32 * rm_u32);
5686 result = ReadXRegister(instr->GetRa()) - (rn_u32 * rm_u32);
5690 internal::MultiplyHigh<64>(ReadRegister<uint64_t>(instr->GetRn()),
5691 ReadRegister<uint64_t>(instr->GetRm()));
5694 result = internal::MultiplyHigh<64>(ReadXRegister(instr->GetRn()),
5695 ReadXRegister(instr->GetRm()));
5700 WriteRegister(reg_size, instr->GetRd(), result);
5704 void Simulator::VisitBitfield(const Instruction* instr) {
5705 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize;
5706 int64_t reg_mask = instr->GetSixtyFourBits() ? kXRegMask : kWRegMask;
5707 int R = instr->GetImmR();
5708 int S = instr->GetImmS();
5710 if (instr->GetSixtyFourBits() != instr->GetBitN()) {
5711 VisitUnallocated(instr);
5714 if ((instr->GetSixtyFourBits() == 0) && ((S > 31) || (R > 31))) {
5715 VisitUnallocated(instr);
5734 switch (instr->Mask(BitfieldMask)) {
5751 uint64_t dst = inzero ? 0 : ReadRegister(reg_size, instr->GetRd());
5752 uint64_t src = ReadRegister(reg_size, instr->GetRn());
5762 WriteRegister(reg_size, instr->GetRd(), result);
5766 void Simulator::VisitExtract(const Instruction* instr) {
5767 unsigned lsb = instr->GetImmS();
5768 unsigned reg_size = (instr->GetSixtyFourBits() == 1) ? kXRegSize : kWRegSize;
5770 static_cast<uint64_t>(ReadRegister(reg_size, instr->GetRm())) >> lsb;
5773 : ReadRegister<uint64_t>(reg_size, instr->GetRn())
5775 WriteRegister(reg_size, instr->GetRd(), low_res | high_res);
5779 void Simulator::VisitFPImmediate(const Instruction* instr) {
5781 unsigned dest = instr->GetRd();
5782 switch (instr->Mask(FPImmediateMask)) {
5784 WriteHRegister(dest, Float16ToRawbits(instr->GetImmFP16()));
5787 WriteSRegister(dest, instr->GetImmFP32());
5790 WriteDRegister(dest, instr->GetImmFP64());
5798 void Simulator::VisitFPIntegerConvert(const Instruction* instr) {
5801 unsigned dst = instr->GetRd();
5802 unsigned src = instr->GetRn();
5806 switch (instr->Mask(FPIntegerConvertMask)) {
6072 void Simulator::VisitFPFixedPointConvert(const Instruction* instr) {
6075 unsigned dst = instr->GetRd();
6076 unsigned src = instr->GetRn();
6077 int fbits = 64 - instr->GetFPScale();
6081 switch (instr->Mask(FPFixedPointConvertMask)) {
6198 void Simulator::VisitFPCompare(const Instruction* instr) {
6202 switch (instr->Mask(FPCompareMask)) {
6207 FPCompare(ReadHRegister(instr->GetRn()),
6208 ReadHRegister(instr->GetRm()),
6215 FPCompare(ReadSRegister(instr->GetRn()),
6216 ReadSRegister(instr->GetRm()),
6223 FPCompare(ReadDRegister(instr->GetRn()),
6224 ReadDRegister(instr->GetRm()),
6231 FPCompare(ReadHRegister(instr->GetRn()), SimFloat16(0.0), trap);
6237 FPCompare(ReadSRegister(instr->GetRn()), 0.0f, trap);
6243 FPCompare(ReadDRegister(instr->GetRn()), 0.0, trap);
6251 void Simulator::VisitFPConditionalCompare(const Instruction* instr) {
6255 switch (instr->Mask(FPConditionalCompareMask)) {
6260 if (ConditionPassed(instr->GetCondition())) {
6261 FPCompare(ReadHRegister(instr->GetRn()),
6262 ReadHRegister(instr->GetRm()),
6265 ReadNzcv().SetFlags(instr->GetNzcv());
6273 if (ConditionPassed(instr->GetCondition())) {
6274 FPCompare(ReadSRegister(instr->GetRn()),
6275 ReadSRegister(instr->GetRm()),
6278 ReadNzcv().SetFlags(instr->GetNzcv());
6286 if (ConditionPassed(instr->GetCondition())) {
6287 FPCompare(ReadDRegister(instr->GetRn()),
6288 ReadDRegister(instr->GetRm()),
6291 ReadNzcv().SetFlags(instr->GetNzcv());
6301 void Simulator::VisitFPConditionalSelect(const Instruction* instr) {
6305 if (ConditionPassed(instr->GetCondition())) {
6306 selected = instr->GetRn();
6308 selected = instr->GetRm();
6311 switch (instr->Mask(FPConditionalSelectMask)) {
6313 WriteHRegister(instr->GetRd(), ReadHRegister(selected));
6316 WriteSRegister(instr->GetRd(), ReadSRegister(selected));
6319 WriteDRegister(instr->GetRd(), ReadDRegister(selected));
6327 void Simulator::VisitFPDataProcessing1Source(const Instruction* instr) {
6332 switch (instr->Mask(FPTypeMask)) {
6346 SimVRegister& rd = ReadVRegister(instr->GetRd());
6347 SimVRegister& rn = ReadVRegister(instr->GetRn());
6351 unsigned fd = instr->GetRd();
6352 unsigned fn = instr->GetRn();
6354 switch (instr->Mask(FPDataProcessing1SourceMask)) {
6474 void Simulator::VisitFPDataProcessing2Source(const Instruction* instr) {
6478 switch (instr->Mask(FPTypeMask)) {
6491 SimVRegister& rd = ReadVRegister(instr->GetRd());
6492 SimVRegister& rn = ReadVRegister(instr->GetRn());
6493 SimVRegister& rm = ReadVRegister(instr->GetRm());
6495 switch (instr->Mask(FPDataProcessing2SourceMask)) {
6545 LogVRegister(instr->GetRd(), GetPrintRegisterFormatFP(vform));
6549 void Simulator::VisitFPDataProcessing3Source(const Instruction* instr) {
6552 unsigned fd = instr->GetRd();
6553 unsigned fn = instr->GetRn();
6554 unsigned fm = instr->GetRm();
6555 unsigned fa = instr->GetRa();
6557 switch (instr->Mask(FPDataProcessing3SourceMask)) {
6638 bool Simulator::FPProcessNaNs(const Instruction* instr) {
6639 unsigned fd = instr->GetRd();
6640 unsigned fn = instr->GetRn();
6641 unsigned fm = instr->GetRm();
6644 if (instr->Mask(FP64) == FP64) {
6650 } else if (instr->Mask(FP32) == FP32) {
6657 VIXL_ASSERT(instr->Mask(FP16) == FP16);
6708 void Simulator::VisitSystem(const Instruction* instr) {
6741 switch (instr->GetImmSystemRegister()) {
6743 ReadNzcv().SetRawValue(ReadWRegister(instr->GetRt()));
6747 ReadFpcr().SetRawValue(ReadWRegister(instr->GetRt()));
6755 switch (instr->GetImmSystemRegister()) {
6757 WriteXRegister(instr->GetRt(), ReadNzcv().GetRawValue());
6760 WriteXRegister(instr->GetRt(), ReadFpcr().GetRawValue());
6767 WriteXRegister(instr->GetRt(), rand_num);
6784 switch (instr->GetImmHint()) {
6863 SysOp_W(instr->GetSysOp(), ReadXRegister(instr->GetRt()));
6871 void Simulator::VisitException(const Instruction* instr) {
6872 switch (instr->Mask(ExceptionMask)) {
6874 switch (instr->GetImmException()) {
6876 DoUnreachable(instr);
6879 DoTrace(instr);
6882 DoLog(instr);
6885 DoPrintf(instr);
6888 DoRuntimeCall(instr);
6893 DoConfigureCPUFeatures(instr);
6896 DoSaveCPUFeatures(instr);
6899 DoRestoreCPUFeatures(instr);
6928 void Simulator::VisitCrypto2RegSHA(const Instruction* instr) {
6929 VisitUnimplemented(instr);
6933 void Simulator::VisitCrypto3RegSHA(const Instruction* instr) {
6934 VisitUnimplemented(instr);
6938 void Simulator::VisitCryptoAES(const Instruction* instr) {
6939 VisitUnimplemented(instr);
6943 void Simulator::VisitNEON2RegMisc(const Instruction* instr) {
6944 NEONFormatDecoder nfd(instr);
6958 SimVRegister& rd = ReadVRegister(instr->GetRd());
6959 SimVRegister& rn = ReadVRegister(instr->GetRn());
6961 if (instr->Mask(NEON2RegMiscOpcode) <= NEON_NEG_opcode) {
6964 switch (instr->Mask(NEON2RegMiscMask)) {
7030 switch (instr->GetFPType()) {
7050 switch (instr->Mask(NEON2RegMiscFPMask)) {
7061 if (instr->Mask(NEON_Q)) {
7068 if (instr->Mask(NEON_Q)) {
7075 if (instr->Mask(NEON_Q)) {
7187 if ((NEON_XTN_opcode <= instr->Mask(NEON2RegMiscOpcode)) &&
7188 (instr->Mask(NEON2RegMiscOpcode) <= NEON_UQXTN_opcode)) {
7189 switch (instr->Mask(NEON2RegMiscMask)) {
7204 if (instr->Mask(NEON_Q)) {
7224 void Simulator::VisitNEON2RegMiscFP16(const Instruction* instr) {
7226 NEONFormatDecoder nfd(instr);
7231 SimVRegister& rd = ReadVRegister(instr->GetRd());
7232 SimVRegister& rn = ReadVRegister(instr->GetRn());
7234 switch (instr->Mask(NEON2RegMiscFP16Mask)) {
7329 void Simulator::VisitNEON3Same(const Instruction* instr) {
7330 NEONFormatDecoder nfd(instr);
7331 SimVRegister& rd = ReadVRegister(instr->GetRd());
7332 SimVRegister& rn = ReadVRegister(instr->GetRn());
7333 SimVRegister& rm = ReadVRegister(instr->GetRm());
7335 if (instr->Mask(NEON3SameLogicalFMask) == NEON3SameLogicalFixed) {
7337 switch (instr->Mask(NEON3SameLogicalMask)) {
7365 } else if (instr->Mask(NEON3SameFPFMask) == NEON3SameFPFixed) {
7367 switch (instr->Mask(NEON3SameFPMask)) {
7442 switch (instr->Mask(NEON3SameFHMMask)) {
7461 switch (instr->Mask(NEON3SameMask)) {
7604 void Simulator::VisitNEON3SameFP16(const Instruction* instr) {
7605 NEONFormatDecoder nfd(instr);
7606 SimVRegister& rd = ReadVRegister(instr->GetRd());
7607 SimVRegister& rn = ReadVRegister(instr->GetRn());
7608 SimVRegister& rm = ReadVRegister(instr->GetRm());
7611 switch (instr->Mask(NEON3SameFP16Mask)) {
7661 void Simulator::VisitNEON3SameExtra(const Instruction* instr) {
7662 NEONFormatDecoder nfd(instr);
7663 SimVRegister& rd = ReadVRegister(instr->GetRd());
7664 SimVRegister& rn = ReadVRegister(instr->GetRn());
7665 SimVRegister& rm = ReadVRegister(instr->GetRm());
7671 rot = instr->GetImmRotFcmlaVec();
7675 rot = instr->GetImmRotFcadd();
7697 void Simulator::VisitNEON3Different(const Instruction* instr) {
7698 NEONFormatDecoder nfd(instr);
7702 SimVRegister& rd = ReadVRegister(instr->GetRd());
7703 SimVRegister& rn = ReadVRegister(instr->GetRn());
7704 SimVRegister& rm = ReadVRegister(instr->GetRm());
7706 switch (instr->Mask(NEON3DifferentMask)) {
7869 void Simulator::VisitNEONAcrossLanes(const Instruction* instr) {
7870 NEONFormatDecoder nfd(instr);
7874 SimVRegister& rd = ReadVRegister(instr->GetRd());
7875 SimVRegister& rn = ReadVRegister(instr->GetRn());
7877 if (instr->Mask(NEONAcrossLanesFP16FMask) == NEONAcrossLanesFP16Fixed) {
7879 switch (instr->Mask(NEONAcrossLanesFP16Mask)) {
7895 } else if (instr->Mask(NEONAcrossLanesFPFMask) == NEONAcrossLanesFPFixed) {
7899 switch (instr->Mask(NEONAcrossLanesFPMask)) {
7918 switch (instr->Mask(NEONAcrossLanesMask)) {
7946 void Simulator::SimulateNEONMulByElementLong(const Instruction* instr) {
7947 NEONFormatDecoder nfd(instr);
7950 SimVRegister& rd = ReadVRegister(instr->GetRd());
7951 SimVRegister& rn = ReadVRegister(instr->GetRn());
7953 int rm_reg = instr->GetRm();
7954 int index = (instr->GetNEONH() << 1) | instr->GetNEONL();
7955 if (instr->GetNEONSize() == 1) {
7956 rm_reg = instr->GetRmLow16();
7957 index = (index << 1) | instr->GetNEONM();
7966 bool is_2 = instr->Mask(NEON_Q) ? true : false;
8001 void Simulator::SimulateNEONFPMulByElementLong(const Instruction* instr) {
8002 VectorFormat vform = instr->GetNEONQ() ? kFormat4S : kFormat2S;
8003 SimVRegister& rd = ReadVRegister(instr->GetRd());
8004 SimVRegister& rn = ReadVRegister(instr->GetRn());
8005 SimVRegister& rm = ReadVRegister(instr->GetRmLow16());
8008 (instr->GetNEONH() << 2) | (instr->GetNEONL() << 1) | instr->GetNEONM();
8028 void Simulator::SimulateNEONFPMulByElement(const Instruction* instr) {
8029 NEONFormatDecoder nfd(instr);
8035 SimVRegister& rd = ReadVRegister(instr->GetRd());
8036 SimVRegister& rn = ReadVRegister(instr->GetRn());
8038 int rm_reg = instr->GetRm();
8040 (instr->GetNEONH() << 2) | (instr->GetNEONL() << 1) | instr->GetNEONM();
8048 VIXL_ASSERT(instr->GetNEONL() == 0);
8076 void Simulator::SimulateNEONComplexMulByElement(const Instruction* instr) {
8077 VectorFormat vform = instr->GetNEONQ() ? kFormat8H : kFormat4H;
8078 SimVRegister& rd = ReadVRegister(instr->GetRd());
8079 SimVRegister& rn = ReadVRegister(instr->GetRn());
8080 SimVRegister& rm = ReadVRegister(instr->GetRm());
8081 int index = (instr->GetNEONH() << 1) | instr->GetNEONL();
8089 fcmla(vform, rd, rn, rm, index, instr->GetImmRotFcmlaSca());
8096 void Simulator::SimulateNEONDotProdByElement(const Instruction* instr) {
8097 VectorFormat vform = instr->GetNEONQ() ? kFormat4S : kFormat2S;
8099 SimVRegister& rd = ReadVRegister(instr->GetRd());
8100 SimVRegister& rn = ReadVRegister(instr->GetRn());
8101 SimVRegister& rm = ReadVRegister(instr->GetRm());
8102 int index = (instr->GetNEONH() << 1) | instr->GetNEONL();
8125 void Simulator::VisitNEONByIndexedElement(const Instruction* instr) {
8126 NEONFormatDecoder nfd(instr);
8129 SimVRegister& rd = ReadVRegister(instr->GetRd());
8130 SimVRegister& rn = ReadVRegister(instr->GetRn());
8132 int rm_reg = instr->GetRm();
8133 int index = (instr->GetNEONH() << 1) | instr->GetNEONL();
8137 index = (index << 1) | instr->GetNEONM();
8168 void Simulator::VisitNEONCopy(const Instruction* instr) {
8169 NEONFormatDecoder nfd(instr, NEONFormatDecoder::TriangularFormatMap());
8172 SimVRegister& rd = ReadVRegister(instr->GetRd());
8173 SimVRegister& rn = ReadVRegister(instr->GetRn());
8174 int imm5 = instr->GetImmNEON5();
8178 if (instr->Mask(NEONCopyInsElementMask) == NEON_INS_ELEMENT) {
8179 int imm4 = instr->GetImmNEON4();
8182 } else if (instr->Mask(NEONCopyInsGeneralMask) == NEON_INS_GENERAL) {
8183 ins_immediate(vf, rd, reg_index, ReadXRegister(instr->GetRn()));
8184 } else if (instr->Mask(NEONCopyUmovMask) == NEON_UMOV) {
8187 WriteXRegister(instr->GetRd(), value);
8188 } else if (instr->Mask(NEONCopyUmovMask) == NEON_SMOV) {
8190 if (instr->GetNEONQ()) {
8191 WriteXRegister(instr->GetRd(), value);
8193 WriteWRegister(instr->GetRd(), (int32_t)value);
8195 } else if (instr->Mask(NEONCopyDupElementMask) == NEON_DUP_ELEMENT) {
8197 } else if (instr->Mask(NEONCopyDupGeneralMask) == NEON_DUP_GENERAL) {
8198 dup_immediate(vf, rd, ReadXRegister(instr->GetRn()));
8205 void Simulator::VisitNEONExtract(const Instruction* instr) {
8206 NEONFormatDecoder nfd(instr, NEONFormatDecoder::LogicalFormatMap());
8208 SimVRegister& rd = ReadVRegister(instr->GetRd());
8209 SimVRegister& rn = ReadVRegister(instr->GetRn());
8210 SimVRegister& rm = ReadVRegister(instr->GetRm());
8211 if (instr->Mask(NEONExtractMask) == NEON_EXT) {
8212 int index = instr->GetImmNEONExt();
8220 void Simulator::NEONLoadStoreMultiStructHelper(const Instruction* instr,
8222 NEONFormatDecoder nfd(instr, NEONFormatDecoder::LoadStoreFormatMap());
8225 uint64_t addr_base = ReadXRegister(instr->GetRn(), Reg31IsStackPointer);
8231 reg[i] = (instr->GetRt() + i) % kNumberOfVRegisters;
8241 if ((instr->ExtractBit(23) == 0) && (instr->ExtractBits(20, 16) != 0)) {
8247 switch (instr->Mask(NEONLoadStoreMultiStructPostIndexMask)) {
8370 int rm = instr->GetRm();
8375 WriteXRegister(instr->GetRn(),
8385 void Simulator::VisitNEONLoadStoreMultiStruct(const Instruction* instr) {
8386 NEONLoadStoreMultiStructHelper(instr, Offset);
8391 const Instruction* instr) {
8392 NEONLoadStoreMultiStructHelper(instr, PostIndex);
8396 void Simulator::NEONLoadStoreSingleStructHelper(const Instruction* instr,
8398 uint64_t addr = ReadXRegister(instr->GetRn(), Reg31IsStackPointer);
8399 int rt = instr->GetRt();
8404 if ((instr->ExtractBit(23) == 0) && (instr->ExtractBits(20, 16) != 0)) {
8414 NEONFormatDecoder nfd(instr, NEONFormatDecoder::LoadStoreFormatMap());
8418 switch (instr->Mask(NEONLoadStoreSingleStructPostIndexMask)) {
8483 vf = ((instr->GetNEONLSSize() & 1) == 0) ? kFormat4S : kFormat2D;
8505 int lane = instr->GetNEONLSIndex(index_shift);
8510 switch (instr->Mask(NEONLoadStoreSingleLenMask)) {
8611 int rm = instr->GetRm();
8613 WriteXRegister(instr->GetRn(),
8622 void Simulator::VisitNEONLoadStoreSingleStruct(const Instruction* instr) {
8623 NEONLoadStoreSingleStructHelper(instr, Offset);
8628 const Instruction* instr) {
8629 NEONLoadStoreSingleStructHelper(instr, PostIndex);
8633 void Simulator::VisitNEONModifiedImmediate(const Instruction* instr) {
8634 SimVRegister& rd = ReadVRegister(instr->GetRd());
8635 int cmode = instr->GetNEONCmode();
8641 int half_enc = instr->ExtractBit(11);
8642 int q = instr->GetNEONQ();
8643 int op_bit = instr->GetNEONModImmOp();
8644 uint64_t imm8 = instr->GetImmNEONabcdefgh();
8684 imm = Float16ToRawbits(instr->GetImmNEONFP16());
8687 imm = FloatToRawbits(instr->GetImmNEONFP32());
8690 imm = DoubleToRawbits(instr->GetImmNEONFP64());
8693 VisitUnallocated(instr);
8740 VisitUnimplemented(instr);
8745 void Simulator::VisitNEONScalar2RegMisc(const Instruction* instr) {
8746 NEONFormatDecoder nfd(instr, NEONFormatDecoder::ScalarFormatMap());
8749 SimVRegister& rd = ReadVRegister(instr->GetRd());
8750 SimVRegister& rn = ReadVRegister(instr->GetRn());
8752 if (instr->Mask(NEON2RegMiscOpcode) <= NEON_NEG_scalar_opcode) {
8755 switch (instr->Mask(NEONScalar2RegMiscMask)) {
8799 switch (instr->Mask(NEONScalar2RegMiscFPMask)) {
8863 VIXL_ASSERT(instr->ExtractBit(22) == 1);
8867 switch (instr->Mask(NEONScalar2RegMiscMask)) {
8885 void Simulator::VisitNEONScalar2RegMiscFP16(const Instruction* instr) {
8889 SimVRegister& rd = ReadVRegister(instr->GetRd());
8890 SimVRegister& rn = ReadVRegister(instr->GetRn());
8892 switch (instr->Mask(NEONScalar2RegMiscFP16Mask)) {
8957 void Simulator::VisitNEONScalar3Diff(const Instruction* instr) {
8958 NEONFormatDecoder nfd(instr, NEONFormatDecoder::LongScalarFormatMap());
8961 SimVRegister& rd = ReadVRegister(instr->GetRd());
8962 SimVRegister& rn = ReadVRegister(instr->GetRn());
8963 SimVRegister& rm = ReadVRegister(instr->GetRm());
8964 switch (instr->Mask(NEONScalar3DiffMask)) {
8980 void Simulator::VisitNEONScalar3Same(const Instruction* instr) {
8981 NEONFormatDecoder nfd(instr, NEONFormatDecoder::ScalarFormatMap());
8984 SimVRegister& rd = ReadVRegister(instr->GetRd());
8985 SimVRegister& rn = ReadVRegister(instr->GetRn());
8986 SimVRegister& rm = ReadVRegister(instr->GetRm());
8988 if (instr->Mask(NEONScalar3SameFPFMask) == NEONScalar3SameFPFixed) {
8990 switch (instr->Mask(NEONScalar3SameFPMask)) {
9022 switch (instr->Mask(NEONScalar3SameMask)) {
9095 void Simulator::VisitNEONScalar3SameFP16(const Instruction* instr) {
9096 SimVRegister& rd = ReadVRegister(instr->GetRd());
9097 SimVRegister& rn = ReadVRegister(instr->GetRn());
9098 SimVRegister& rm = ReadVRegister(instr->GetRm());
9100 switch (instr->Mask(NEONScalar3SameFP16Mask)) {
9134 void Simulator::VisitNEONScalar3SameExtra(const Instruction* instr) {
9135 NEONFormatDecoder nfd(instr, NEONFormatDecoder::ScalarFormatMap());
9138 SimVRegister& rd = ReadVRegister(instr->GetRd());
9139 SimVRegister& rn = ReadVRegister(instr->GetRn());
9140 SimVRegister& rm = ReadVRegister(instr->GetRm());
9142 switch (instr->Mask(NEONScalar3SameExtraMask)) {
9154 void Simulator::VisitNEONScalarByIndexedElement(const Instruction* instr) {
9155 NEONFormatDecoder nfd(instr, NEONFormatDecoder::LongScalarFormatMap());
9159 SimVRegister& rd = ReadVRegister(instr->GetRd());
9160 SimVRegister& rn = ReadVRegister(instr->GetRn());
9163 int rm_reg = instr->GetRm();
9164 int index = (instr->GetNEONH() << 1) | instr->GetNEONL();
9165 if (instr->GetNEONSize() == 1) {
9167 index = (index << 1) | instr->GetNEONM();
9170 switch (instr->Mask(NEONScalarByIndexedElementMask)) {
9198 index = instr->GetNEONH();
9199 if (instr->GetFPType() == 0) {
9200 index = (index << 2) | (instr->GetNEONL() << 1) | instr->GetNEONM();
9203 } else if ((instr->GetFPType() & 1) == 0) {
9204 index = (index << 1) | instr->GetNEONL();
9206 switch (instr->Mask(NEONScalarByIndexedElementFPMask)) {
9232 void Simulator::VisitNEONScalarCopy(const Instruction* instr) {
9233 NEONFormatDecoder nfd(instr, NEONFormatDecoder::TriangularScalarFormatMap());
9236 SimVRegister& rd = ReadVRegister(instr->GetRd());
9237 SimVRegister& rn = ReadVRegister(instr->GetRn());
9239 if (instr->Mask(NEONScalarCopyMask) == NEON_DUP_ELEMENT_scalar) {
9240 int imm5 = instr->GetImmNEON5();
9250 void Simulator::VisitNEONScalarPairwise(const Instruction* instr) {
9251 NEONFormatDecoder nfd(instr, NEONFormatDecoder::FPScalarPairwiseFormatMap());
9254 SimVRegister& rd = ReadVRegister(instr->GetRd());
9255 SimVRegister& rn = ReadVRegister(instr->GetRn());
9256 switch (instr->Mask(NEONScalarPairwiseMask)) {
9260 NEONFormatDecoder nfd_addp(instr, NEONFormatDecoder::FPScalarFormatMap());
9290 void Simulator::VisitNEONScalarShiftImmediate(const Instruction* instr) {
9291 SimVRegister& rd = ReadVRegister(instr->GetRd());
9292 SimVRegister& rn = ReadVRegister(instr->GetRn());
9312 NEONFormatDecoder nfd(instr, &map);
9315 int highest_set_bit = HighestSetBitPosition(instr->GetImmNEONImmh());
9316 int immh_immb = instr->GetImmNEONImmhImmb();
9319 switch (instr->Mask(NEONScalarShiftImmediateMask)) {
9398 void Simulator::VisitNEONShiftImmediate(const Instruction* instr) {
9399 SimVRegister& rd = ReadVRegister(instr->GetRd());
9400 SimVRegister& rn = ReadVRegister(instr->GetRn());
9414 NEONFormatDecoder nfd(instr, &map);
9423 int highest_set_bit = HighestSetBitPosition(instr->GetImmNEONImmh());
9424 int immh_immb = instr->GetImmNEONImmhImmb();
9428 switch (instr->Mask(NEONShiftImmediateMask)) {
9485 if (instr->Mask(NEON_Q)) {
9493 if (instr->Mask(NEON_Q)) {
9500 if (instr->Mask(NEON_Q)) {
9507 if (instr->Mask(NEON_Q)) {
9514 if (instr->Mask(NEON_Q)) {
9521 if (instr->Mask(NEON_Q)) {
9528 if (instr->Mask(NEON_Q)) {
9535 if (instr->Mask(NEON_Q)) {
9542 if (instr->Mask(NEON_Q)) {
9549 if (instr->Mask(NEON_Q)) {
9561 void Simulator::VisitNEONTable(const Instruction* instr) {
9562 NEONFormatDecoder nfd(instr, NEONFormatDecoder::LogicalFormatMap());
9565 SimVRegister& rd = ReadVRegister(instr->GetRd());
9566 SimVRegister& rn = ReadVRegister(instr->GetRn());
9567 SimVRegister& rn2 = ReadVRegister((instr->GetRn() + 1) % kNumberOfVRegisters);
9568 SimVRegister& rn3 = ReadVRegister((instr->GetRn() + 2) % kNumberOfVRegisters);
9569 SimVRegister& rn4 = ReadVRegister((instr->GetRn() + 3) % kNumberOfVRegisters);
9570 SimVRegister& rm = ReadVRegister(instr->GetRm());
9572 switch (instr->Mask(NEONTableMask)) {
9603 void Simulator::VisitNEONPerm(const Instruction* instr) {
9604 NEONFormatDecoder nfd(instr);
9607 SimVRegister& rd = ReadVRegister(instr->GetRd());
9608 SimVRegister& rn = ReadVRegister(instr->GetRn());
9609 SimVRegister& rm = ReadVRegister(instr->GetRm());
9611 switch (instr->Mask(NEONPermMask)) {
9635 void Simulator::VisitSVEAddressGeneration(const Instruction* instr) {
9636 SimVRegister& zd = ReadVRegister(instr->GetRd());
9637 SimVRegister& zn = ReadVRegister(instr->GetRn());
9638 SimVRegister& zm = ReadVRegister(instr->GetRm());
9644 switch (instr->Mask(SVEAddressGenerationMask)) {
9662 int shift_amount = instr->ExtractBits(11, 10);
9668 const Instruction* instr) {
9669 Instr op = instr->Mask(SVEBitwiseLogicalWithImm_UnpredicatedMask);
9674 int lane_size = instr->GetSVEBitwiseImmLaneSizeInBytesLog2();
9675 uint64_t imm = instr->GetSVEImmLogical();
9681 ReadVRegister(instr->GetRd()),
9691 void Simulator::VisitSVEBroadcastBitmaskImm(const Instruction* instr) {
9692 switch (instr->Mask(SVEBroadcastBitmaskImmMask)) {
9696 int lane_size = instr->GetSVEBitwiseImmLaneSizeInBytesLog2();
9697 uint64_t imm = instr->GetSVEImmLogical();
9699 dup_immediate(vform, ReadVRegister(instr->GetRd()), imm);
9708 void Simulator::VisitSVEBitwiseLogicalUnpredicated(const Instruction* instr) {
9709 SimVRegister& zd = ReadVRegister(instr->GetRd());
9710 SimVRegister& zn = ReadVRegister(instr->GetRn());
9711 SimVRegister& zm = ReadVRegister(instr->GetRm());
9712 Instr op = instr->Mask(SVEBitwiseLogicalUnpredicatedMask);
9737 void Simulator::VisitSVEBitwiseShiftByImm_Predicated(const Instruction* instr) {
9738 SimVRegister& zdn = ReadVRegister(instr->GetRd());
9739 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
9746 switch (instr->Mask(SVEBitwiseShiftByImm_PredicatedMask)) {
9766 instr->GetSVEImmShiftAndLaneSizeLog2(/* is_predicated = */ true);
9785 const Instruction* instr) {
9786 VectorFormat vform = instr->GetSVEVectorFormat();
9787 SimVRegister& zdn = ReadVRegister(instr->GetRd());
9788 SimVRegister& zm = ReadVRegister(instr->GetRn());
9789 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
9866 const Instruction* instr) {
9867 VectorFormat vform = instr->GetSVEVectorFormat();
9868 SimVRegister& zdn = ReadVRegister(instr->GetRd());
9869 SimVRegister& zm = ReadVRegister(instr->GetRn());
9870 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
9875 switch (instr->Mask(SVEBitwiseShiftByWideElements_PredicatedMask)) {
9897 void Simulator::VisitSVEBitwiseShiftUnpredicated(const Instruction* instr) {
9898 SimVRegister& zd = ReadVRegister(instr->GetRd());
9899 SimVRegister& zn = ReadVRegister(instr->GetRn());
9902 switch (instr->Mask(SVEBitwiseShiftUnpredicatedMask)) {
9920 switch (instr->Mask(SVEBitwiseShiftUnpredicatedMask)) {
9926 instr->GetSVEImmShiftAndLaneSizeLog2(/* is_predicated = */ false);
9943 instr->GetSVEVectorFormat(),
9946 ReadVRegister(instr->GetRm()),
9955 void Simulator::VisitSVEIncDecRegisterByElementCount(const Instruction* instr) {
9958 VectorFormat vform = instr->GetSVEVectorFormat();
9960 int pattern = instr->GetImmSVEPredicateConstraint();
9962 int multiplier = instr->ExtractBits(19, 16) + 1;
9964 switch (instr->Mask(SVEIncDecRegisterByElementCountMask)) {
9982 WriteXRegister(instr->GetRd(),
9983 IncDecN(ReadXRegister(instr->GetRd()),
9988 void Simulator::VisitSVEIncDecVectorByElementCount(const Instruction* instr) {
9989 VectorFormat vform = instr->GetSVEVectorFormat();
9994 int pattern = instr->GetImmSVEPredicateConstraint();
9996 int multiplier = instr->ExtractBits(19, 16) + 1;
9998 switch (instr->Mask(SVEIncDecVectorByElementCountMask)) {
10014 SimVRegister& zd = ReadVRegister(instr->GetRd());
10025 const Instruction* instr) {
10028 VectorFormat vform = instr->GetSVEVectorFormat();
10030 int pattern = instr->GetImmSVEPredicateConstraint();
10032 int multiplier = instr->ExtractBits(19, 16) + 1;
10037 switch (instr->Mask(SVESaturatingIncDecRegisterByElementCountMask)) {
10092 WriteXRegister(instr->GetRd(),
10093 IncDecN(ReadXRegister(instr->GetRd()),
10101 const Instruction* instr) {
10102 VectorFormat vform = instr->GetSVEVectorFormat();
10107 int pattern = instr->GetImmSVEPredicateConstraint();
10109 int multiplier = instr->ExtractBits(19, 16) + 1;
10111 SimVRegister& zd = ReadVRegister(instr->GetRd());
10119 switch (instr->Mask(SVESaturatingIncDecVectorByElementCountMask)) {
10146 void Simulator::VisitSVEElementCount(const Instruction* instr) {
10147 switch (instr->Mask(SVEElementCountMask)) {
10161 VectorFormat vform = instr->GetSVEVectorFormat();
10163 int pattern = instr->GetImmSVEPredicateConstraint();
10165 int multiplier = instr->ExtractBits(19, 16) + 1;
10166 WriteXRegister(instr->GetRd(), count * multiplier);
10169 void Simulator::VisitSVEFPAccumulatingReduction(const Instruction* instr) {
10170 VectorFormat vform = instr->GetSVEVectorFormat();
10171 SimVRegister& vdn = ReadVRegister(instr->GetRd());
10172 SimVRegister& zm = ReadVRegister(instr->GetRn());
10173 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
10177 switch (instr->Mask(SVEFPAccumulatingReductionMask)) {
10187 void Simulator::VisitSVEFPArithmetic_Predicated(const Instruction* instr) {
10188 VectorFormat vform = instr->GetSVEVectorFormat();
10189 SimVRegister& zdn = ReadVRegister(instr->GetRd());
10190 SimVRegister& zm = ReadVRegister(instr->GetRn());
10191 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
10196 switch (instr->Mask(SVEFPArithmetic_PredicatedMask)) {
10244 const Instruction* instr) {
10245 VectorFormat vform = instr->GetSVEVectorFormat();
10250 SimVRegister& zdn = ReadVRegister(instr->GetRd());
10251 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
10254 int i1 = instr->ExtractBit(5);
10263 switch (instr->Mask(SVEFPArithmeticWithImm_PredicatedMask)) {
10295 void Simulator::VisitSVEFPTrigMulAddCoefficient(const Instruction* instr) {
10296 VectorFormat vform = instr->GetSVEVectorFormat();
10297 SimVRegister& zd = ReadVRegister(instr->GetRd());
10298 SimVRegister& zm = ReadVRegister(instr->GetRn());
10302 switch (instr->Mask(SVEFPTrigMulAddCoefficientMask)) {
10304 ftmad(vform, zd, zd, zm, instr->ExtractBits(18, 16));
10312 void Simulator::VisitSVEFPArithmeticUnpredicated(const Instruction* instr) {
10313 VectorFormat vform = instr->GetSVEVectorFormat();
10314 SimVRegister& zd = ReadVRegister(instr->GetRd());
10315 SimVRegister& zn = ReadVRegister(instr->GetRn());
10316 SimVRegister& zm = ReadVRegister(instr->GetRm());
10320 switch (instr->Mask(SVEFPArithmeticUnpredicatedMask)) {
10345 void Simulator::VisitSVEFPCompareVectors(const Instruction* instr) {
10346 SimPRegister& pd = ReadPRegister(instr->GetPd());
10347 SimVRegister& zn = ReadVRegister(instr->GetRn());
10348 SimVRegister& zm = ReadVRegister(instr->GetRm());
10349 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
10350 VectorFormat vform = instr->GetSVEVectorFormat();
10355 switch (instr->Mask(SVEFPCompareVectorsMask)) {
10386 void Simulator::VisitSVEFPCompareWithZero(const Instruction* instr) {
10387 SimPRegister& pd = ReadPRegister(instr->GetPd());
10388 SimVRegister& zn = ReadVRegister(instr->GetRn());
10389 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
10390 VectorFormat vform = instr->GetSVEVectorFormat();
10398 switch (instr->Mask(SVEFPCompareWithZeroMask)) {
10426 void Simulator::VisitSVEFPComplexAddition(const Instruction* instr) {
10427 VectorFormat vform = instr->GetSVEVectorFormat();
10433 SimVRegister& zdn = ReadVRegister(instr->GetRd());
10434 SimVRegister& zm = ReadVRegister(instr->GetRn());
10435 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
10436 int rot = instr->ExtractBit(16);
10440 switch (instr->Mask(SVEFPComplexAdditionMask)) {
10451 void Simulator::VisitSVEFPComplexMulAdd(const Instruction* instr) {
10452 VectorFormat vform = instr->GetSVEVectorFormat();
10458 SimVRegister& zda = ReadVRegister(instr->GetRd());
10459 SimVRegister& zn = ReadVRegister(instr->GetRn());
10460 SimVRegister& zm = ReadVRegister(instr->GetRm());
10461 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
10462 int rot = instr->ExtractBits(14, 13);
10466 switch (instr->Mask(SVEFPComplexMulAddMask)) {
10477 void Simulator::VisitSVEFPComplexMulAddIndex(const Instruction* instr) {
10478 SimVRegister& zda = ReadVRegister(instr->GetRd());
10479 SimVRegister& zn = ReadVRegister(instr->GetRn());
10480 int rot = instr->ExtractBits(11, 10);
10481 unsigned zm_code = instr->GetRm();
10485 switch (instr->Mask(SVEFPComplexMulAddIndexMask)) {
10514 void Simulator::VisitSVEFPFastReduction(const Instruction* instr) {
10515 VectorFormat vform = instr->GetSVEVectorFormat();
10516 SimVRegister& vd = ReadVRegister(instr->GetRd());
10517 SimVRegister& zn = ReadVRegister(instr->GetRn());
10518 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
10526 switch (instr->Mask(SVEFPFastReductionMask)) {
10557 void Simulator::VisitSVEFPMulIndex(const Instruction* instr) {
10560 switch (instr->Mask(SVEFPMulIndexMask)) {
10576 SimVRegister& zd = ReadVRegister(instr->GetRd());
10577 SimVRegister& zn = ReadVRegister(instr->GetRn());
10580 dup_elements_to_segments(vform, temp, instr->GetSVEMulZmAndIndex());
10584 void Simulator::VisitSVEFPMulAdd(const Instruction* instr) {
10585 VectorFormat vform = instr->GetSVEVectorFormat();
10586 SimVRegister& zd = ReadVRegister(instr->GetRd());
10587 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
10592 if (instr->ExtractBit(15) == 0) {
10594 SimVRegister& zm = ReadVRegister(instr->GetRm());
10595 SimVRegister& zn = ReadVRegister(instr->GetRn());
10597 switch (instr->Mask(SVEFPMulAddMask)) {
10622 SimVRegister& za = ReadVRegister(instr->GetRm());
10623 SimVRegister& zm = ReadVRegister(instr->GetRn());
10625 switch (instr->Mask(SVEFPMulAddMask)) {
10653 void Simulator::VisitSVEFPMulAddIndex(const Instruction* instr) {
10656 switch (instr->Mask(SVEFPMulAddIndexMask)) {
10676 SimVRegister& zd = ReadVRegister(instr->GetRd());
10677 SimVRegister& zn = ReadVRegister(instr->GetRn());
10680 dup_elements_to_segments(vform, temp, instr->GetSVEMulZmAndIndex());
10681 if (instr->ExtractBit(10) == 1) {
10688 void Simulator::VisitSVEFPConvertToInt(const Instruction* instr) {
10689 SimVRegister& zd = ReadVRegister(instr->GetRd());
10690 SimVRegister& zn = ReadVRegister(instr->GetRn());
10691 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
10695 switch (instr->Mask(SVEFPConvertToIntMask)) {
10741 if (instr->ExtractBit(16) == 0) {
10748 void Simulator::VisitSVEFPConvertPrecision(const Instruction* instr) {
10749 SimVRegister& zd = ReadVRegister(instr->GetRd());
10750 SimVRegister& zn = ReadVRegister(instr->GetRn());
10751 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
10755 switch (instr->Mask(SVEFPConvertPrecisionMask)) {
10788 void Simulator::VisitSVEFPUnaryOp(const Instruction* instr) {
10789 SimVRegister& zd = ReadVRegister(instr->GetRd());
10790 SimVRegister& zn = ReadVRegister(instr->GetRn());
10791 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
10792 VectorFormat vform = instr->GetSVEVectorFormat();
10795 switch (instr->Mask(SVEFPUnaryOpMask)) {
10809 void Simulator::VisitSVEFPRoundToIntegralValue(const Instruction* instr) {
10810 SimVRegister& zd = ReadVRegister(instr->GetRd());
10811 SimVRegister& zn = ReadVRegister(instr->GetRn());
10812 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
10813 VectorFormat vform = instr->GetSVEVectorFormat();
10819 switch (instr->Mask(SVEFPRoundToIntegralValueMask)) {
10850 void Simulator::VisitSVEIntConvertToFP(const Instruction* instr) {
10851 SimVRegister& zd = ReadVRegister(instr->GetRd());
10852 SimVRegister& zn = ReadVRegister(instr->GetRn());
10853 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
10858 switch (instr->Mask(SVEIntConvertToFPMask)) {
10904 if (instr->ExtractBit(16) == 0) {
10911 void Simulator::VisitSVEFPUnaryOpUnpredicated(const Instruction* instr) {
10912 VectorFormat vform = instr->GetSVEVectorFormat();
10913 SimVRegister& zd = ReadVRegister(instr->GetRd());
10914 SimVRegister& zn = ReadVRegister(instr->GetRn());
10919 switch (instr->Mask(SVEFPUnaryOpUnpredicatedMask)) {
10932 void Simulator::VisitSVEIncDecByPredicateCount(const Instruction* instr) {
10933 VectorFormat vform = instr->GetSVEVectorFormat();
10934 SimPRegister& pg = ReadPRegister(instr->ExtractBits(8, 5));
10938 if (instr->ExtractBit(11) == 0) {
10939 SimVRegister& zdn = ReadVRegister(instr->GetRd());
10940 switch (instr->Mask(SVEIncDecByPredicateCountMask)) {
10964 bool is_saturating = (instr->ExtractBit(18) == 0);
10966 is_saturating ? instr->ExtractBit(17) : instr->ExtractBit(16);
10967 bool is_signed = (instr->ExtractBit(16) == 0);
10968 bool sf = is_saturating ? (instr->ExtractBit(10) != 0) : true;
10971 switch (instr->Mask(SVEIncDecByPredicateCountMask)) {
10982 WriteXRegister(instr->GetRd(),
10983 IncDecN(ReadXRegister(instr->GetRd()),
11048 void Simulator::VisitSVEIndexGeneration(const Instruction* instr) {
11049 VectorFormat vform = instr->GetSVEVectorFormat();
11050 SimVRegister& zd = ReadVRegister(instr->GetRd());
11051 switch (instr->Mask(SVEIndexGenerationMask)) {
11056 uint64_t start = instr->ExtractBit(10) ? ReadXRegister(instr->GetRn())
11057 : instr->ExtractSignedBits(9, 5);
11058 uint64_t step = instr->ExtractBit(11) ? ReadXRegister(instr->GetRm())
11059 : instr->ExtractSignedBits(20, 16);
11069 void Simulator::VisitSVEIntArithmeticUnpredicated(const Instruction* instr) {
11070 VectorFormat vform = instr->GetSVEVectorFormat();
11071 SimVRegister& zd = ReadVRegister(instr->GetRd());
11072 SimVRegister& zn = ReadVRegister(instr->GetRn());
11073 SimVRegister& zm = ReadVRegister(instr->GetRm());
11074 switch (instr->Mask(SVEIntArithmeticUnpredicatedMask)) {
11100 const Instruction* instr) {
11101 VectorFormat vform = instr->GetSVEVectorFormat();
11102 SimVRegister& zdn = ReadVRegister(instr->GetRd());
11103 SimVRegister& zm = ReadVRegister(instr->GetRn());
11104 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
11107 switch (instr->Mask(SVEIntAddSubtractVectors_PredicatedMask)) {
11124 void Simulator::VisitSVEBitwiseLogical_Predicated(const Instruction* instr) {
11125 VectorFormat vform = instr->GetSVEVectorFormat();
11126 SimVRegister& zdn = ReadVRegister(instr->GetRd());
11127 SimVRegister& zm = ReadVRegister(instr->GetRn());
11128 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
11131 switch (instr->Mask(SVEBitwiseLogical_PredicatedMask)) {
11151 void Simulator::VisitSVEIntMulVectors_Predicated(const Instruction* instr) {
11152 VectorFormat vform = instr->GetSVEVectorFormat();
11153 SimVRegister& zdn = ReadVRegister(instr->GetRd());
11154 SimVRegister& zm = ReadVRegister(instr->GetRn());
11155 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
11158 switch (instr->Mask(SVEIntMulVectors_PredicatedMask)) {
11176 const Instruction* instr) {
11177 VectorFormat vform = instr->GetSVEVectorFormat();
11178 SimVRegister& zdn = ReadVRegister(instr->GetRd());
11179 SimVRegister& zm = ReadVRegister(instr->GetRn());
11180 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
11183 switch (instr->Mask(SVEIntMinMaxDifference_PredicatedMask)) {
11209 void Simulator::VisitSVEIntMulImm_Unpredicated(const Instruction* instr) {
11210 VectorFormat vform = instr->GetSVEVectorFormat();
11211 SimVRegister& zd = ReadVRegister(instr->GetRd());
11214 switch (instr->Mask(SVEIntMulImm_UnpredicatedMask)) {
11216 dup_immediate(vform, scratch, instr->GetImmSVEIntWideSigned());
11225 void Simulator::VisitSVEIntDivideVectors_Predicated(const Instruction* instr) {
11226 VectorFormat vform = instr->GetSVEVectorFormat();
11227 SimVRegister& zdn = ReadVRegister(instr->GetRd());
11228 SimVRegister& zm = ReadVRegister(instr->GetRn());
11229 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
11234 switch (instr->Mask(SVEIntDivideVectors_PredicatedMask)) {
11254 void Simulator::VisitSVEIntMinMaxImm_Unpredicated(const Instruction* instr) {
11255 VectorFormat vform = instr->GetSVEVectorFormat();
11256 SimVRegister& zd = ReadVRegister(instr->GetRd());
11259 uint64_t unsigned_imm = instr->GetImmSVEIntWideUnsigned();
11260 int64_t signed_imm = instr->GetImmSVEIntWideSigned();
11262 switch (instr->Mask(SVEIntMinMaxImm_UnpredicatedMask)) {
11286 const Instruction* instr) {
11287 unsigned rn_code = instr->GetRn();
11288 unsigned rm_code = instr->GetRm();
11289 SimPRegister& pd = ReadPRegister(instr->GetPd());
11290 VectorFormat vform = instr->GetSVEVectorFormat();
11292 bool is_64_bit = instr->ExtractBit(12) == 1;
11353 const Instruction* instr) {
11354 unsigned rn_code = instr->GetRn();
11355 unsigned rm_code = instr->GetRm();
11356 bool is_64_bit = instr->ExtractBit(22) == 1;
11360 switch (instr->Mask(SVEConditionallyTerminateScalarsMask)) {
11376 void Simulator::VisitSVEIntCompareSignedImm(const Instruction* instr) {
11379 switch (instr->Mask(SVEIntCompareSignedImmMask)) {
11405 VectorFormat vform = instr->GetSVEVectorFormat();
11409 ExtractSignedBitfield64(4, 0, instr->ExtractBits(20, 16)));
11412 ReadPRegister(instr->GetPd()),
11413 ReadPRegister(instr->GetPgLow8()),
11415 : ReadVRegister(instr->GetRn()),
11416 commute_inputs ? ReadVRegister(instr->GetRn())
11420 void Simulator::VisitSVEIntCompareUnsignedImm(const Instruction* instr) {
11423 switch (instr->Mask(SVEIntCompareUnsignedImmMask)) {
11443 VectorFormat vform = instr->GetSVEVectorFormat();
11445 dup_immediate(vform, src2, instr->ExtractBits(20, 14));
11448 ReadPRegister(instr->GetPd()),
11449 ReadPRegister(instr->GetPgLow8()),
11451 : ReadVRegister(instr->GetRn()),
11452 commute_inputs ? ReadVRegister(instr->GetRn())
11456 void Simulator::VisitSVEIntCompareVectors(const Instruction* instr) {
11457 Instr op = instr->Mask(SVEIntCompareVectorsMask);
11519 instr->GetSVEVectorFormat(),
11520 ReadPRegister(instr->GetPd()),
11521 ReadPRegister(instr->GetPgLow8()),
11522 ReadVRegister(instr->GetRn()),
11523 ReadVRegister(instr->GetRm()),
11527 void Simulator::VisitSVEFPExponentialAccelerator(const Instruction* instr) {
11528 VectorFormat vform = instr->GetSVEVectorFormat();
11529 SimVRegister& zd = ReadVRegister(instr->GetRd());
11530 SimVRegister& zn = ReadVRegister(instr->GetRn());
11535 switch (instr->Mask(SVEFPExponentialAcceleratorMask)) {
11545 void Simulator::VisitSVEFPTrigSelectCoefficient(const Instruction* instr) {
11546 VectorFormat vform = instr->GetSVEVectorFormat();
11547 SimVRegister& zd = ReadVRegister(instr->GetRd());
11548 SimVRegister& zn = ReadVRegister(instr->GetRn());
11549 SimVRegister& zm = ReadVRegister(instr->GetRm());
11554 switch (instr->Mask(SVEFPTrigSelectCoefficientMask)) {
11565 const Instruction* instr) {
11566 SimVRegister& zd = ReadVRegister(instr->GetRd());
11567 SimVRegister& zn = ReadVRegister(instr->GetRn());
11569 switch (instr->Mask(SVEConstructivePrefix_UnpredicatedMask)) {
11579 void Simulator::VisitSVEIntMulAddPredicated(const Instruction* instr) {
11580 VectorFormat vform = instr->GetSVEVectorFormat();
11582 SimVRegister& zd = ReadVRegister(instr->GetRd());
11583 SimVRegister& zm = ReadVRegister(instr->GetRm());
11586 switch (instr->Mask(SVEIntMulAddPredicatedMask)) {
11588 mla(vform, result, zd, ReadVRegister(instr->GetRn()), zm);
11591 mls(vform, result, zd, ReadVRegister(instr->GetRn()), zm);
11595 mla(vform, result, ReadVRegister(instr->GetRn()), zd, zm);
11599 mls(vform, result, ReadVRegister(instr->GetRn()), zd, zm);
11606 mov_merging(vform, zd, ReadPRegister(instr->GetPgLow8()), result);
11609 void Simulator::VisitSVEIntMulAddUnpredicated(const Instruction* instr) {
11610 VectorFormat vform = instr->GetSVEVectorFormat();
11611 SimVRegister& zda = ReadVRegister(instr->GetRd());
11612 SimVRegister& zn = ReadVRegister(instr->GetRn());
11613 SimVRegister& zm = ReadVRegister(instr->GetRm());
11631 void Simulator::VisitSVEMovprfx(const Instruction* instr) {
11632 VectorFormat vform = instr->GetSVEVectorFormat();
11633 SimVRegister& zn = ReadVRegister(instr->GetRn());
11634 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
11635 SimVRegister& zd = ReadVRegister(instr->GetRd());
11637 switch (instr->Mask(SVEMovprfxMask)) {
11639 if (instr->ExtractBit(16)) {
11651 void Simulator::VisitSVEIntReduction(const Instruction* instr) {
11652 VectorFormat vform = instr->GetSVEVectorFormat();
11653 SimVRegister& vd = ReadVRegister(instr->GetRd());
11654 SimVRegister& zn = ReadVRegister(instr->GetRn());
11655 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
11657 if (instr->Mask(SVEIntReductionLogicalFMask) == SVEIntReductionLogicalFixed) {
11658 switch (instr->Mask(SVEIntReductionLogicalMask)) {
11673 switch (instr->Mask(SVEIntReductionMask)) {
11699 void Simulator::VisitSVEIntUnaryArithmeticPredicated(const Instruction* instr) {
11700 VectorFormat vform = instr->GetSVEVectorFormat();
11701 SimVRegister& zn = ReadVRegister(instr->GetRn());
11704 switch (instr->Mask(SVEIntUnaryArithmeticPredicatedMask)) {
11735 sxt(vform, result, zn, (kBitsPerByte << instr->ExtractBits(18, 17)));
11740 uxt(vform, result, zn, (kBitsPerByte << instr->ExtractBits(18, 17)));
11747 SimVRegister& zd = ReadVRegister(instr->GetRd());
11748 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
11752 void Simulator::VisitSVECopyFPImm_Predicated(const Instruction* instr) {
11754 VIXL_ASSERT(instr->Mask(SVECopyFPImm_PredicatedMask) == FCPY_z_p_i);
11756 VectorFormat vform = instr->GetSVEVectorFormat();
11757 SimPRegister& pg = ReadPRegister(instr->ExtractBits(19, 16));
11758 SimVRegister& zd = ReadVRegister(instr->GetRd());
11763 switch (instr->Mask(SVECopyFPImm_PredicatedMask)) {
11765 int imm8 = instr->ExtractBits(12, 5);
11779 const Instruction* instr) {
11780 VectorFormat vform = instr->GetSVEVectorFormat();
11781 SimVRegister& zd = ReadVRegister(instr->GetRd());
11784 uint64_t imm = instr->GetImmSVEIntWideUnsigned();
11785 imm <<= instr->ExtractBit(13) * 8;
11787 switch (instr->Mask(SVEIntAddSubtractImm_UnpredicatedMask)) {
11815 void Simulator::VisitSVEBroadcastIntImm_Unpredicated(const Instruction* instr) {
11816 SimVRegister& zd = ReadVRegister(instr->GetRd());
11818 VectorFormat format = instr->GetSVEVectorFormat();
11819 int64_t imm = instr->GetImmSVEIntWideSigned();
11820 int shift = instr->ExtractBit(13) * 8;
11823 switch (instr->Mask(SVEBroadcastIntImm_UnpredicatedMask)) {
11838 void Simulator::VisitSVEBroadcastFPImm_Unpredicated(const Instruction* instr) {
11839 VectorFormat vform = instr->GetSVEVectorFormat();
11840 SimVRegister& zd = ReadVRegister(instr->GetRd());
11842 switch (instr->Mask(SVEBroadcastFPImm_UnpredicatedMask)) {
11846 dup_immediate(vform, zd, Float16ToRawbits(instr->GetSVEImmFP16()));
11849 dup_immediate(vform, zd, FloatToRawbits(instr->GetSVEImmFP32()));
11852 dup_immediate(vform, zd, DoubleToRawbits(instr->GetSVEImmFP64()));
11865 const Instruction* instr) {
11866 switch (instr->Mask(
11878 SVEOffsetModifier mod = (instr->ExtractBit(22) == 1) ? SVE_SXTW : SVE_UXTW;
11879 SVEGatherLoadScalarPlusVectorHelper(instr, kFormatVnS, mod);
11883 const Instruction* instr) {
11884 switch (instr->Mask(SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsMask)) {
11901 SVEOffsetModifier mod = (instr->ExtractBit(22) == 1) ? SVE_SXTW : SVE_UXTW;
11902 SVEGatherLoadScalarPlusVectorHelper(instr, kFormatVnS, mod);
11906 const Instruction* instr) {
11907 switch (instr->Mask(SVE32BitGatherLoad_VectorPlusImmMask)) {
11945 const Instruction* instr) {
11947 instr->Mask(SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsMask)) {
11956 SVEOffsetModifier mod = (instr->ExtractBit(22) == 1) ? SVE_SXTW : SVE_UXTW;
11957 SVEGatherLoadScalarPlusVectorHelper(instr, kFormatVnS, mod);
11961 const Instruction* instr) {
11963 instr->Mask(SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsMask)) {
11977 const Instruction* instr) {
11978 switch (instr->Mask(SVE32BitGatherPrefetch_VectorPlusImmMask)) {
11992 const Instruction* instr) {
11993 switch (instr->Mask(SVEContiguousPrefetch_ScalarPlusImmMask)) {
12007 const Instruction* instr) {
12008 switch (instr->Mask(SVEContiguousPrefetch_ScalarPlusScalarMask)) {
12014 if (instr->GetRm() == kZeroRegCode) {
12024 void Simulator::VisitSVELoadAndBroadcastElement(const Instruction* instr) {
12026 switch (instr->Mask(SVELoadAndBroadcastElementMask)) {
12054 int msize_in_bytes_log2 = instr->GetSVEMsizeFromDtype(is_signed);
12055 int esize_in_bytes_log2 = instr->GetSVEEsizeFromDtype(is_signed, 13);
12058 uint64_t offset = instr->ExtractBits(21, 16) << msize_in_bytes_log2;
12059 uint64_t base = ReadXRegister(instr->GetRn(), Reg31IsStackPointer) + offset;
12065 ReadVRegister(instr->GetRt()),
12066 ReadPRegister(instr->GetPgLow8()),
12070 void Simulator::VisitSVELoadPredicateRegister(const Instruction* instr) {
12071 switch (instr->Mask(SVELoadPredicateRegisterMask)) {
12073 SimPRegister& pt = ReadPRegister(instr->GetPt());
12075 int imm9 = (instr->ExtractBits(21, 16) << 3) | instr->ExtractBits(12, 10);
12077 uint64_t base = ReadXRegister(instr->GetRn(), Reg31IsStackPointer);
12082 LogPRead(instr->GetPt(), address);
12091 void Simulator::VisitSVELoadVectorRegister(const Instruction* instr) {
12092 switch (instr->Mask(SVELoadVectorRegisterMask)) {
12094 SimVRegister& zt = ReadVRegister(instr->GetRt());
12096 int imm9 = (instr->ExtractBits(21, 16) << 3) | instr->ExtractBits(12, 10);
12098 uint64_t base = ReadXRegister(instr->GetRn(), Reg31IsStackPointer);
12103 LogZRead(instr->GetRt(), address);
12113 const Instruction* instr) {
12114 switch (instr->Mask(
12132 SVEOffsetModifier mod = (instr->ExtractBit(22) == 1) ? SVE_SXTW : SVE_UXTW;
12133 SVEGatherLoadScalarPlusVectorHelper(instr, kFormatVnD, mod);
12137 const Instruction* instr) {
12138 switch (instr->Mask(SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsMask)) {
12155 SVEGatherLoadScalarPlusVectorHelper(instr, kFormatVnD, SVE_LSL);
12159 const Instruction* instr) {
12160 switch (instr->Mask(SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsMask)) {
12181 SVEGatherLoadScalarPlusVectorHelper(instr,
12187 const Instruction* instr) {
12188 switch (instr->Mask(
12210 SVEOffsetModifier mod = (instr->ExtractBit(22) == 1) ? SVE_SXTW : SVE_UXTW;
12211 SVEGatherLoadScalarPlusVectorHelper(instr, kFormatVnD, mod);
12215 const Instruction* instr) {
12216 switch (instr->Mask(SVE64BitGatherLoad_VectorPlusImmMask)) {
12236 bool is_signed = instr->ExtractBit(14) == 0;
12237 bool is_ff = instr->ExtractBit(13) == 1;
12239 int msize_in_bytes_log2 = instr->ExtractBits(24, 23);
12240 uint64_t imm = instr->ExtractBits(20, 16) << msize_in_bytes_log2;
12241 LogicSVEAddressVector addr(imm, &ReadVRegister(instr->GetRn()), kFormatVnD);
12247 ReadPRegister(instr->GetPgLow8()),
12248 instr->GetRt(),
12255 const Instruction* instr) {
12257 instr->Mask(SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsMask)) {
12272 const Instruction* instr) {
12273 switch (instr->Mask(
12288 const Instruction* instr) {
12289 switch (instr->Mask(SVE64BitGatherPrefetch_VectorPlusImmMask)) {
12303 const Instruction* instr) {
12305 switch (instr->Mask(SVEContiguousLoad_ScalarPlusScalarMask)) {
12333 int msize_in_bytes_log2 = instr->GetSVEMsizeFromDtype(is_signed);
12334 int esize_in_bytes_log2 = instr->GetSVEEsizeFromDtype(is_signed);
12337 uint64_t base = ReadXRegister(instr->GetRn(), Reg31IsStackPointer);
12338 uint64_t offset = ReadXRegister(instr->GetRm());
12343 ReadPRegister(instr->GetPgLow8()),
12344 instr->GetRt(),
12351 const Instruction* instr) {
12353 switch (instr->Mask(SVEContiguousNonFaultLoad_ScalarPlusImmMask)) {
12377 int msize_in_bytes_log2 = instr->GetSVEMsizeFromDtype(is_signed);
12378 int esize_in_bytes_log2 = instr->GetSVEEsizeFromDtype(is_signed);
12383 uint64_t base = ReadXRegister(instr->GetRn(), Reg31IsStackPointer);
12385 (instr->ExtractSignedBits(19, 16) * vl) / (1 << vl_divisor_log2);
12389 ReadPRegister(instr->GetPgLow8()),
12390 instr->GetRt(),
12397 const Instruction* instr) {
12398 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
12401 switch (instr->Mask(SVEContiguousNonTemporalLoad_ScalarPlusImmMask)) {
12420 uint64_t base = ReadXRegister(instr->GetRn(), Reg31IsStackPointer);
12421 uint64_t offset = instr->ExtractSignedBits(19, 16) * vl;
12426 instr->GetRt(),
12432 const Instruction* instr) {
12433 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
12436 switch (instr->Mask(SVEContiguousNonTemporalLoad_ScalarPlusScalarMask)) {
12454 uint64_t base = ReadXRegister(instr->GetRn(), Reg31IsStackPointer);
12455 uint64_t offset = ReadXRegister(instr->GetRm()) << msize_in_bytes_log2;
12460 instr->GetRt(),
12466 const Instruction* instr) {
12467 SimVRegister& zt = ReadVRegister(instr->GetRt());
12468 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
12480 uint64_t addr = ReadXRegister(instr->GetRn(), Reg31IsStackPointer);
12482 instr->ExtractSignedBits(19, 16) * dwords * kDRegSizeInBytes;
12483 int msz = instr->ExtractBits(24, 23);
12494 const Instruction* instr) {
12495 SimVRegister& zt = ReadVRegister(instr->GetRt());
12496 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
12508 uint64_t addr = ReadXRegister(instr->GetRn(), Reg31IsStackPointer);
12509 uint64_t offset = ReadXRegister(instr->GetRm());
12510 int msz = instr->ExtractBits(24, 23);
12521 const Instruction* instr) {
12522 switch (instr->Mask(SVELoadMultipleStructures_ScalarPlusImmMask)) {
12536 int msz = instr->ExtractBits(24, 23);
12537 int reg_count = instr->ExtractBits(22, 21) + 1;
12538 uint64_t offset = instr->ExtractSignedBits(19, 16) * vl * reg_count;
12540 ReadXRegister(instr->GetRn(), Reg31IsStackPointer) + offset);
12544 ReadPRegister(instr->GetPgLow8()),
12545 instr->GetRt(),
12556 const Instruction* instr) {
12557 switch (instr->Mask(SVELoadMultipleStructures_ScalarPlusScalarMask)) {
12570 int msz = instr->ExtractBits(24, 23);
12571 uint64_t offset = ReadXRegister(instr->GetRm()) * (1 << msz);
12574 ReadXRegister(instr->GetRn(), Reg31IsStackPointer) + offset);
12576 addr.SetRegCount(instr->ExtractBits(22, 21) + 1);
12578 ReadPRegister(instr->GetPgLow8()),
12579 instr->GetRt(),
12591 const Instruction* instr) {
12592 switch (instr->Mask(SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsMask)) {
12595 unsigned msize_in_bytes_log2 = instr->GetSVEMsizeFromDtype(false);
12597 int scale = instr->ExtractBit(21) * msize_in_bytes_log2;
12598 uint64_t base = ReadXRegister(instr->GetRn(), Reg31IsStackPointer);
12600 (instr->ExtractBit(14) == 1) ? SVE_SXTW : SVE_UXTW;
12602 &ReadVRegister(instr->GetRm()),
12608 ReadPRegister(instr->GetPgLow8()),
12609 instr->GetRt(),
12620 const Instruction* instr) {
12622 instr->Mask(SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsMask)) {
12626 unsigned msize_in_bytes_log2 = instr->GetSVEMsizeFromDtype(false);
12628 uint64_t base = ReadXRegister(instr->GetRn(), Reg31IsStackPointer);
12630 (instr->ExtractBit(14) == 1) ? SVE_SXTW : SVE_UXTW;
12632 &ReadVRegister(instr->GetRm()),
12637 ReadPRegister(instr->GetPgLow8()),
12638 instr->GetRt(),
12649 const Instruction* instr) {
12651 switch (instr->Mask(SVE32BitScatterStore_VectorPlusImmMask)) {
12665 uint64_t imm = instr->ExtractBits(20, 16) << msz;
12666 LogicSVEAddressVector addr(imm, &ReadVRegister(instr->GetRn()), kFormatVnS);
12669 ReadPRegister(instr->GetPgLow8()),
12670 instr->GetRt(),
12675 const Instruction* instr) {
12676 switch (instr->Mask(SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsMask)) {
12680 unsigned msize_in_bytes_log2 = instr->GetSVEMsizeFromDtype(false);
12682 int scale = instr->ExtractBit(21) * msize_in_bytes_log2;
12683 uint64_t base = ReadXRegister(instr->GetRn(), Reg31IsStackPointer);
12685 &ReadVRegister(instr->GetRm()),
12691 ReadPRegister(instr->GetPgLow8()),
12692 instr->GetRt(),
12703 const Instruction* instr) {
12705 instr->Mask(SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsMask)) {
12710 unsigned msize_in_bytes_log2 = instr->GetSVEMsizeFromDtype(false);
12712 uint64_t base = ReadXRegister(instr->GetRn(), Reg31IsStackPointer);
12714 &ReadVRegister(instr->GetRm()),
12719 ReadPRegister(instr->GetPgLow8()),
12720 instr->GetRt(),
12731 const Instruction* instr) {
12732 switch (instr->Mask(
12737 unsigned msize_in_bytes_log2 = instr->GetSVEMsizeFromDtype(false);
12739 int scale = instr->ExtractBit(21) * msize_in_bytes_log2;
12740 uint64_t base = ReadXRegister(instr->GetRn(), Reg31IsStackPointer);
12742 (instr->ExtractBit(14) == 1) ? SVE_SXTW : SVE_UXTW;
12744 &ReadVRegister(instr->GetRm()),
12750 ReadPRegister(instr->GetPgLow8()),
12751 instr->GetRt(),
12763 const Instruction* instr) {
12764 switch (instr->Mask(
12770 unsigned msize_in_bytes_log2 = instr->GetSVEMsizeFromDtype(false);
12772 uint64_t base = ReadXRegister(instr->GetRn(), Reg31IsStackPointer);
12774 (instr->ExtractBit(14) == 1) ? SVE_SXTW : SVE_UXTW;
12776 &ReadVRegister(instr->GetRm()),
12781 ReadPRegister(instr->GetPgLow8()),
12782 instr->GetRt(),
12793 const Instruction* instr) {
12795 switch (instr->Mask(SVE64BitScatterStore_VectorPlusImmMask)) {
12812 uint64_t imm = instr->ExtractBits(20, 16) << msz;
12813 LogicSVEAddressVector addr(imm, &ReadVRegister(instr->GetRn()), kFormatVnD);
12816 ReadPRegister(instr->GetPgLow8()),
12817 instr->GetRt(),
12822 const Instruction* instr) {
12823 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
12826 switch (instr->Mask(SVEContiguousNonTemporalStore_ScalarPlusImmMask)) {
12845 uint64_t base = ReadXRegister(instr->GetRn(), Reg31IsStackPointer);
12846 uint64_t offset = instr->ExtractSignedBits(19, 16) * vl;
12849 SVEStructuredStoreHelper(vform, pg, instr->GetRt(), addr);
12853 const Instruction* instr) {
12854 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
12857 switch (instr->Mask(SVEContiguousNonTemporalStore_ScalarPlusScalarMask)) {
12875 uint64_t base = ReadXRegister(instr->GetRn(), Reg31IsStackPointer);
12876 uint64_t offset = ReadXRegister(instr->GetRm()) << msize_in_bytes_log2;
12879 SVEStructuredStoreHelper(vform, pg, instr->GetRt(), addr);
12883 const Instruction* instr) {
12884 switch (instr->Mask(SVEContiguousStore_ScalarPlusImmMask)) {
12890 int msize_in_bytes_log2 = instr->GetSVEMsizeFromDtype(false);
12891 int esize_in_bytes_log2 = instr->GetSVEEsizeFromDtype(false);
12894 uint64_t base = ReadXRegister(instr->GetRn(), Reg31IsStackPointer);
12896 (instr->ExtractSignedBits(19, 16) * vl) / (1 << vl_divisor_log2);
12902 ReadPRegister(instr->GetPgLow8()),
12903 instr->GetRt(),
12914 const Instruction* instr) {
12915 switch (instr->Mask(SVEContiguousStore_ScalarPlusScalarMask)) {
12920 uint64_t base = ReadXRegister(instr->GetRn(), Reg31IsStackPointer);
12921 uint64_t offset = ReadXRegister(instr->GetRm());
12922 offset <<= instr->ExtractBits(24, 23);
12924 SVEFormatFromLaneSizeInBytesLog2(instr->ExtractBits(22, 21));
12926 addr.SetMsizeInBytesLog2(instr->ExtractBits(24, 23));
12928 ReadPRegister(instr->GetPgLow8()),
12929 instr->GetRt(),
12940 const Instruction* instr) {
12941 VectorFormat vform = instr->GetSVEVectorFormat();
12942 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
12945 switch (instr->Mask(SVECopySIMDFPScalarRegisterToVector_PredicatedMask)) {
12947 dup_element(vform, z_result, ReadVRegister(instr->GetRn()), 0);
12948 mov_merging(vform, ReadVRegister(instr->GetRd()), pg, z_result);
12957 const Instruction* instr) {
12958 switch (instr->Mask(SVEStoreMultipleStructures_ScalarPlusImmMask)) {
12972 int msz = instr->ExtractBits(24, 23);
12973 int reg_count = instr->ExtractBits(22, 21) + 1;
12974 uint64_t offset = instr->ExtractSignedBits(19, 16) * vl * reg_count;
12976 ReadXRegister(instr->GetRn(), Reg31IsStackPointer) + offset);
12980 ReadPRegister(instr->GetPgLow8()),
12981 instr->GetRt(),
12992 const Instruction* instr) {
12993 switch (instr->Mask(SVEStoreMultipleStructures_ScalarPlusScalarMask)) {
13006 int msz = instr->ExtractBits(24, 23);
13007 uint64_t offset = ReadXRegister(instr->GetRm()) * (1 << msz);
13010 ReadXRegister(instr->GetRn(), Reg31IsStackPointer) + offset);
13012 addr.SetRegCount(instr->ExtractBits(22, 21) + 1);
13014 ReadPRegister(instr->GetPgLow8()),
13015 instr->GetRt(),
13025 void Simulator::VisitSVEStorePredicateRegister(const Instruction* instr) {
13026 switch (instr->Mask(SVEStorePredicateRegisterMask)) {
13028 SimPRegister& pt = ReadPRegister(instr->GetPt());
13030 int imm9 = (instr->ExtractBits(21, 16) << 3) | instr->ExtractBits(12, 10);
13032 uint64_t base = ReadXRegister(instr->GetRn(), Reg31IsStackPointer);
13037 LogPWrite(instr->GetPt(), address);
13046 void Simulator::VisitSVEStoreVectorRegister(const Instruction* instr) {
13047 switch (instr->Mask(SVEStoreVectorRegisterMask)) {
13049 SimVRegister& zt = ReadVRegister(instr->GetRt());
13051 int imm9 = (instr->ExtractBits(21, 16) << 3) | instr->ExtractBits(12, 10);
13053 uint64_t base = ReadXRegister(instr->GetRn(), Reg31IsStackPointer);
13058 LogZWrite(instr->GetRt(), address);
13067 void Simulator::VisitSVEMulIndex(const Instruction* instr) {
13068 VectorFormat vform = instr->GetSVEVectorFormat();
13069 SimVRegister& zda = ReadVRegister(instr->GetRd());
13070 SimVRegister& zn = ReadVRegister(instr->GetRn());
13071 std::pair<int, int> zm_and_index = instr->GetSVEMulZmAndIndex();
13099 void Simulator::SimulateMatrixMul(const Instruction* instr) {
13101 SimVRegister& dn = ReadVRegister(instr->GetRd());
13102 SimVRegister& n = ReadVRegister(instr->GetRn());
13103 SimVRegister& m = ReadVRegister(instr->GetRm());
13133 void Simulator::SimulateSVEFPMatrixMul(const Instruction* instr) {
13134 VectorFormat vform = instr->GetSVEVectorFormat();
13135 SimVRegister& zdn = ReadVRegister(instr->GetRd());
13136 SimVRegister& zn = ReadVRegister(instr->GetRn());
13137 SimVRegister& zm = ReadVRegister(instr->GetRm());
13150 void Simulator::VisitSVEPartitionBreakCondition(const Instruction* instr) {
13151 SimPRegister& pd = ReadPRegister(instr->GetPd());
13152 SimPRegister& pg = ReadPRegister(instr->ExtractBits(13, 10));
13153 SimPRegister& pn = ReadPRegister(instr->GetPn());
13156 switch (instr->Mask(SVEPartitionBreakConditionMask)) {
13170 if (instr->ExtractBit(4) == 1) {
13177 if (instr->ExtractBit(22) == 1) {
13183 const Instruction* instr) {
13184 SimPRegister& pdm = ReadPRegister(instr->GetPd());
13185 SimPRegister& pg = ReadPRegister(instr->ExtractBits(13, 10));
13186 SimPRegister& pn = ReadPRegister(instr->GetPn());
13188 switch (instr->Mask(SVEPropagateBreakToNextPartitionMask)) {
13199 if (instr->ExtractBit(22) == 1) {
13205 void Simulator::VisitSVEUnpackPredicateElements(const Instruction* instr) {
13206 SimPRegister& pd = ReadPRegister(instr->GetPd());
13207 SimPRegister& pn = ReadPRegister(instr->GetPn());
13213 switch (instr->Mask(SVEUnpackPredicateElementsMask)) {
13227 void Simulator::VisitSVEPermutePredicateElements(const Instruction* instr) {
13228 VectorFormat vform = instr->GetSVEVectorFormat();
13229 SimPRegister& pd = ReadPRegister(instr->GetPd());
13230 SimPRegister& pn = ReadPRegister(instr->GetPn());
13231 SimPRegister& pm = ReadPRegister(instr->GetPm());
13236 switch (instr->Mask(SVEPermutePredicateElementsMask)) {
13262 void Simulator::VisitSVEReversePredicateElements(const Instruction* instr) {
13263 switch (instr->Mask(SVEReversePredicateElementsMask)) {
13265 VectorFormat vform = instr->GetSVEVectorFormat();
13266 SimPRegister& pn = ReadPRegister(instr->GetPn());
13267 SimPRegister& pd = ReadPRegister(instr->GetPd());
13279 void Simulator::VisitSVEPermuteVectorExtract(const Instruction* instr) {
13280 SimVRegister& zdn = ReadVRegister(instr->GetRd());
13282 SimVRegister& zm = ReadVRegister(instr->GetRn());
13284 int index = instr->GetSVEExtractImmediate();
13288 switch (instr->Mask(SVEPermuteVectorExtractMask)) {
13298 void Simulator::VisitSVEPermuteVectorInterleaving(const Instruction* instr) {
13299 VectorFormat vform = instr->GetSVEVectorFormat();
13300 SimVRegister& zd = ReadVRegister(instr->GetRd());
13301 SimVRegister& zn = ReadVRegister(instr->GetRn());
13302 SimVRegister& zm = ReadVRegister(instr->GetRm());
13304 switch (instr->Mask(SVEPermuteVectorInterleavingMask)) {
13330 const Instruction* instr) {
13331 VectorFormat vform = instr->GetSVEVectorFormat();
13332 SimVRegister& zdn = ReadVRegister(instr->GetRd());
13333 SimVRegister& zm = ReadVRegister(instr->GetRn());
13334 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
13337 switch (instr->Mask(SVEConditionallyBroadcastElementToVectorMask)) {
13362 const Instruction* instr) {
13363 VectorFormat vform = instr->GetSVEVectorFormat();
13364 SimVRegister& vdn = ReadVRegister(instr->GetRd());
13365 SimVRegister& zm = ReadVRegister(instr->GetRn());
13366 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
13369 switch (instr->Mask(SVEConditionallyExtractElementToSIMDFPScalarMask)) {
13391 const Instruction* instr) {
13392 VectorFormat vform = instr->GetSVEVectorFormat();
13393 SimVRegister& zm = ReadVRegister(instr->GetRn());
13394 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
13397 switch (instr->Mask(SVEConditionallyExtractElementToGeneralRegisterMask)) {
13411 uint64_t masked_src = ReadXRegister(instr->GetRd()) &
13413 WriteXRegister(instr->GetRd(), value.first ? value.second : masked_src);
13418 const Instruction* instr) {
13419 VectorFormat vform = instr->GetSVEVectorFormat();
13420 SimVRegister& vdn = ReadVRegister(instr->GetRd());
13421 SimVRegister& zm = ReadVRegister(instr->GetRn());
13422 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
13425 switch (instr->Mask(SVEExtractElementToSIMDFPScalarRegisterMask)) {
13446 const Instruction* instr) {
13447 VectorFormat vform = instr->GetSVEVectorFormat();
13448 SimVRegister& zm = ReadVRegister(instr->GetRn());
13449 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
13452 switch (instr->Mask(SVEExtractElementToGeneralRegisterMask)) {
13466 WriteXRegister(instr->GetRd(), value.second);
13470 void Simulator::VisitSVECompressActiveElements(const Instruction* instr) {
13471 VectorFormat vform = instr->GetSVEVectorFormat();
13472 SimVRegister& zd = ReadVRegister(instr->GetRd());
13473 SimVRegister& zn = ReadVRegister(instr->GetRn());
13474 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
13476 switch (instr->Mask(SVECompressActiveElementsMask)) {
13487 const Instruction* instr) {
13488 VectorFormat vform = instr->GetSVEVectorFormat();
13489 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
13492 switch (instr->Mask(SVECopyGeneralRegisterToVector_PredicatedMask)) {
13496 ReadXRegister(instr->GetRn(), Reg31IsStackPointer));
13497 mov_merging(vform, ReadVRegister(instr->GetRd()), pg, z_result);
13505 void Simulator::VisitSVECopyIntImm_Predicated(const Instruction* instr) {
13506 VectorFormat vform = instr->GetSVEVectorFormat();
13507 SimPRegister& pg = ReadPRegister(instr->ExtractBits(19, 16));
13508 SimVRegister& zd = ReadVRegister(instr->GetRd());
13511 switch (instr->Mask(SVECopyIntImm_PredicatedMask)) {
13514 uint64_t imm8 = instr->GetImmSVEIntWideSigned();
13515 dup_immediate(vform, result, imm8 << (instr->ExtractBit(13) * 8));
13523 if (instr->ExtractBit(14) != 0) {
13530 void Simulator::VisitSVEReverseWithinElements(const Instruction* instr) {
13531 SimVRegister& zd = ReadVRegister(instr->GetRd());
13532 SimVRegister& zn = ReadVRegister(instr->GetRn());
13533 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
13540 VectorFormat chunk_form = instr->GetSVEVectorFormat();
13543 switch (instr->Mask(SVEReverseWithinElementsMask)) {
13565 if (instr->Mask(SVEReverseWithinElementsMask) != RBIT_z_p_z) {
13585 void Simulator::VisitSVEVectorSplice(const Instruction* instr) {
13586 VectorFormat vform = instr->GetSVEVectorFormat();
13587 SimVRegister& zd = ReadVRegister(instr->GetRd());
13588 SimVRegister& zn = ReadVRegister(instr->GetRn());
13589 SimVRegister& zn2 = ReadVRegister((instr->GetRn() + 1) % kNumberOfZRegisters);
13590 SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
13605 void Simulator::VisitSVEBroadcastGeneralRegister(const Instruction* instr) {
13606 SimVRegister& zd = ReadVRegister(instr->GetRd());
13607 switch (instr->Mask(SVEBroadcastGeneralRegisterMask)) {
13609 dup_immediate(instr->GetSVEVectorFormat(),
13611 ReadXRegister(instr->GetRn(), Reg31IsStackPointer));
13619 void Simulator::VisitSVEInsertSIMDFPScalarRegister(const Instruction* instr) {
13620 SimVRegister& zd = ReadVRegister(instr->GetRd());
13621 VectorFormat vform = instr->GetSVEVectorFormat();
13622 switch (instr->Mask(SVEInsertSIMDFPScalarRegisterMask)) {
13624 insr(vform, zd, ReadDRegisterBits(instr->GetRn()));
13632 void Simulator::VisitSVEInsertGeneralRegister(const Instruction* instr) {
13633 SimVRegister& zd = ReadVRegister(instr->GetRd());
13634 VectorFormat vform = instr->GetSVEVectorFormat();
13635 switch (instr->Mask(SVEInsertGeneralRegisterMask)) {
13637 insr(vform, zd, ReadXRegister(instr->GetRn()));
13645 void Simulator::VisitSVEBroadcastIndexElement(const Instruction* instr) {
13646 SimVRegister& zd = ReadVRegister(instr->GetRd());
13647 switch (instr->Mask(SVEBroadcastIndexElementMask)) {
13650 instr->GetSVEPermuteIndexAndLaneSizeLog2();
13659 dup_element(vform, zd, ReadVRegister(instr->GetRn()), index);
13669 void Simulator::VisitSVEReverseVectorElements(const Instruction* instr) {
13670 SimVRegister& zd = ReadVRegister(instr->GetRd());
13671 VectorFormat vform = instr->GetSVEVectorFormat();
13672 switch (instr->Mask(SVEReverseVectorElementsMask)) {
13674 rev(vform, zd, ReadVRegister(instr->GetRn()));
13682 void Simulator::VisitSVEUnpackVectorElements(const Instruction* instr) {
13683 SimVRegister& zd = ReadVRegister(instr->GetRd());
13684 VectorFormat vform = instr->GetSVEVectorFormat();
13685 switch (instr->Mask(SVEUnpackVectorElementsMask)) {
13687 unpk(vform, zd, ReadVRegister(instr->GetRn()), kHiHalf, kSignedExtend);
13690 unpk(vform, zd, ReadVRegister(instr->GetRn()), kLoHalf, kSignedExtend);
13693 unpk(vform, zd, ReadVRegister(instr->GetRn()), kHiHalf, kUnsignedExtend);
13696 unpk(vform, zd, ReadVRegister(instr->GetRn()), kLoHalf, kUnsignedExtend);
13704 void Simulator::VisitSVETableLookup(const Instruction* instr) {
13705 VectorFormat vform = instr->GetSVEVectorFormat();
13706 SimVRegister& zd = ReadVRegister(instr->GetRd());
13707 SimVRegister& zn = ReadVRegister(instr->GetRn());
13708 SimVRegister& zn2 = ReadVRegister((instr->GetRn() + 1) % kNumberOfZRegisters);
13709 SimVRegister& zm = ReadVRegister(instr->GetRm());
13727 void Simulator::VisitSVEPredicateCount(const Instruction* instr) {
13728 VectorFormat vform = instr->GetSVEVectorFormat();
13729 SimPRegister& pg = ReadPRegister(instr->ExtractBits(13, 10));
13730 SimPRegister& pn = ReadPRegister(instr->GetPn());
13732 switch (instr->Mask(SVEPredicateCountMask)) {
13734 WriteXRegister(instr->GetRd(), CountActiveAndTrueLanes(vform, pg, pn));
13743 void Simulator::VisitSVEPredicateLogical(const Instruction* instr) {
13744 Instr op = instr->Mask(SVEPredicateLogicalMask);
13745 SimPRegister& pd = ReadPRegister(instr->GetPd());
13746 SimPRegister& pg = ReadPRegister(instr->ExtractBits(13, 10));
13747 SimPRegister& pn = ReadPRegister(instr->GetPn());
13748 SimPRegister& pm = ReadPRegister(instr->GetPm());
13779 if (instr->Mask(SVEPredicateLogicalSetFlagsBit) != 0) {
13784 void Simulator::VisitSVEPredicateFirstActive(const Instruction* instr) {
13785 LogicPRegister pg = ReadPRegister(instr->ExtractBits(8, 5));
13786 LogicPRegister pdn = ReadPRegister(instr->GetPd());
13787 switch (instr->Mask(SVEPredicateFirstActiveMask)) {
13799 void Simulator::VisitSVEPredicateInitialize(const Instruction* instr) {
13804 VIXL_ASSERT((instr->Mask(SVEPredicateInitializeMask) == PTRUE_p_s) ||
13805 (instr->Mask(SVEPredicateInitializeMask) == PTRUES_p_s));
13807 LogicPRegister pdn = ReadPRegister(instr->GetPd());
13808 VectorFormat vform = instr->GetSVEVectorFormat();
13810 ptrue(vform, pdn, instr->GetImmSVEPredicateConstraint());
13811 if (instr->ExtractBit(16)) PredTest(vform, pdn, pdn);
13814 void Simulator::VisitSVEPredicateNextActive(const Instruction* instr) {
13817 VIXL_ASSERT(instr->Mask(SVEPredicateNextActiveMask) == PNEXT_p_p_p);
13819 LogicPRegister pg = ReadPRegister(instr->ExtractBits(8, 5));
13820 LogicPRegister pdn = ReadPRegister(instr->GetPd());
13821 VectorFormat vform = instr->GetSVEVectorFormat();
13829 const Instruction* instr) {
13830 LogicPRegister pd(ReadPRegister(instr->GetPd()));
13831 LogicPRegister pg(ReadPRegister(instr->GetPn()));
13833 switch (instr->Mask(SVEPredicateReadFromFFR_PredicatedMask)) {
13854 const Instruction* instr) {
13855 LogicPRegister pd(ReadPRegister(instr->GetPd()));
13857 switch (instr->Mask(SVEPredicateReadFromFFR_UnpredicatedMask)) {
13867 void Simulator::VisitSVEPredicateTest(const Instruction* instr) {
13868 switch (instr->Mask(SVEPredicateTestMask)) {
13871 ReadPRegister(instr->ExtractBits(13, 10)),
13872 ReadPRegister(instr->GetPn()));
13880 void Simulator::VisitSVEPredicateZero(const Instruction* instr) {
13881 switch (instr->Mask(SVEPredicateZeroMask)) {
13883 pfalse(ReadPRegister(instr->GetPd()));
13891 void Simulator::VisitSVEPropagateBreak(const Instruction* instr) {
13892 SimPRegister& pd = ReadPRegister(instr->GetPd());
13893 SimPRegister& pg = ReadPRegister(instr->ExtractBits(13, 10));
13894 SimPRegister& pn = ReadPRegister(instr->GetPn());
13895 SimPRegister& pm = ReadPRegister(instr->GetPm());
13898 switch (instr->Mask(SVEPropagateBreakMask)) {
13921 void Simulator::VisitSVEStackFrameAdjustment(const Instruction* instr) {
13923 switch (instr->Mask(SVEStackFrameAdjustmentMask)) {
13933 uint64_t base = ReadXRegister(instr->GetRm(), Reg31IsStackPointer);
13934 WriteXRegister(instr->GetRd(),
13935 base + (length * instr->GetImmSVEVLScale()),
13940 void Simulator::VisitSVEStackFrameSize(const Instruction* instr) {
13941 int64_t scale = instr->GetImmSVEVLScale();
13943 switch (instr->Mask(SVEStackFrameSizeMask)) {
13945 WriteXRegister(instr->GetRd(), GetVectorLengthInBytes() * scale);
13952 void Simulator::VisitSVEVectorSelect(const Instruction* instr) {
13955 VIXL_ASSERT(instr->Mask(SVEVectorSelectMask) == SEL_z_p_zz);
13957 VectorFormat vform = instr->GetSVEVectorFormat();
13958 SimVRegister& zd = ReadVRegister(instr->GetRd());
13959 SimPRegister& pg = ReadPRegister(instr->ExtractBits(13, 10));
13960 SimVRegister& zn = ReadVRegister(instr->GetRn());
13961 SimVRegister& zm = ReadVRegister(instr->GetRm());
13966 void Simulator::VisitSVEFFRInitialise(const Instruction* instr) {
13967 switch (instr->Mask(SVEFFRInitialiseMask)) {
13979 void Simulator::VisitSVEFFRWriteFromPredicate(const Instruction* instr) {
13980 switch (instr->Mask(SVEFFRWriteFromPredicateMask)) {
13982 SimPRegister pn(ReadPRegister(instr->GetPn()));
14001 void Simulator::VisitSVEContiguousLoad_ScalarPlusImm(const Instruction* instr) {
14003 switch (instr->Mask(SVEContiguousLoad_ScalarPlusImmMask)) {
14032 int msize_in_bytes_log2 = instr->GetSVEMsizeFromDtype(is_signed);
14033 int esize_in_bytes_log2 = instr->GetSVEEsizeFromDtype(is_signed);
14036 uint64_t base = ReadXRegister(instr->GetRn(), Reg31IsStackPointer);
14038 (instr->ExtractSignedBits(19, 16) * vl) / (1 << vl_divisor_log2);
14043 ReadPRegister(instr->GetPgLow8()),
14044 instr->GetRt(),
14050 const Instruction* instr) {
14052 switch (instr->Mask(SVEContiguousLoad_ScalarPlusScalarMask)) {
14080 int msize_in_bytes_log2 = instr->GetSVEMsizeFromDtype(is_signed);
14081 int esize_in_bytes_log2 = instr->GetSVEEsizeFromDtype(is_signed);
14084 uint64_t base = ReadXRegister(instr->GetRn(), Reg31IsStackPointer);
14085 uint64_t offset = ReadXRegister(instr->GetRm());
14090 ReadPRegister(instr->GetPgLow8()),
14091 instr->GetRt(),
14096 void Simulator::DoUnreachable(const Instruction* instr) {
14097 VIXL_ASSERT((instr->Mask(ExceptionMask) == HLT) &&
14098 (instr->GetImmException() == kUnreachableOpcode));
14102 reinterpret_cast<const void*>(instr));
14106 void Simulator::Simulate_XdSP_XnSP_Xm(const Instruction* instr) {
14108 uint64_t rn = ReadXRegister(instr->GetRn(), Reg31IsStackPointer);
14109 uint64_t rm = ReadXRegister(instr->GetRm());
14112 WriteXRegister(instr->GetRd(), new_val, LogRegWrites, Reg31IsStackPointer);
14115 void Simulator::SimulateMTEAddSubTag(const Instruction* instr) {
14116 uint64_t rn = ReadXRegister(instr->GetRn(), Reg31IsStackPointer);
14118 uint64_t tag_offset = instr->ExtractBits(13, 10);
14122 uint64_t offset = instr->ExtractBits(21, 16) * kMTETagGranuleInBytes;
14133 WriteXRegister(instr->GetRd(), new_val, LogRegWrites, Reg31IsStackPointer);
14136 void Simulator::SimulateMTETagMaskInsert(const Instruction* instr) {
14138 uint64_t mask = ReadXRegister(instr->GetRm());
14140 ReadXRegister(instr->GetRn(), Reg31IsStackPointer));
14142 WriteXRegister(instr->GetRd(), mask | mask_bit);
14145 void Simulator::SimulateMTESubPointer(const Instruction* instr) {
14146 uint64_t rn = ReadXRegister(instr->GetRn(), Reg31IsStackPointer);
14147 uint64_t rm = ReadXRegister(instr->GetRm(), Reg31IsStackPointer);
14156 WriteXRegister(instr->GetRd(), new_val);
14159 void Simulator::SimulateMTEStoreTagPair(const Instruction* instr) {
14160 uint64_t rn = ReadXRegister(instr->GetRn(), Reg31IsStackPointer);
14161 uint64_t rt = ReadXRegister(instr->GetRt());
14162 uint64_t rt2 = ReadXRegister(instr->GetRt2());
14163 int offset = instr->GetImmLSPair() * static_cast<int>(kMTETagGranuleInBytes);
14180 uintptr_t address = AddressModeHelper(instr->GetRn(), offset, addr_mode);
14192 void Simulator::SimulateMTEStoreTag(const Instruction* instr) {
14193 uint64_t rt = ReadXRegister(instr->GetRt(), Reg31IsStackPointer);
14194 int offset = instr->GetImmLS() * static_cast<int>(kMTETagGranuleInBytes);
14248 uintptr_t address = AddressModeHelper(instr->GetRn(), offset, addr_mode);
14271 meta_data_.SetMTETag(address, tag, instr);
14273 meta_data_.SetMTETag(address + kMTETagGranuleInBytes, tag, instr);
14277 void Simulator::SimulateMTELoadTag(const Instruction* instr) {
14278 uint64_t rt = ReadXRegister(instr->GetRt());
14279 int offset = instr->GetImmLS() * static_cast<int>(kMTETagGranuleInBytes);
14288 uintptr_t address = AddressModeHelper(instr->GetRn(), offset, Offset);
14290 uint64_t tag = meta_data_.GetMTETag(address, instr);
14291 WriteXRegister(instr->GetRt(), GetAddressWithAllocationTag(rt, tag));
14294 void Simulator::SimulateCpyFP(const Instruction* instr) {
14295 MOPSPHelper<"cpy"_h>(instr);
14299 void Simulator::SimulateCpyP(const Instruction* instr) {
14300 MOPSPHelper<"cpy"_h>(instr);
14302 int d = instr->GetRd();
14303 int n = instr->GetRn();
14304 int s = instr->GetRs();
14328 void Simulator::SimulateCpyM(const Instruction* instr) {
14329 VIXL_ASSERT(instr->IsConsistentMOPSTriplet<"cpy"_h>());
14330 VIXL_ASSERT(instr->IsMOPSMainOf(GetLastExecutedInstruction(), "cpy"_h));
14332 int d = instr->GetRd();
14333 int n = instr->GetRn();
14334 int s = instr->GetRs();
14366 void Simulator::SimulateCpyE(const Instruction* instr) {
14367 USE(instr);
14368 VIXL_ASSERT(instr->IsConsistentMOPSTriplet<"cpy"_h>());
14369 VIXL_ASSERT(instr->IsMOPSEpilogueOf(GetLastExecutedInstruction(), "cpy"_h));
14374 void Simulator::SimulateSetP(const Instruction* instr) {
14375 MOPSPHelper<"set"_h>(instr);
14379 void Simulator::SimulateSetM(const Instruction* instr) {
14380 VIXL_ASSERT(instr->IsConsistentMOPSTriplet<"set"_h>());
14381 VIXL_ASSERT(instr->IsMOPSMainOf(GetLastExecutedInstruction(), "set"_h));
14383 uint64_t xd = ReadXRegister(instr->GetRd());
14384 uint64_t xn = ReadXRegister(instr->GetRn());
14385 uint64_t xs = ReadXRegister(instr->GetRs());
14388 LogWrite(instr->GetRs(), GetPrintRegPartial(kPrintRegLaneSizeB), xd);
14391 WriteXRegister(instr->GetRd(), xd);
14392 WriteXRegister(instr->GetRn(), 0);
14395 void Simulator::SimulateSetE(const Instruction* instr) {
14396 USE(instr);
14397 VIXL_ASSERT(instr->IsConsistentMOPSTriplet<"set"_h>());
14398 VIXL_ASSERT(instr->IsMOPSEpilogueOf(GetLastExecutedInstruction(), "set"_h));
14403 void Simulator::SimulateSetGP(const Instruction* instr) {
14404 MOPSPHelper<"setg"_h>(instr);
14406 uint64_t xd = ReadXRegister(instr->GetRd());
14407 uint64_t xn = ReadXRegister(instr->GetRn());
14420 void Simulator::SimulateSetGM(const Instruction* instr) {
14421 uint64_t xd = ReadXRegister(instr->GetRd());
14422 uint64_t xn = ReadXRegister(instr->GetRn());
14430 SimulateSetM(instr);
14433 void Simulator::DoTrace(const Instruction* instr) {
14434 VIXL_ASSERT((instr->Mask(ExceptionMask) == HLT) &&
14435 (instr->GetImmException() == kTraceOpcode));
14441 VIXL_STATIC_ASSERT(sizeof(*instr) == 1);
14442 memcpy(¶meters, instr + kTraceParamsOffset, sizeof(parameters));
14443 memcpy(&command, instr + kTraceCommandOffset, sizeof(command));
14456 WritePc(instr->GetInstructionAtOffset(kTraceLength));
14460 void Simulator::DoLog(const Instruction* instr) {
14461 VIXL_ASSERT((instr->Mask(ExceptionMask) == HLT) &&
14462 (instr->GetImmException() == kLogOpcode));
14467 VIXL_STATIC_ASSERT(sizeof(*instr) == 1);
14468 memcpy(¶meters, instr + kTraceParamsOffset, sizeof(parameters));
14477 WritePc(instr->GetInstructionAtOffset(kLogLength));
14481 void Simulator::DoPrintf(const Instruction* instr) {
14482 VIXL_ASSERT((instr->Mask(ExceptionMask) == HLT) &&
14483 (instr->GetImmException() == kPrintfOpcode));
14488 VIXL_STATIC_ASSERT(sizeof(*instr) == 1);
14489 memcpy(&arg_count, instr + kPrintfArgCountOffset, sizeof(arg_count));
14491 instr + kPrintfArgPatternListOffset,
14586 WritePc(instr->GetInstructionAtOffset(kPrintfLength));
14595 void Simulator::DoRuntimeCall(const Instruction* instr) {
14600 MemRead<uintptr_t>(instr + kRuntimeCallWrapperOffset);
14602 MemRead<uintptr_t>(instr + kRuntimeCallFunctionOffset);
14604 MemRead<uint32_t>(instr + kRuntimeCallTypeOffset));
14610 instr->GetInstructionAtOffset(kRuntimeCallLength));
14617 void Simulator::DoRuntimeCall(const Instruction* instr) {
14618 USE(instr);
14624 void Simulator::DoConfigureCPUFeatures(const Instruction* instr) {
14625 VIXL_ASSERT(instr->Mask(ExceptionMask) == HLT);
14639 ElementType feature = MemRead<ElementType>(instr + offset);
14645 switch (instr->GetImmException()) {
14660 WritePc(instr->GetInstructionAtOffset(AlignUp(offset, kInstructionSize)));
14664 void Simulator::DoSaveCPUFeatures(const Instruction* instr) {
14665 VIXL_ASSERT((instr->Mask(ExceptionMask) == HLT) &&
14666 (instr->GetImmException() == kSaveCPUFeaturesOpcode));
14667 USE(instr);
14673 void Simulator::DoRestoreCPUFeatures(const Instruction* instr) {
14674 VIXL_ASSERT((instr->Mask(ExceptionMask) == HLT) &&
14675 (instr->GetImmException() == kRestoreCPUFeaturesOpcode));
14676 USE(instr);