Lines Matching defs:zero
844 SimVRegister zero;
845 dup_immediate(kFormatVnB, zero, 0);
851 zero,
1342 // unprinted bits are zero.
1420 SimRegister zero;
1422 reg = &zero;
1430 // unprinted bits are all zero:
1481 // unprinted bits are all zero:
2067 // For sign- and zero-extension, make it clear that the resulting register
2412 SimVRegister result, zero, zd_b;
2414 zero.Clear();
2425 zip1(kFormatVnS, result, result, zero);
2729 SimVRegister zero;
2730 zero.Clear();
2731 zip1(vform, zd, result, zero);
2911 SimVRegister zero;
2912 zero.Clear();
2913 zip1(vform, zd, result, zero);
3251 SimVRegister zero, zn_b, zm_b, zn_t, zm_t;
3252 zero.Clear();
3255 uzp1(vform_half, zn_b, zn, zero);
3256 uzp1(vform_half, zm_b, zm, zero);
3257 uzp2(vform_half, zn_t, zn, zero);
3258 uzp2(vform_half, zm_t, zm, zero);
5445 // Division by zero can be trapped, but not on A-class processors.
5458 // Division by zero can be trapped, but not on A-class processors.
5469 // Division by zero can be trapped, but not on A-class processors.
5480 // Division by zero can be trapped, but not on A-class processors.
5658 // Extract and sign- or zero-extend 32-bit arguments for widening operations.
5730 // destination register value or in zero.
5759 // Merge sign extension, dest/zero and bitfield.
6023 // the sign- or zero-extension will not affect the conversion.
6083 // the sign- or zero-extension will not affect the conversion.
6824 // assume here to be zero. This allows execution of PACI[AB]SP when
8239 // In offset mode, bits 20 to 16 should be zero; these bits encode the
8402 // In offset mode, bits 20 to 16 should be zero; these bits encode the
9676 // Valid immediate is a non-zero bits
13210 SimVRegister zero;
13211 dup_immediate(kFormatVnB, zero, 0);
13215 zip2(kFormatVnB, temp, temp, zero);
13218 zip1(kFormatVnB, temp, temp, zero);
13656 // Out of bounds, set the destination register to zero.
14314 // as it should have zero in bits 63:55.