Lines Matching defs:result
835 SimVRegister ones, result;
837 mov_zeroing(kFormatVnB, result, pg, ones);
838 return result;
942 uint64_t result = (left + right + carry_in) & reg_mask;
945 uint8_t nzcv = CalcNFlag(result, reg_size) ? 8 : 0;
946 nzcv |= CalcZFlag(result) ? 4 : 0;
948 // Compute the C flag by comparing the result to the max unsigned integer.
954 // for the result.
957 uint64_t result_sign = result & sign_mask;
961 return std::make_pair(result, nzcv);
969 int carry_in = (sum_lo.second & 0x2) >> 1; // C flag in NZCV result.
1006 vixl_uint128_t result = Add128(a, b);
1007 result = Add128(result, c);
1008 result = Add128(result, d);
1009 return neg_result ? std::make_pair(-result.first - 1, -result.second)
1010 : result;
1023 // equal to the register lane size. Work out the shifted result based on
1059 int64_t result;
1060 memcpy(&result, &uvalue, sizeof(result));
1061 return result;
2392 SimVRegister result, zd_b;
2398 fcvt(kFormatVnH, kFormatVnS, result, pg, zn);
2399 pack_even_elements(kFormatVnH, result, result);
2400 zip1(kFormatVnH, result, zd_b, result);
2405 mov_merging(kFormatVnS, zd, pg, result);
2412 SimVRegister result, zero, zd_b;
2419 fcvt(kFormatVnS, kFormatVnD, result, pg, zn);
2420 pack_even_elements(kFormatVnS, result, result);
2421 zip1(kFormatVnS, result, zd_b, result);
2424 fcvtxn(kFormatVnS, result, zn);
2425 zip1(kFormatVnS, result, result, zero);
2428 fcvtxn(kFormatVnS, result, zn);
2429 zip1(kFormatVnS, result, zd_b, result);
2434 mov_merging(kFormatVnD, zd, pg, result);
2441 SimVRegister result;
2445 ext(kFormatVnB, result, zn, zn, kHRegSizeInBytes);
2446 fcvt(kFormatVnS, kFormatVnH, zd, pg, result);
2449 ext(kFormatVnB, result, zn, zn, kSRegSizeInBytes);
2450 fcvt(kFormatVnD, kFormatVnS, zd, pg, result);
2462 SimVRegister result;
2470 urecpe(vform, result, zn);
2473 ursqrte(vform, result, zn);
2478 mov_merging(vform, zd, pg, result);
2486 SimVRegister result;
2491 flogb(vform, result, zn);
2494 abs(vform, result, zn).SignedSaturate(vform);
2497 neg(vform, result, zn).SignedSaturate(vform);
2502 mov_merging(vform, zd, pg, result);
2511 SimVRegister result;
2515 histogram(vform, result, pg, zn, zm);
2516 mov_zeroing(vform, zd, pg, result);
2527 SimVRegister result;
2541 rotate_elements_right(vform, result, zm, 1);
2542 SVEBitwiseLogicalUnpredicatedHelper(EOR, kFormatVnD, result, zn, result);
2543 mov_alternating(vform, zd, result, 0);
2546 rotate_elements_right(vform, result, zm, -1);
2547 SVEBitwiseLogicalUnpredicatedHelper(EOR, kFormatVnD, result, zn, result);
2548 mov_alternating(vform, zd, result, 1);
2626 // result.
2641 SimVRegister result;
2657 sqxtn(vform, result, zn);
2663 sqxtun(vform, result, zn);
2669 uqxtn(vform, result, zn);
2675 rshrn(vform, result, zn, right_shift_dist);
2681 shrn(vform, result, zn, right_shift_dist);
2687 sqrshrn(vform, result, zn, right_shift_dist);
2693 sqrshrun(vform, result, zn, right_shift_dist);
2699 sqshrn(vform, result, zn, right_shift_dist);
2705 sqshrun(vform, result, zn, right_shift_dist);
2711 uqrshrn(vform, result, zn, right_shift_dist);
2717 uqshrn(vform, result, zn, right_shift_dist);
2726 zip1(vform, zd, zd, result);
2731 zip1(vform, zd, result, zero);
2867 SimVRegister result;
2881 addhn(vform, result, zn, zm);
2887 raddhn(vform, result, zn, zm);
2893 rsubhn(vform, result, zn, zm);
2899 subhn(vform, result, zn, zm);
2908 zip1(vform, zd, zd, result);
2913 zip1(vform, zd, result, zero);
3117 SimVRegister result;
3121 sadalp(vform, result, zn);
3124 uadalp(vform, result, zn);
3129 mov_merging(vform, zda, pg, result);
3379 SimVRegister result;
3383 add(vform, result, zdn, zm).Halve(vform);
3386 sub(vform, result, zdn, zm).Halve(vform);
3389 sub(vform, result, zm, zdn).Halve(vform);
3392 add(vform, result, zdn, zm).Halve(vform).Round(vform);
3395 add(vform, result, zdn, zm).Uhalve(vform);
3398 sub(vform, result, zdn, zm).Uhalve(vform);
3401 sub(vform, result, zm, zdn).Uhalve(vform);
3404 add(vform, result, zdn, zm).Uhalve(vform).Round(vform);
3410 mov_merging(vform, zdn, pg, result);
3418 SimVRegister result;
3422 add(vform, result, zdn, zm).SignedSaturate(vform);
3425 sub(vform, result, zdn, zm).SignedSaturate(vform);
3428 sub(vform, result, zm, zdn).SignedSaturate(vform);
3431 suqadd(vform, result, zdn, zm);
3434 add(vform, result, zdn, zm).UnsignedSaturate(vform);
3437 sub(vform, result, zdn, zm).UnsignedSaturate(vform);
3440 sub(vform, result, zm, zdn).UnsignedSaturate(vform);
3443 usqadd(vform, result, zdn, zm);
3449 mov_merging(vform, zdn, pg, result);
3457 SimVRegister result;
3461 addp(vform, result, zdn, zm);
3464 smaxp(vform, result, zdn, zm);
3467 sminp(vform, result, zdn, zm);
3470 umaxp(vform, result, zdn, zm);
3473 uminp(vform, result, zdn, zm);
3479 mov_merging(vform, zdn, pg, result);
3487 SimVRegister result;
3491 faddp(vform, result, zdn, zm);
3494 fmaxnmp(vform, result, zdn, zm);
3497 fmaxp(vform, result, zdn, zm);
3500 fminnmp(vform, result, zdn, zm);
3503 fminp(vform, result, zdn, zm);
3508 mov_merging(vform, zdn, pg, result);
3521 SimVRegister result;
3525 sqshl(vform, result, zdn, left_shift_dist);
3528 sqshlu(vform, result, zdn, left_shift_dist);
3531 sshr(vform, result, zdn, right_shift_dist).Round(vform);
3534 uqshl(vform, result, zdn, left_shift_dist);
3537 ushr(vform, result, zdn, right_shift_dist).Round(vform);
3542 mov_merging(vform, zdn, pg, result);
4034 int64_t result = 0;
4044 result = op1 & op2;
4047 result = op1 | op2;
4050 result = op1 ^ op2;
4057 ReadNzcv().SetN(CalcNFlag(result, reg_size));
4058 ReadNzcv().SetZ(CalcZFlag(result));
4066 result,
4089 // If the condition passes, set the status flags to the result of comparing
4665 ssize_t result = write(placeholder_pipe_fd_[1],
4668 if (result > 0) {
4669 written += result;
4671 switch (result) {
4695 ssize_t result = read(placeholder_pipe_fd_[0],
4700 if (result > 0) {
4701 VIXL_ASSERT(static_cast<size_t>(result) <= written);
4702 written -= result;
4705 VIXL_CHECK(result == -EINTR);
4952 T result = 0;
4955 result = data + value;
4959 result = data & ~value;
4963 result = data ^ value;
4967 result = data | value;
4973 result = (data > value) ? data : value;
4977 result = (data > value) ? value : data;
4995 MemWrite<T>(address, result);
5435 int64_t result = 0;
5443 result = kWMinInt;
5446 result = 0;
5448 result = rn / rm;
5456 result = kXMinInt;
5459 result = 0;
5461 result = rn / rm;
5470 result = 0;
5472 result = rn / rm;
5481 result = 0;
5483 result = rn / rm;
5508 result = code & 0xffffffff00000000;
5514 result = Crc32Checksum(acc, val, CRC32_POLY);
5520 result = Crc32Checksum(acc, val, CRC32_POLY);
5526 result = Crc32Checksum(acc, val, CRC32_POLY);
5532 result = Crc32Checksum(acc, val, CRC32_POLY);
5539 result = Crc32Checksum(acc, val, CRC32C_POLY);
5545 result = Crc32Checksum(acc, val, CRC32C_POLY);
5551 result = Crc32Checksum(acc, val, CRC32C_POLY);
5557 result = Crc32Checksum(acc, val, CRC32C_POLY);
5570 result = ShiftOperand(reg_size,
5575 WriteRegister(reg_size, instr->GetRd(), result);
5657 uint64_t result = 0;
5668 result = ReadXRegister(instr->GetRa()) + (rn_u64 * rm_u64);
5672 result = ReadXRegister(instr->GetRa()) - (rn_u64 * rm_u64);
5675 result = ReadXRegister(instr->GetRa()) +
5679 result = ReadXRegister(instr->GetRa()) -
5683 result = ReadXRegister(instr->GetRa()) + (rn_u32 * rm_u32);
5686 result = ReadXRegister(instr->GetRa()) - (rn_u32 * rm_u32);
5689 result =
5694 result = internal::MultiplyHigh<64>(ReadXRegister(instr->GetRn()),
5700 WriteRegister(reg_size, instr->GetRd(), result);
5754 uint64_t result = RotateRight(src, R, reg_size);
5760 result = signbits | (result & mask) | (dst & ~mask);
5762 WriteRegister(reg_size, instr->GetRd(), result);
6645 double result = FPProcessNaNs(ReadDRegister(fn), ReadDRegister(fm));
6646 if (IsNaN(result)) {
6647 WriteDRegister(fd, result);
6651 float result = FPProcessNaNs(ReadSRegister(fn), ReadSRegister(fm));
6652 if (IsNaN(result)) {
6653 WriteSRegister(fd, result);
6703 uint64_t result =
6705 WriteXRegister(dst, result);
9742 SimVRegister result;
9772 asrd(vform, result, zdn, shift_dist);
9775 // Shift distance is computed differently for LSL. Convert the result.
9779 SVEBitwiseShiftHelper(shift_op, vform, result, zdn, scratch, false);
9781 mov_merging(vform, zdn, pg, result);
9790 SimVRegister result;
9797 sshr(vform, result, zm, zdn);
9800 sshr(vform, result, zdn, zm);
9803 sshl(vform, result, zm, zdn, shift_in_ls_byte);
9806 sshl(vform, result, zdn, zm, shift_in_ls_byte);
9809 ushr(vform, result, zm, zdn);
9812 ushr(vform, result, zdn, zm);
9815 sshl(vform, result, zdn, zm, shift_in_ls_byte)
9820 sshl(vform, result, zm, zdn, shift_in_ls_byte)
9825 sshl(vform, result, zdn, zm, shift_in_ls_byte).SignedSaturate(vform);
9828 sshl(vform, result, zm, zdn, shift_in_ls_byte).SignedSaturate(vform);
9831 sshl(vform, result, zdn, zm, shift_in_ls_byte).Round(vform);
9834 sshl(vform, result, zm, zdn, shift_in_ls_byte).Round(vform);
9837 ushl(vform, result, zdn, zm, shift_in_ls_byte)
9842 ushl(vform, result, zm, zdn, shift_in_ls_byte)
9847 ushl(vform, result, zdn, zm, shift_in_ls_byte).UnsignedSaturate(vform);
9850 ushl(vform, result, zm, zdn, shift_in_ls_byte).UnsignedSaturate(vform);
9853 ushl(vform, result, zdn, zm, shift_in_ls_byte).Round(vform);
9856 ushl(vform, result, zm, zdn, shift_in_ls_byte).Round(vform);
9862 mov_merging(vform, zdn, pg, result);
9872 SimVRegister result;
9890 result,
9894 mov_merging(vform, zdn, pg, result);
9932 // Shift distance is computed differently for LSL. Convert the result.
10195 SimVRegister result;
10198 fabd(vform, result, zdn, zm);
10201 fadd(vform, result, zdn, zm);
10204 fdiv(vform, result, zm, zdn);
10207 fdiv(vform, result, zdn, zm);
10210 fmaxnm(vform, result, zdn, zm);
10213 fmax(vform, result, zdn, zm);
10216 fminnm(vform, result, zdn, zm);
10219 fmin(vform, result, zdn, zm);
10222 fmulx(vform, result, zdn, zm);
10225 fmul(vform, result, zdn, zm);
10228 fscale(vform, result, zdn, zm);
10231 fsub(vform, result, zm, zdn);
10234 fsub(vform, result, zdn, zm);
10240 mov_merging(vform, zdn, pg, result);
10252 SimVRegister result;
10265 fadd(vform, result, zdn, add_sub_imm);
10268 fmaxnm(vform, result, zdn, min_max_imm);
10271 fmax(vform, result, zdn, min_max_imm);
10274 fminnm(vform, result, zdn, min_max_imm);
10277 fmin(vform, result, zdn, min_max_imm);
10280 fmul(vform, result, zdn, mul_imm);
10283 fsub(vform, result, add_sub_imm, zdn);
10286 fsub(vform, result, zdn, add_sub_imm);
10292 mov_merging(vform, zdn, pg, result);
10351 SimVRegister result;
10357 fabscmp(vform, result, zn, zm, ge);
10360 fabscmp(vform, result, zn, zm, gt);
10363 fcmp(vform, result, zn, zm, eq);
10366 fcmp(vform, result, zn, zm, ge);
10369 fcmp(vform, result, zn, zm, gt);
10372 fcmp(vform, result, zn, zm, ne);
10375 fcmp(vform, result, zn, zm, uo);
10382 ExtractFromSimVRegister(vform, pd, result);
10394 SimVRegister result;
10400 fcmp(vform, result, zn, zeros, eq);
10403 fcmp(vform, result, zn, zeros, ge);
10406 fcmp(vform, result, zn, zeros, gt);
10409 fcmp(vform, result, zn, zeros, le);
10412 fcmp(vform, result, zn, zeros, lt);
10415 fcmp(vform, result, zn, zeros, ne);
10422 ExtractFromSimVRegister(vform, pd, result);
10438 SimVRegister result;
10442 fcadd(vform, result, zdn, zm, rot);
10448 mov_merging(vform, zdn, pg, result);
10464 SimVRegister result;
10468 fcmla(vform, result, zn, zm, zda, rot);
10474 mov_merging(vform, zda, pg, result);
10588 SimVRegister result;
10600 fmla(vform, result, zd, zn, zm);
10604 fneg(vform, result, zd);
10605 fmls(vform, result, result, zn, zm);
10609 fmls(vform, result, zd, zn, zm);
10613 fneg(vform, result, zd);
10614 fmla(vform, result, result, zn, zm);
10628 fmla(vform, result, za, zd, zm);
10632 fneg(vform, result, za);
10633 fmls(vform, result, result, zd, zm);
10637 fmls(vform, result, za, zd, zm);
10641 fneg(vform, result, za);
10642 fmla(vform, result, result, zd, zm);
10650 mov_merging(vform, zd, pg, result);
10793 SimVRegister result;
10797 frecpx(vform, result, zn);
10800 fsqrt(vform, result, zn);
10806 mov_merging(vform, zd, pg, result);
10845 SimVRegister result;
10846 frint(vform, result, zn, fpcr_rounding, exact_exception, kFrintToInteger);
10847 mov_merging(vform, zd, pg, result);
11008 uint64_t result = (acc + delta) & mask;
11010 bool result_negative = ((result & sign_mask) != 0);
11018 // result, there was an overflow.
11024 result = mask & ~sign_mask; // E.g. 0x000000007fffffff
11028 result = ~mask | sign_mask; // E.g. 0xffffffff80000000
11032 if ((delta < 0) && (result > acc)) {
11034 result = 0;
11035 } else if ((delta > 0) && (result < acc)) {
11037 result = mask;
11043 if (result_negative && is_signed) result |= ~mask;
11045 return result;
11105 SimVRegister result;
11109 add(vform, result, zdn, zm);
11112 sub(vform, result, zm, zdn);
11115 sub(vform, result, zdn, zm);
11121 mov_merging(vform, zdn, pg, result);
11129 SimVRegister result;
11133 SVEBitwiseLogicalUnpredicatedHelper(AND, vform, result, zdn, zm);
11136 SVEBitwiseLogicalUnpredicatedHelper(BIC, vform, result, zdn, zm);
11139 SVEBitwiseLogicalUnpredicatedHelper(EOR, vform, result, zdn, zm);
11142 SVEBitwiseLogicalUnpredicatedHelper(ORR, vform, result, zdn, zm);
11148 mov_merging(vform, zdn, pg, result);
11156 SimVRegister result;
11160 mul(vform, result, zdn, zm);
11163 smulh(vform, result, zdn, zm);
11166 umulh(vform, result, zdn, zm);
11172 mov_merging(vform, zdn, pg, result);
11181 SimVRegister result;
11185 absdiff(vform, result, zdn, zm, true);
11188 smax(vform, result, zdn, zm);
11191 smin(vform, result, zdn, zm);
11194 absdiff(vform, result, zdn, zm, false);
11197 umax(vform, result, zdn, zm);
11200 umin(vform, result, zdn, zm);
11206 mov_merging(vform, zdn, pg, result);
11230 SimVRegister result;
11236 sdiv(vform, result, zm, zdn);
11239 sdiv(vform, result, zdn, zm);
11242 udiv(vform, result, zm, zdn);
11245 udiv(vform, result, zdn, zm);
11251 mov_merging(vform, zdn, pg, result);
11585 SimVRegister result;
11588 mla(vform, result, zd, ReadVRegister(instr->GetRn()), zm);
11591 mls(vform, result, zd, ReadVRegister(instr->GetRn()), zm);
11595 mla(vform, result, ReadVRegister(instr->GetRn()), zd, zm);
11599 mls(vform, result, ReadVRegister(instr->GetRn()), zd, zm);
11606 mov_merging(vform, zd, ReadPRegister(instr->GetPgLow8()), result);
11703 SimVRegister result;
11706 abs(vform, result, zn);
11709 cls(vform, result, zn);
11712 clz(vform, result, zn);
11715 cnot(vform, result, zn);
11718 cnt(vform, result, zn);
11721 fabs_(vform, result, zn);
11724 fneg(vform, result, zn);
11727 neg(vform, result, zn);
11730 not_(vform, result, zn);
11735 sxt(vform, result, zn, (kBitsPerByte << instr->ExtractBits(18, 17)));
11740 uxt(vform, result, zn, (kBitsPerByte << instr->ExtractBits(18, 17)));
11749 mov_merging(vform, zd, pg, result);
11762 SimVRegister result;
11768 dup_immediate(vform, result, value);
11775 mov_merging(vform, zd, pg, result);
13154 SimPRegister result;
13159 brka(result, pg, pn);
13163 brkb(result, pg, pn);
13171 mov_merging(pd, pg, result);
13173 mov_zeroing(pd, pg, result);
13510 SimVRegister result;
13515 dup_immediate(vform, result, imm8 << (instr->ExtractBit(13) * 8));
13524 mov_merging(vform, zd, pg, result);
13526 mov_zeroing(vform, zd, pg, result);
13534 SimVRegister result;
13545 rbit(chunk_form, result, zn);
13569 rev16(element_form, result, zn);
13572 rev32(element_form, result, zn);
13575 rev64(element_form, result, zn);
13582 mov_merging(chunk_form, zd, pg, result);
13749 SimPRegister result;
13766 result,
13778 mov_zeroing(pd, pg, result);
14540 // can emulate a single printf call by adding the result from each chunk. If
14547 int result = printf("%s", format);
14550 if (result >= 0) {
14572 result = part_result;
14576 result += part_result;
14582 // Printf returns its result in x0 (just like the C library's printf).
14583 WriteXRegister(0, result);