Lines Matching defs:mode
771 const char* Simulator::WRegNameForCode(unsigned code, Reg31Mode mode) {
774 ((code == kZeroRegCode) && (mode == Reg31IsStackPointer))) {
782 const char* Simulator::XRegNameForCode(unsigned code, Reg31Mode mode) {
785 ((code == kZeroRegCode) && (mode == Reg31IsStackPointer))) {
3931 // Add/sub/adds/subs don't allow ROR as a shift mode.
4251 // Pre-index mode.
6411 break; // Use FPCR rounding mode.
6416 break; // Use FPCR rounding mode.
6432 break; // Use FPCR rounding mode.
7087 break; // Use FPCR rounding mode.
7096 break; // Use FPCR rounding mode.
7103 break; // Use FPCR rounding mode.
8238 // Bit 23 determines whether this is an offset or post-index addressing mode.
8239 // In offset mode, bits 20 to 16 should be zero; these bits encode the
8240 // register or immediate in post-index mode.
8371 // The immediate post index addressing mode is indicated by rm = 31.
8401 // Bit 23 determines whether this is an offset or post-index addressing mode.
8402 // In offset mode, bits 20 to 16 should be zero; these bits encode the
8403 // register or immediate in post-index mode.
10824 break; // Use FPCR rounding mode.
14168 // Default is the offset mode.
14202 // Default is the offset mode.