Lines Matching defs:address
583 // Returning to address 0 exits the Simulator.
1753 uintptr_t address,
1795 uint64_t nibble = MemReadUint(lane_size_in_bytes, address + offset);
1803 address,
1811 uintptr_t address) {
1820 // "# {reg}: 0x{value} -> {address}"
1828 address,
1835 uintptr_t address) {
1839 // "# v{code}: 0x{value} -> {address}"
1847 address,
1855 uintptr_t address) {
1877 address + (i * reg_count));
1886 uintptr_t address) {
1892 // "# ╙───── {struct_value} -> {address}"
1897 PrintPartialAccess(lane_mask, 0, reg_count, lane_size_in_bytes, op, address);
1904 uintptr_t address) {
1910 // "# ╙─╨─╨─╨─ {struct_value} -> {address}"
1915 PrintPartialAccess(lane_mask, 0, reg_count, lane_size_in_bytes, op, address);
1918 void Simulator::PrintZAccess(int rt_code, const char* op, uintptr_t address) {
1923 // "# z{code}<127:0>: 0x{value} -> {address}"
1924 // "# z{code}<255:128>: 0x{value} -> {address + 16}"
1925 // "# z{code}<383:256>: 0x{value} -> {address + 32}"
1937 address,
1939 address += kQRegSizeInBytes;
2002 void Simulator::PrintPAccess(int code, const char* op, uintptr_t address) {
2007 // "# p{code}<15:0>: 0b{value} -> {address}"
2008 // "# p{code}<31:16>: 0b{value} -> {address + 2}"
2009 // "# p{code}<47:32>: 0b{value} -> {address + 4}"
2021 address,
2023 address += kQRegSizeInBytes;
2047 uintptr_t address) {
2052 PrintAccess(rt_code, format, "<-", address);
2058 uintptr_t address) {
2062 PrintRead(rt_code, format, address);
2079 address,
2085 uintptr_t address) {
2088 PrintVAccess(rt_code, format, "<-", address);
2093 uintptr_t address) {
2101 PrintAccess(rt_code, format, "->", address);
2106 uintptr_t address) {
2113 PrintVAccess(rt_code, format, "->", address);
3824 // Check for interceptions to the target address, if one is found, call it.
3829 // Instead of writing the address of the function to the PC, call the
3830 // function's interception directly. We change the address that will be
3832 // the address in the LR. Note: the interception may modify the LR so
4132 uint64_t address = ReadRegister<uint64_t>(rn, Reg31IsStackPointer);
4134 address += offset;
4136 // Verify that the address is available to the host.
4137 VIXL_ASSERT(address == static_cast<uintptr_t>(address));
4139 // Check the alignment of `address`.
4140 if (AlignDown(address, 16) != AlignDown(address + element_size - 1, 16)) {
4144 WriteRegister<T1>(rt, static_cast<T1>(MemRead<T2>(address)));
4149 LogRead(rt, GetPrintRegisterFormat(element_size), address);
4159 uint64_t address = ReadRegister<uint64_t>(rn, Reg31IsStackPointer);
4161 address += offset;
4163 // Verify that the address is available to the host.
4164 VIXL_ASSERT(address == static_cast<uintptr_t>(address));
4166 // Check the alignment of `address`.
4167 if (AlignDown(address, 16) != AlignDown(address + element_size - 1, 16)) {
4174 MemWrite<T>(address, ReadRegister<T>(rt));
4176 LogWrite(rt, GetPrintRegisterFormat(element_size), address);
4229 uint64_t address = ReadXRegister(addr_reg, Reg31IsStackPointer);
4232 address = AuthPAC(address, 0, key, kDataPointer);
4234 int error_lsb = GetTopPACBit(address, kInstructionPointer) - 2;
4235 if (((address >> error_lsb) & 0x3) != 0x0) {
4240 if ((addr_reg == 31) && ((address % 16) != 0)) {
4242 // quadword aligned prior to the address calculation and write-backs.
4248 address += offset;
4253 WriteXRegister(addr_reg, address, LogRegWrites, Reg31IsStackPointer);
4256 uintptr_t addr_ptr = static_cast<uintptr_t>(address);
4258 // Verify that the calculated address is available to the host.
4259 VIXL_ASSERT(address == addr_ptr);
4282 uintptr_t address = AddressModeHelper(instr->GetRn(), offset, addrmode);
4289 WriteWRegister(srcdst, MemRead<uint8_t>(address), NoRegLog);
4293 WriteWRegister(srcdst, MemRead<uint16_t>(address), NoRegLog);
4297 WriteWRegister(srcdst, MemRead<uint32_t>(address), NoRegLog);
4301 WriteXRegister(srcdst, MemRead<uint64_t>(address), NoRegLog);
4305 WriteWRegister(srcdst, MemRead<int8_t>(address), NoRegLog);
4309 WriteWRegister(srcdst, MemRead<int16_t>(address), NoRegLog);
4313 WriteXRegister(srcdst, MemRead<int8_t>(address), NoRegLog);
4317 WriteXRegister(srcdst, MemRead<int16_t>(address), NoRegLog);
4321 WriteXRegister(srcdst, MemRead<int32_t>(address), NoRegLog);
4325 WriteBRegister(srcdst, MemRead<uint8_t>(address), NoRegLog);
4329 WriteHRegister(srcdst, MemRead<uint16_t>(address), NoRegLog);
4333 WriteSRegister(srcdst, MemRead<float>(address), NoRegLog);
4337 WriteDRegister(srcdst, MemRead<double>(address), NoRegLog);
4341 WriteQRegister(srcdst, MemRead<qreg_t>(address), NoRegLog);
4346 MemWrite<uint8_t>(address, ReadWRegister(srcdst));
4349 MemWrite<uint16_t>(address, ReadWRegister(srcdst));
4352 MemWrite<uint32_t>(address, ReadWRegister(srcdst));
4355 MemWrite<uint64_t>(address, ReadXRegister(srcdst));
4358 MemWrite<uint8_t>(address, ReadBRegister(srcdst));
4362 MemWrite<uint16_t>(address, ReadHRegisterBits(srcdst));
4366 MemWrite<float>(address, ReadSRegister(srcdst));
4370 MemWrite<double>(address, ReadDRegister(srcdst));
4374 MemWrite<qreg_t>(address, ReadQRegister(srcdst));
4386 // Print a detailed trace (including the memory address).
4396 LogVRead(srcdst, print_format, address);
4398 LogExtendingRead(srcdst, print_format, access_size, address);
4402 LogVWrite(srcdst, print_format, address);
4404 LogWrite(srcdst, GetPrintRegisterFormatForSize(result_size), address);
4440 uintptr_t address = AddressModeHelper(instr->GetRn(), offset, addrmode);
4441 uintptr_t address2 = address + element_size;
4455 WriteWRegister(rt, MemRead<uint32_t>(address), NoRegLog);
4460 WriteSRegister(rt, MemRead<float>(address), NoRegLog);
4466 WriteXRegister(rt, MemRead<uint64_t>(address), NoRegLog);
4471 WriteDRegister(rt, MemRead<double>(address), NoRegLog);
4477 WriteQRegister(rt, MemRead<qreg_t>(address), NoRegLog);
4483 WriteXRegister(rt, MemRead<int32_t>(address), NoRegLog);
4489 MemWrite<uint32_t>(address, ReadWRegister(rt));
4494 MemWrite<float>(address, ReadSRegister(rt));
4500 MemWrite<uint64_t>(address, ReadXRegister(rt));
4505 MemWrite<double>(address, ReadDRegister(rt));
4511 MemWrite<qreg_t>(address, ReadQRegister(rt));
4520 // Print a detailed trace (including the memory address).
4528 LogVRead(rt, print_format, address);
4531 LogExtendingRead(rt, print_format, element_size, address);
4534 LogRead(rt, print_format, address);
4539 LogVWrite(rt, print_format, address);
4542 LogWrite(rt, print_format, address);
4558 uint64_t address = ReadRegister<uint64_t>(rn, Reg31IsStackPointer);
4560 CheckIsValidUnalignedAtomicAccess(rn, address, element_size);
4572 T data = MemRead<T>(address);
4583 MemWrite<T>(address, newvalue);
4584 LogWrite(rt, GetPrintRegisterFormatForSize(element_size), address);
4587 LogRead(rs, GetPrintRegisterFormatForSize(element_size), address);
4601 uint64_t address = ReadRegister<uint64_t>(rn, Reg31IsStackPointer);
4603 CheckIsValidUnalignedAtomicAccess(rn, address, element_size * 2);
4605 uint64_t address2 = address + element_size;
4619 T data_low = MemRead<T>(address);
4635 MemWrite<T>(address, newvalue_low);
4643 LogRead(rs, format, address);
4647 LogWrite(rt, format, address);
4652 bool Simulator::CanReadMemory(uintptr_t address, size_t size) {
4666 reinterpret_cast<void*>(address + written),
4674 // The address range is not accessible.
4782 uint64_t address = ReadRegister<uint64_t>(rn, Reg31IsStackPointer);
4784 CheckIsValidUnalignedAtomicAccess(rn, address, access_size);
4788 local_monitor_.MarkExclusive(address, access_size);
4804 WriteWRegister(rt, MemRead<uint8_t>(address), NoRegLog);
4811 WriteWRegister(rt, MemRead<uint16_t>(address), NoRegLog);
4818 WriteWRegister(rt, MemRead<uint32_t>(address), NoRegLog);
4825 WriteXRegister(rt, MemRead<uint64_t>(address), NoRegLog);
4830 WriteWRegister(rt, MemRead<uint32_t>(address), NoRegLog);
4832 MemRead<uint32_t>(address + element_size),
4838 WriteXRegister(rt, MemRead<uint64_t>(address), NoRegLog);
4840 MemRead<uint64_t>(address + element_size),
4854 LogExtendingRead(rt, format, element_size, address);
4856 LogExtendingRead(rt2, format, element_size, address + element_size);
4867 do_store = local_monitor_.IsExclusive(address, access_size) &&
4868 global_monitor_.IsExclusive(address, access_size);
4884 MemWrite<uint8_t>(address, ReadWRegister(rt));
4890 MemWrite<uint16_t>(address, ReadWRegister(rt));
4896 MemWrite<uint32_t>(address, ReadWRegister(rt));
4902 MemWrite<uint64_t>(address, ReadXRegister(rt));
4906 MemWrite<uint32_t>(address, ReadWRegister(rt));
4907 MemWrite<uint32_t>(address + element_size, ReadWRegister(rt2));
4911 MemWrite<uint64_t>(address, ReadXRegister(rt));
4912 MemWrite<uint64_t>(address + element_size, ReadXRegister(rt2));
4920 LogWrite(rt, format, address);
4922 LogWrite(rt2, format, address + element_size);
4939 uint64_t address = ReadRegister<uint64_t>(rn, Reg31IsStackPointer);
4941 CheckIsValidUnalignedAtomicAccess(rn, address, element_size);
4945 T data = MemRead<T>(address);
4993 LogExtendingRead(rt, format, element_size, address);
4995 MemWrite<T>(address, result);
4997 LogWrite(rs, format, address);
5010 uint64_t address = ReadRegister<uint64_t>(rn, Reg31IsStackPointer);
5012 CheckIsValidUnalignedAtomicAccess(rn, address, element_size);
5014 T data = MemRead<T>(address);
5024 MemWrite<T>(address, ReadRegister<T>(rs));
5029 LogRead(rt, format, address);
5030 LogWrite(rs, format, address);
5039 uint64_t address = ReadRegister<uint64_t>(rn, Reg31IsStackPointer);
5041 CheckIsValidUnalignedAtomicAccess(rn, address, element_size);
5043 WriteRegister<T>(rt, MemRead<T>(address));
5048 LogRead(rt, GetPrintRegisterFormatForSize(element_size), address);
5155 uint64_t address = instr->GetLiteralAddress<uint64_t>();
5157 // Verify that the calculated address is available to the host.
5158 VIXL_ASSERT(address == static_cast<uintptr_t>(address));
5164 WriteWRegister(rt, MemRead<uint32_t>(address), NoRegLog);
5165 LogRead(rt, kPrintWReg, address);
5168 WriteXRegister(rt, MemRead<uint64_t>(address), NoRegLog);
5169 LogRead(rt, kPrintXReg, address);
5172 WriteSRegister(rt, MemRead<float>(address), NoRegLog);
5173 LogVRead(rt, kPrintSRegFP, address);
5176 WriteDRegister(rt, MemRead<double>(address), NoRegLog);
5177 LogVRead(rt, kPrintDRegFP, address);
5180 WriteQRegister(rt, MemRead<qreg_t>(address), NoRegLog);
5181 LogVRead(rt, kPrintReg1Q, address);
5184 WriteXRegister(rt, MemRead<int32_t>(address), NoRegLog);
5185 LogExtendingRead(rt, kPrintXReg, kWRegSizeInBytes, address);
5203 uint64_t address = ReadXRegister(addr_reg, Reg31IsStackPointer);
5205 if ((addr_reg == 31) && ((address % 16) != 0)) {
5207 // quadword aligned prior to the address calculation and write-backs.
5218 WriteXRegister(addr_reg, address + offset, log_mode, Reg31IsStackPointer);
5222 address += offset;
5225 // Verify that the calculated address is available to the host.
5226 VIXL_ASSERT(address == static_cast<uintptr_t>(address));
5228 return static_cast<uintptr_t>(address);
6680 // to the specified address. The read access does not require a tag match,
8364 uintptr_t address = addr_base + (s * RegisterSizeInBytesFromFormat(vf));
8365 PrintVStructAccess(reg[s], struct_parts, print_format, op, address);
12078 uint64_t address = base + multiplier * pl;
12080 pt.Insert(i, MemRead<uint8_t>(address + i));
12082 LogPRead(instr->GetPt(), address);
12099 uint64_t address = base + multiplier * vl;
12101 zt.Insert(i, MemRead<uint8_t>(address + i));
12103 LogZRead(instr->GetRt(), address);
13033 uint64_t address = base + multiplier * pl;
13035 MemWrite(address + i, pt.GetLane<uint8_t>(i));
13037 LogPWrite(instr->GetPt(), address);
13054 uint64_t address = base + multiplier * vl;
13056 MemWrite(address + i, zt.GetLane<uint8_t>(i));
13058 LogZWrite(instr->GetRt(), address);
14180 uintptr_t address = AddressModeHelper(instr->GetRn(), offset, addr_mode);
14181 if (!IsAligned(address, kMTETagGranuleInBytes)) {
14186 meta_data_.SetMTETag(address, tag);
14188 MemWrite<uint64_t>(address, rt);
14189 MemWrite<uint64_t>(address + kXRegSizeInBytes, rt2);
14248 uintptr_t address = AddressModeHelper(instr->GetRn(), offset, addr_mode);
14251 if (!IsAligned(reinterpret_cast<uintptr_t>(address),
14265 MemWrite<uint64_t>(address + fill_offset, 0);
14271 meta_data_.SetMTETag(address, tag, instr);
14273 meta_data_.SetMTETag(address + kMTETagGranuleInBytes, tag, instr);
14288 uintptr_t address = AddressModeHelper(instr->GetRn(), offset, Offset);
14289 address = AlignDown(address, kMTETagGranuleInBytes);
14290 uint64_t tag = meta_data_.GetMTETag(address, instr);
14613 // Read the return address from `lr` and write it into `pc`.
14683 void* address, size_t length, int prot, int flags, int fd, off_t offset) {
14691 mmap(address, length, prot, flags, fd, offset));
14694 // The returning address of `mmap` isn't tagged.
14704 int Simulator::Munmap(void* address, size_t length, int prot) {
14706 // Untag the address since `munmap` doesn't recognize the memory tagging
14708 address = AddressUntag(address);
14709 CleanGranuleTag(reinterpret_cast<char*>(address), length);
14712 return munmap(address, length);