Lines Matching defs:const
40 static const int kRegListSizeInBits = sizeof(RegList) * 8;
90 static const unsigned kUnknownSize = 0;
111 unsigned GetCode() const { return code_; }
113 RegisterBank GetBank() const { return bank_; }
117 bool HasSize() const { return size_ != kEncodedUnknownSize; }
118 bool HasLaneSize() const { return lane_size_ != kEncodedUnknownSize; }
120 RegList GetBit() const {
130 inline std::string GetArchitecturalName() const;
135 unsigned GetMaxCode() const { return GetMaxCodeFor(GetBank()); }
138 int GetSizeInBits() const { return DecodeSizeInBits(size_); }
139 int GetSizeInBytes() const { return DecodeSizeInBytes(size_); }
141 unsigned GetLaneSizeInBits() const { return DecodeSizeInBits(lane_size_); }
142 unsigned GetLaneSizeInBytes() const { return DecodeSizeInBytes(lane_size_); }
143 unsigned GetLaneSizeInBytesLog2() const {
148 int GetLanes() const {
162 bool Is8Bits() const { return size_ == kEncodedBRegSize; }
163 bool Is16Bits() const { return size_ == kEncodedHRegSize; }
164 bool Is32Bits() const { return size_ == kEncodedSRegSize; }
165 bool Is64Bits() const { return size_ == kEncodedDRegSize; }
166 bool Is128Bits() const { return size_ == kEncodedQRegSize; }
168 bool IsLaneSizeB() const { return lane_size_ == kEncodedBRegSize; }
169 bool IsLaneSizeH() const { return lane_size_ == kEncodedHRegSize; }
170 bool IsLaneSizeS() const { return lane_size_ == kEncodedSRegSize; }
171 bool IsLaneSizeD() const { return lane_size_ == kEncodedDRegSize; }
172 bool IsLaneSizeQ() const { return lane_size_ == kEncodedQRegSize; }
186 bool IsRegister() const { return GetType() == kRegister; }
187 bool IsVRegister() const { return GetType() == kVRegister; }
188 bool IsZRegister() const { return GetType() == kZRegister; }
189 bool IsPRegister() const { return GetType() == kPRegister; }
191 bool IsNone() const { return GetType() == kNoRegister; }
195 RegisterType GetType() const {
212 bool IsFPRegister() const { return Is1H() || Is1S() || Is1D(); }
216 bool IsValidRegister() const {
223 bool IsValidVRegister() const {
231 bool IsValidFPRegister() const {
235 bool IsValidZRegister() const {
243 bool IsValidPRegister() const {
253 bool IsValid() const {
258 bool IsValidOrNone() const { return IsNone() || IsValid(); }
260 bool IsVector() const { return HasLaneSize() && (size_ != lane_size_); }
261 bool IsScalar() const { return HasLaneSize() && (size_ == lane_size_); }
263 bool IsSameType(const CPURegister& other) const {
267 bool IsSameBank(const CPURegister& other) const {
274 bool IsSameSizeAndType(const CPURegister& other) const {
278 bool IsSameFormat(const CPURegister& other) const {
283 bool Aliases(const CPURegister& other) const {
287 bool Is(const CPURegister& other) const {
319 inline Register W() const;
320 inline Register X() const;
322 inline VRegister B() const;
323 inline VRegister H() const;
324 inline VRegister S() const;
325 inline VRegister D() const;
326 inline VRegister Q() const;
327 inline VRegister V() const;
329 inline ZRegister Z() const;
330 inline PRegister P() const;
334 bool IsZero() const { return IsRegister() && (code_ == kZeroRegCode); }
335 bool IsSP() const { return IsRegister() && (code_ == kSPRegInternalCode); }
336 bool IsW() const { return IsRegister() && Is32Bits(); }
337 bool IsX() const { return IsRegister() && Is64Bits(); }
347 bool IsB() const { return IsVRegister() && Is8Bits(); }
348 bool IsH() const { return IsVRegister() && Is16Bits(); }
349 bool IsS() const { return IsVRegister() && Is32Bits(); }
350 bool IsD() const { return IsVRegister() && Is64Bits(); }
351 bool IsQ() const { return IsVRegister() && Is128Bits(); }
356 bool Is1B() const { return IsB() && IsScalar(); }
357 bool Is1H() const { return IsH() && IsScalar(); }
358 bool Is1S() const { return IsS() && IsScalar(); }
359 bool Is1D() const { return IsD() && IsScalar(); }
360 bool Is1Q() const { return IsQ() && IsScalar(); }
363 bool Is8B() const { return IsD() && IsLaneSizeB(); }
364 bool Is16B() const { return IsQ() && IsLaneSizeB(); }
365 bool Is2H() const { return IsS() && IsLaneSizeH(); }
366 bool Is4H() const { return IsD() && IsLaneSizeH(); }
367 bool Is8H() const { return IsQ() && IsLaneSizeH(); }
368 bool Is2S() const { return IsD() && IsLaneSizeS(); }
369 bool Is4S() const { return IsQ() && IsLaneSizeS(); }
370 bool Is2D() const { return IsQ() && IsLaneSizeD(); }
376 bool Is1S4B() const { return Is1S(); }
380 bool IsUnqualified() const { return qualifiers_ == kNoQualifiers; }
381 bool IsMerging() const { return IsPRegister() && (qualifiers_ == kMerging); }
382 bool IsZeroing() const { return IsPRegister() && (qualifiers_ == kZeroing); }
386 int GetMaxSizeInBytes() const {
398 int GetMinSizeInBytes() const {
410 int GetMaxSizeInBits() const { return GetMaxSizeInBytes() * kBitsPerByte; }
411 int GetMinSizeInBits() const { return GetMinSizeInBytes() * kBitsPerByte; }
452 char GetLaneSizeSymbol() const {
577 bool IsValid() const { return IsValidRegister(); }
604 inline VRegister V8B() const;
605 inline VRegister V16B() const;
606 inline VRegister V2H() const;
607 inline VRegister V4H() const;
608 inline VRegister V8H() const;
609 inline VRegister V2S() const;
610 inline VRegister V4S() const;
611 inline VRegister V1D() const;
612 inline VRegister V2D() const;
616 inline VRegister S4B() const;
618 bool IsValid() const { return IsValidVRegister(); }
651 ZRegister VnB() const { return ZRegister(GetCode(), kBRegSize); }
652 ZRegister VnH() const { return ZRegister(GetCode(), kHRegSize); }
653 ZRegister VnS() const { return ZRegister(GetCode(), kSRegSize); }
654 ZRegister VnD() const { return ZRegister(GetCode(), kDRegSize); }
655 ZRegister VnQ() const { return ZRegister(GetCode(), kQRegSize); }
658 ZRegister WithLaneSize(T format) const {
662 ZRegister WithSameLaneSizeAs(const CPURegister& other) const {
667 bool IsValid() const { return IsValidZRegister(); }
679 bool IsValid() const {
684 PRegisterWithLaneSize VnB() const;
685 PRegisterWithLaneSize VnH() const;
686 PRegisterWithLaneSize VnS() const;
687 PRegisterWithLaneSize VnD() const;
690 PRegisterWithLaneSize WithLaneSize(T format) const;
692 PRegisterWithLaneSize WithSameLaneSizeAs(const CPURegister& other) const;
696 PRegisterZ Zeroing() const;
697 PRegisterM Merging() const;
731 bool IsValid() const {
740 unsigned GetLaneSizeInBits() const {
745 unsigned GetLaneSizeInBytes() const {
760 bool IsValid() const {
774 bool IsValid() const {
779 inline PRegisterWithLaneSize PRegister::VnB() const {
782 inline PRegisterWithLaneSize PRegister::VnH() const {
785 inline PRegisterWithLaneSize PRegister::VnS() const {
788 inline PRegisterWithLaneSize PRegister::VnD() const {
793 inline PRegisterWithLaneSize PRegister::WithLaneSize(T format) const {
798 const CPURegister& other) const {
803 inline PRegisterZ PRegister::Zeroing() const { return PRegisterZ(GetCode()); }
804 inline PRegisterM PRegister::Merging() const { return PRegisterM(GetCode()); }
825 PARENT As##PARENT() const { return *this; } \
827 VIXL_CONSTEXPR int GetSizeInBits() const { return SIZE; } \
829 bool IsValid() const { \
839 const Register NoReg;
840 const VRegister NoVReg;
841 const CPURegister NoCPUReg;
842 const ZRegister NoZReg;
847 const Register w##N = WRegister(N); \
848 const Register x##N = XRegister(N); \
849 const VRegister b##N = BRegister(N); \
850 const VRegister h##N = HRegister(N); \
851 const VRegister s##N = SRegister(N); \
852 const VRegister d##N = DRegister(N); \
853 const VRegister q##N = QRegister(N); \
854 const VRegister v##N(N); \
855 const ZRegister z##N(N);
859 #define VIXL_DEFINE_P_REGISTERS(N) const PRegister p##N(N);
876 RET_TYPE CPURegister::CTOR_TYPE() const { \
896 VRegister VRegister::V##LANES##LANE_TYPE() const { \
906 VRegister VRegister::S4B() const {
912 const Register wsp = WRegister(kSPRegInternalCode);
913 const Register sp = XRegister(kSPRegInternalCode);
916 const Register ip0 = x16;
917 const Register ip1 = x17;
918 const Register lr = x30;
919 const Register xzr = x31;
920 const Register wzr = w31;
922 std::string CPURegister::GetArchitecturalName() const {
973 bool AreAliased(const CPURegister& reg1,
974 const CPURegister& reg2,
975 const CPURegister& reg3 = NoReg,
976 const CPURegister& reg4 = NoReg,
977 const CPURegister& reg5 = NoReg,
978 const CPURegister& reg6 = NoReg,
979 const CPURegister& reg7 = NoReg,
980 const CPURegister& reg8 = NoReg) {
989 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8};
1029 bool AreSameSizeAndType(const CPURegister& reg1,
1030 const CPURegister& reg2,
1031 const CPURegister& reg3 = NoCPUReg,
1032 const CPURegister& reg4 = NoCPUReg,
1033 const CPURegister& reg5 = NoCPUReg,
1034 const CPURegister& reg6 = NoCPUReg,
1035 const CPURegister& reg7 = NoCPUReg,
1036 const CPURegister& reg8 = NoCPUReg) {
1053 bool AreEven(const CPURegister& reg1,
1054 const CPURegister& reg2,
1055 const CPURegister& reg3 = NoReg,
1056 const CPURegister& reg4 = NoReg,
1057 const CPURegister& reg5 = NoReg,
1058 const CPURegister& reg6 = NoReg,
1059 const CPURegister& reg7 = NoReg,
1060 const CPURegister& reg8 = NoReg) {
1078 bool AreConsecutive(const CPURegister& reg1,
1079 const CPURegister& reg2,
1080 const CPURegister& reg3 = NoCPUReg,
1081 const CPURegister& reg4 = NoCPUReg) {
1112 bool AreSameFormat(const CPURegister& reg1,
1113 const CPURegister& reg2,
1114 const CPURegister& reg3 = NoCPUReg,
1115 const CPURegister& reg4 = NoCPUReg) {
1130 bool AreSameLaneSize(const CPURegister& reg1,
1131 const CPURegister& reg2,
1132 const CPURegister& reg3 = NoCPUReg,
1133 const CPURegister& reg4 = NoCPUReg) {