Lines Matching defs:code
7 // * Redistributions of source code must retain the above copyright notice,
99 CPURegister(int code, int size_in_bits, RegisterType type)
100 : code_(code),
132 // Return the highest valid register code for this type, to allow generic
289 // For core (W, X) and FP/NEON registers, we only consider the code, size
304 // (`GetBank()`) is checked and the code (`GetCode()`) preserved, but all
316 // code like `cond ? reg.W() : reg.X()`, which would have indeterminate type.
533 CPURegister(int code,
538 : code_(code),
572 Register(int code, int size_in_bits)
573 : CPURegister(code, size_in_bits, kRegister) {
587 explicit VRegister(int code, int size_in_bits = kQRegSize, int lanes = 1)
588 : CPURegister(code,
595 VRegister(int code, VectorFormat format)
596 : CPURegister(code,
633 explicit ZRegister(int code, int lane_size_in_bits = kUnknownSize)
634 : CPURegister(code,
641 ZRegister(int code, VectorFormat format)
642 : CPURegister(code,
675 explicit PRegister(int code) : CPURegister(code, kUnknownSize, kPRegister) {
701 PRegister(int code, EncodedSize encoded_lane_size)
702 : CPURegister(code,
708 PRegister(int code, Qualifiers qualifiers)
709 : CPURegister(code,
721 PRegisterWithLaneSize(int code, int lane_size_in_bits)
722 : PRegister(code, EncodeSizeInBits(lane_size_in_bits)) {
726 PRegisterWithLaneSize(int code, VectorFormat format)
727 : PRegister(code, EncodeSizeInBits(LaneSizeInBitsFromFormat(format))) {
756 explicit PRegisterZ(int code) : PRegister(code, kZeroing) {
770 explicit PRegisterM(int code) : PRegister(code, kMerging) {
819 explicit NAME(int code) : PARENT(code, SIZE) {} \
911 // VIXL represents 'sp' with a unique code, to tell it apart from 'xzr'.