Lines Matching refs:VIXL_ASSERT

36   VIXL_ASSERT(imm.FitsInLane(zd));
41   VIXL_ASSERT((option == kAddImmediate) || (option == kSubImmediate));
52     VIXL_ASSERT(n_imm.IsPositiveOrZero());
73   VIXL_ASSERT(imm.FitsInLane(zd));
132   VIXL_ASSERT(allow_macro_instructions_);
141   VIXL_ASSERT(allow_macro_instructions_);
142   VIXL_ASSERT(imm.FitsInSignedLane(zd));
151   VIXL_ASSERT(allow_macro_instructions_);
152   VIXL_ASSERT(imm.FitsInSignedLane(zd));
161   VIXL_ASSERT(allow_macro_instructions_);
162   VIXL_ASSERT(imm.FitsInUnsignedLane(zd));
171   VIXL_ASSERT(allow_macro_instructions_);
172   VIXL_ASSERT(imm.FitsInUnsignedLane(zd));
181   VIXL_ASSERT(allow_macro_instructions_);
185   VIXL_ASSERT(multiplier <= (INT64_MAX / kZRegMaxSizeInBytes));
186   VIXL_ASSERT(multiplier >= (INT64_MIN / kZRegMaxSizeInBytes));
210     VIXL_ASSERT(xn.IsZero());  // Other cases were handled with `addpl`.
251   VIXL_ASSERT(allow_macro_instructions_);
252   VIXL_ASSERT(xd.IsX());
253   VIXL_ASSERT(xn.IsX());
256   VIXL_ASSERT(multiplier <= (INT64_MAX / kZRegMaxSizeInBytes));
257   VIXL_ASSERT(multiplier >= (INT64_MIN / kZRegMaxSizeInBytes));
307   VIXL_ASSERT(allow_macro_instructions_);
308   VIXL_ASSERT(!addr.IsScatterGather());
309   VIXL_ASSERT(xd.IsX());
312   VIXL_ASSERT(!addr.IsMulVl() || (vl_divisor_log2 >= 0));
315   VIXL_ASSERT(vl_divisor_log2 <= static_cast<int>(kZRegBitsPerPRegBitLog2));
331     VIXL_ASSERT(offset != 0);  // Handled by IsEquivalentToScalar.
336       VIXL_ASSERT((kZRegBitsPerPRegBit % vl_divisor) == 0);
340       VIXL_ASSERT(mod == NO_SVE_OFFSET_MODIFIER);
348     VIXL_ASSERT(!offset.IsZero());  // Handled by IsEquivalentToScalar.
353       VIXL_ASSERT(mod == NO_SVE_OFFSET_MODIFIER);
366   VIXL_ASSERT(allow_macro_instructions_);
367   VIXL_ASSERT(imm.FitsInLane(zd));
386   VIXL_ASSERT(imm.FitsInLane(zd));
430   VIXL_ASSERT(allow_macro_instructions_);
431   VIXL_ASSERT(pg.IsMerging());
447   VIXL_ASSERT(allow_macro_instructions_);
448   VIXL_ASSERT(pg.IsMerging());
464   VIXL_ASSERT(allow_macro_instructions_);
465   VIXL_ASSERT(pg.IsMerging());
479   VIXL_ASSERT(allow_macro_instructions_);
480   VIXL_ASSERT(imm.FitsInLane(zd));
579       VIXL_ASSERT(AreSameLaneSize(zn, zm));                      \
649     VIXL_ASSERT(allow_macro_instructions_);                        \
691     VIXL_ASSERT(allow_macro_instructions_);                           \
709   VIXL_ASSERT(allow_macro_instructions_);
724   VIXL_ASSERT(allow_macro_instructions_);
739   VIXL_ASSERT(allow_macro_instructions_);
754   VIXL_ASSERT(allow_macro_instructions_);
769   VIXL_ASSERT(allow_macro_instructions_);
784   VIXL_ASSERT(allow_macro_instructions_);
799   VIXL_ASSERT(allow_macro_instructions_);
814   VIXL_ASSERT(allow_macro_instructions_);
825   VIXL_ASSERT(allow_macro_instructions_);
847   VIXL_ASSERT(allow_macro_instructions_);
868   VIXL_ASSERT(allow_macro_instructions_);
908         VIXL_ASSERT(op.IsPlainRegister());
915       VIXL_ASSERT(IsInt5(imm));
945   VIXL_ASSERT(allow_macro_instructions_);
946   VIXL_ASSERT(imm.FitsInLane(zdn));
971   VIXL_ASSERT(allow_macro_instructions_);
998   VIXL_ASSERT(allow_macro_instructions_);
1035   VIXL_ASSERT(allow_macro_instructions_);
1036   VIXL_ASSERT(pd.IsLaneSizeB());
1037   VIXL_ASSERT(pn.IsLaneSizeB());
1057   VIXL_ASSERT(allow_macro_instructions_);
1058   VIXL_ASSERT(AreSameFormat(pd, pn));
1078   VIXL_ASSERT(allow_macro_instructions_);
1093   VIXL_ASSERT(allow_macro_instructions_);
1116   VIXL_ASSERT(addr.IsScalarPlusImmediate());
1133   VIXL_ASSERT(allow_macro_instructions_);
1134   VIXL_ASSERT(rt.IsZRegister() || rt.IsPRegister());
1167   VIXL_ASSERT(allow_macro_instructions_);
1240     VIXL_ASSERT(addr.IsScatterGather());
1308   VIXL_ASSERT(allow_macro_instructions_);
1319   VIXL_ASSERT(allow_macro_instructions_);
1330   VIXL_ASSERT(allow_macro_instructions_);
1341   VIXL_ASSERT(allow_macro_instructions_);
1352   VIXL_ASSERT(allow_macro_instructions_);
1363   VIXL_ASSERT(allow_macro_instructions_);
1374   VIXL_ASSERT(allow_macro_instructions_);
1385   VIXL_ASSERT(allow_macro_instructions_);
1396   VIXL_ASSERT(allow_macro_instructions_);
1407   VIXL_ASSERT(allow_macro_instructions_);
1418   VIXL_ASSERT(allow_macro_instructions_);
1429   VIXL_ASSERT(allow_macro_instructions_);
1440   VIXL_ASSERT(allow_macro_instructions_);
1451   VIXL_ASSERT(allow_macro_instructions_);
1462   VIXL_ASSERT(allow_macro_instructions_);
1473   VIXL_ASSERT(allow_macro_instructions_);
1484   VIXL_ASSERT(allow_macro_instructions_);
1495   VIXL_ASSERT(allow_macro_instructions_);
1510     VIXL_ASSERT(allow_macro_instructions_);                    \
1529   VIXL_ASSERT(allow_macro_instructions_);
1547   VIXL_ASSERT(allow_macro_instructions_);
1565   VIXL_ASSERT(allow_macro_instructions_);
1583   VIXL_ASSERT(allow_macro_instructions_);
1601   VIXL_ASSERT(allow_macro_instructions_);
1618   VIXL_ASSERT(allow_macro_instructions_);
1635   VIXL_ASSERT(allow_macro_instructions_);
1652   VIXL_ASSERT(allow_macro_instructions_);
1849     VIXL_ASSERT(allow_macro_instructions_);          \
1885     VIXL_ASSERT(allow_macro_instructions_);          \
1896   VIXL_ASSERT(allow_macro_instructions_);
1905   VIXL_ASSERT(allow_macro_instructions_);
1914   VIXL_ASSERT(allow_macro_instructions_);
1923   VIXL_ASSERT(allow_macro_instructions_);
1956     VIXL_ASSERT(AreSameLaneSize(zn, zm));
2025   VIXL_ASSERT(allow_macro_instructions_);
2042   VIXL_ASSERT(allow_macro_instructions_);
2059   VIXL_ASSERT(allow_macro_instructions_);
2076   VIXL_ASSERT(allow_macro_instructions_);
2091   VIXL_ASSERT(allow_macro_instructions_);
2109   VIXL_ASSERT(allow_macro_instructions_);
2130   VIXL_ASSERT(allow_macro_instructions_);
2149   VIXL_ASSERT(allow_macro_instructions_);
2171   VIXL_ASSERT(allow_macro_instructions_);
2190   VIXL_ASSERT(allow_macro_instructions_);
2210   VIXL_ASSERT(allow_macro_instructions_);
2258   VIXL_ASSERT(allow_macro_instructions_);