xref: /third_party/vixl/src/aarch64/macro-assembler-aarch64.h

1480   void Fadd(const VRegister& vd, const VRegister& vn, const VRegister& vm) {
1483     fadd(vd, vn, vm);
1485   void Fccmp(const VRegister& vn,
1493     FPCCompareMacro(vn, vm, nzcv, cond, trap);
1495   void Fccmpe(const VRegister& vn,
1499     Fccmp(vn, vm, nzcv, cond, EnableTrap);
1501   void Fcmp(const VRegister& vn,
1506     FPCompareMacro(vn, vm, trap);
1508   void Fcmp(const VRegister& vn, double value, FPTrapFlags trap = DisableTrap);
1509   void Fcmpe(const VRegister& vn, double value);
1510   void Fcmpe(const VRegister& vn, const VRegister& vm) {
1511     Fcmp(vn, vm, EnableTrap);
1514              const VRegister& vn,
1520     fcsel(vd, vn, vm, cond);
1522   void Fcvt(const VRegister& vd, const VRegister& vn) {
1525     fcvt(vd, vn);
1527   void Fcvtl(const VRegister& vd, const VRegister& vn) {
1530     fcvtl(vd, vn);
1532   void Fcvtl2(const VRegister& vd, const VRegister& vn) {
1535     fcvtl2(vd, vn);
1537   void Fcvtn(const VRegister& vd, const VRegister& vn) {
1540     fcvtn(vd, vn);
1542   void Fcvtn2(const VRegister& vd, const VRegister& vn) {
1545     fcvtn2(vd, vn);
1547   void Fcvtxn(const VRegister& vd, const VRegister& vn) {
1550     fcvtxn(vd, vn);
1552   void Fcvtxn2(const VRegister& vd, const VRegister& vn) {
1555     fcvtxn2(vd, vn);
1557   void Fcvtas(const Register& rd, const VRegister& vn) {
1561     fcvtas(rd, vn);
1563   void Fcvtau(const Register& rd, const VRegister& vn) {
1567     fcvtau(rd, vn);
1569   void Fcvtms(const Register& rd, const VRegister& vn) {
1573     fcvtms(rd, vn);
1575   void Fcvtmu(const Register& rd, const VRegister& vn) {
1579     fcvtmu(rd, vn);
1581   void Fcvtns(const Register& rd, const VRegister& vn) {
1585     fcvtns(rd, vn);
1587   void Fcvtnu(const Register& rd, const VRegister& vn) {
1591     fcvtnu(rd, vn);
1593   void Fcvtps(const Register& rd, const VRegister& vn) {
1597     fcvtps(rd, vn);
1599   void Fcvtpu(const Register& rd, const VRegister& vn) {
1603     fcvtpu(rd, vn);
1605   void Fcvtzs(const Register& rd, const VRegister& vn, int fbits = 0) {
1609     fcvtzs(rd, vn, fbits);
1611   void Fjcvtzs(const Register& rd, const VRegister& vn) {
1615     fjcvtzs(rd, vn);
1617   void Fcvtzu(const Register& rd, const VRegister& vn, int fbits = 0) {
1621     fcvtzu(rd, vn, fbits);
1623   void Fdiv(const VRegister& vd, const VRegister& vn, const VRegister& vm) {
1626     fdiv(vd, vn, vm);
1628   void Fmax(const VRegister& vd, const VRegister& vn, const VRegister& vm) {
1631     fmax(vd, vn, vm);
1633   void Fmaxnm(const VRegister& vd, const VRegister& vn, const VRegister& vm) {
1636     fmaxnm(vd, vn, vm);
1638   void Fmin(const VRegister& vd, const VRegister& vn, const VRegister& vm) {
1641     fmin(vd, vn, vm);
1643   void Fminnm(const VRegister& vd, const VRegister& vn, const VRegister& vm) {
1646     fminnm(vd, vn, vm);
1648   void Fmov(const VRegister& vd, const VRegister& vn) {
1651     // TODO: Use DiscardMoveMode to allow this move to be elided if vd.Is(vn).
1652     fmov(vd, vn);
1669   void Fmov(const Register& rd, const VRegister& vn, int index) {
1672     if (vn.Is1D() && (index == 0)) {
1673       mov(rd, vn, index);
1675       fmov(rd, vn, index);
1692   void Fmov(Register rd, VRegister vn) {
1696     fmov(rd, vn);
1698   void Fmul(const VRegister& vd, const VRegister& vn, const VRegister& vm) {
1701     fmul(vd, vn, vm);
1703   void Fnmul(const VRegister& vd, const VRegister& vn, const VRegister& vm) {
1706     fnmul(vd, vn, vm);
1709              const VRegister& vn,
1714     fmadd(vd, vn, vm, va);
1717              const VRegister& vn,
1722     fmsub(vd, vn, vm, va);
1725               const VRegister& vn,
1730     fnmadd(vd, vn, vm, va);
1733               const VRegister& vn,
1738     fnmsub(vd, vn, vm, va);
1740   void Fsub(const VRegister& vd, const VRegister& vn, const VRegister& vm) {
1743     fsub(vd, vn, vm);
2627   void Tbl(const VRegister& vd, const VRegister& vn, const VRegister& vm) {
2630     tbl(vd, vn, vm);
2633            const VRegister& vn,
2638     tbl(vd, vn, vn2, vm);
2641            const VRegister& vn,
2647     tbl(vd, vn, vn2, vn3, vm);
2650            const VRegister& vn,
2657     tbl(vd, vn, vn2, vn3, vn4, vm);
2659   void Tbx(const VRegister& vd, const VRegister& vn, const VRegister& vm) {
2662     tbx(vd, vn, vm);
2665            const VRegister& vn,
2670     tbx(vd, vn, vn2, vm);
2673            const VRegister& vn,
2679     tbx(vd, vn, vn2, vn3, vm);
2682            const VRegister& vn,
2689     tbx(vd, vn, vn2, vn3, vn4, vm);
2991   void MASM(const VRegister& vd, const VRegister& vn, const VRegister& vm) { \
2994     ASM(vd, vn, vm);                                                         \
3079   void MASM(const VRegister& vd, const VRegister& vn) { \
3082     ASM(vd, vn);                                        \
3096   void MASM(const VRegister& vd, const VRegister& vn, double imm) { \
3099     ASM(vd, vn, imm);                                               \
3147             const VRegister& vn,            \
3152     ASM(vd, vn, vm, vm_index);              \
3192   void MASM(const VRegister& vd, const VRegister& vn, int shift) { \
3195     ASM(vd, vn, shift);                                            \
3207   void MASM(const VRegister& vd, const VRegister& vn, int shift) { \
3210     if (vn.GetLaneSizeInBits() == static_cast<unsigned>(shift)) {  \
3211       ASM1(vd, vn, shift);                                         \
3213       ASM2(vd, vn, shift);                                         \
3266   void Cmeq(const VRegister& vd, const VRegister& vn, int imm) {
3269     cmeq(vd, vn, imm);
3271   void Cmge(const VRegister& vd, const VRegister& vn, int imm) {
3274     cmge(vd, vn, imm);
3276   void Cmgt(const VRegister& vd, const VRegister& vn, int imm) {
3279     cmgt(vd, vn, imm);
3281   void Cmle(const VRegister& vd, const VRegister& vn, int imm) {
3284     cmle(vd, vn, imm);
3286   void Cmlt(const VRegister& vd, const VRegister& vn, int imm) {
3289     cmlt(vd, vn, imm);
3291   void Dup(const VRegister& vd, const VRegister& vn, int index) {
3294     dup(vd, vn, index);
3302            const VRegister& vn,
3307     ext(vd, vn, vm, index);
3310              const VRegister& vn,
3315     fcadd(vd, vn, vm, rot);
3318              const VRegister& vn,
3324     fcmla(vd, vn, vm, vm_index, rot);
3327              const VRegister& vn,
3332     fcmla(vd, vn, vm, rot);
3336            const VRegister& vn,
3340     ins(vd, vd_index, vn, vn_index);
3457            const VRegister& vn,
3461     mov(vd, vd_index, vn, vn_index);
3463   void Mov(const VRegister& vd, const VRegister& vn, int index) {
3466     mov(vd, vn, index);
3473   void Mov(const Register& rd, const VRegister& vn, int vn_index) {
3476     mov(rd, vn, vn_index);
3496   void Scvtf(const VRegister& vd, const VRegister& vn, int fbits = 0) {
3499     scvtf(vd, vn, fbits);
3501   void Ucvtf(const VRegister& vd, const VRegister& vn, int fbits = 0) {
3504     ucvtf(vd, vn, fbits);
3506   void Fcvtzs(const VRegister& vd, const VRegister& vn, int fbits = 0) {
3509     fcvtzs(vd, vn, fbits);
3511   void Fcvtzu(const VRegister& vd, const VRegister& vn, int fbits = 0) {
3514     fcvtzu(vd, vn, fbits);
3597   void Smov(const Register& rd, const VRegister& vn, int vn_index) {
3600     smov(rd, vn, vn_index);
3602   void Umov(const Register& rd, const VRegister& vn, int vn_index) {
3605     umov(rd, vn, vn_index);
3866               const VRegister& vn,
3870     clasta(vd, pg, vn, zm);
3886               const VRegister& vn,
3890     clastb(vd, pg, vn, zm);
4160   void Cpy(const ZRegister& zd, const PRegisterM& pg, const VRegister& vn) {
4163     cpy(zd, pg, vn);
4351              const VRegister& vn,
4355     fadda(vd, pg, vn, zm);
5470   void Mov(const ZRegister& zd, const VRegister& vn) {
5473     mov(zd, vn);
5496   void Mov(const ZRegister& zd, const PRegisterM& pg, const VRegister& vn) {
5499     mov(zd, pg, vn);

Indexes created Thu Nov 07 10:32:03 CST 2024