Lines Matching refs:temp
540 Register temp;
543 temp = rd.IsSP() ? temps.AcquireSameSizeAs(rd) : rd;
555 if (emit_code) masm->movn(temp, ~imm16 & 0xffff, 16 * i);
558 if (emit_code) masm->movz(temp, imm16, 16 * i);
564 if (emit_code) masm->movk(temp, imm16, 16 * i);
575 if (emit_code) masm->mov(rd, temp);
880 // Use `rd` as a temp, if we can.
952 Register temp = temps.AcquireSameSizeAs(rn);
953 VIXL_ASSERT(!temp.Aliases(rn));
958 Operand imm_operand = MoveImmediateForShiftedOp(temp, immediate, mode);
962 // register so we use the temp register as an intermediate again.
963 Logical(temp, rn, imm_operand, op);
964 Mov(rd, temp);
978 Register temp = temps.AcquireSameSizeAs(rn);
979 VIXL_ASSERT(!temp.Aliases(rn));
980 EmitExtendShift(temp,
984 Logical(rd, rn, Operand(temp), op);
1040 Register temp = temps.AcquireW();
1041 movz(temp, imm);
1042 dup(vd, temp);
1118 Register temp = temps.AcquireW();
1119 Mov(temp, imm);
1120 dup(vd, temp);
1151 Register temp = temps.AcquireX();
1152 Mov(temp, imm);
1154 fmov(vd.D(), temp);
1156 dup(vd.V2D(), temp);
1201 Register temp = temps.AcquireX();
1202 Mov(temp, hi);
1203 Ins(vd.V2D(), 1, temp);
1285 Register temp = temps.AcquireSameSizeAs(rn);
1286 Mov(temp, operand);
1287 ConditionalCompare(rn, temp, nzcv, cond, op);
1364 Register temp = temps.AcquireSameSizeAs(rd);
1365 masm->Mov(temp, left);
1366 left = temp;
1372 Register temp = temps.AcquireSameSizeAs(rd);
1373 masm->Mov(temp, right);
1374 right = temp;
1525 Register temp = temps.AcquireSameSizeAs(rd); \
1526 Mov(temp, imm); \
1527 MASM(rd, rn, temp); \
1738 Register temp = temps.AcquireW();
1739 Mov(temp, rawbits);
1740 Fmov(vd, temp);
1850 CPURegister temp = temps.AcquireCPURegisterOfSize(operand_size);
1851 Ldr(temp, src.GetMemOperand());
1852 Str(temp, dst.GetMemOperand());
1907 // Use `rd` as a temp, if we can.
1913 Register temp = temps.AcquireSameSizeAs(rn);
1929 MoveImmediateForShiftedOp(temp, operand.GetImmediate(), mode);
1932 Mov(temp, operand);
1933 AddSub(rd, rn, temp, S, op);
1998 // Use `rd` as a temp, if we can.
2008 Register temp = temps.AcquireSameSizeAs(rn);
2009 Mov(temp, operand);
2010 AddSubWithCarry(rd, rn, Operand(temp), S, op);
2018 Register temp = temps.AcquireSameSizeAs(rn);
2019 EmitShift(temp,
2023 AddSubWithCarry(rd, rn, Operand(temp), S, op);
2033 Register temp = temps.AcquireSameSizeAs(rn);
2034 EmitExtendShift(temp,
2038 AddSubWithCarry(rd, rn, Operand(temp), S, op);
2101 Register temp = temps.AcquireSameSizeAs(addr.GetBaseRegister());
2102 Mov(temp, addr.GetOffset());
2103 LoadStore(rt, MemOperand(addr.GetBaseRegister(), temp), op);
2153 Register temp = temps.AcquireSameSizeAs(base);
2154 Add(temp, base, offset);
2155 LoadStorePair(rt, rt2, MemOperand(temp), op);
2185 Register temp = temps.AcquireSameSizeAs(addr.GetBaseRegister());
2186 Mov(temp, addr.GetOffset());
2187 Prefetch(op, MemOperand(addr.GetBaseRegister(), temp));