Lines Matching refs:rn
801 const Register& rn,
804 LogicalMacro(rd, rn, operand, AND);
809 const Register& rn,
812 LogicalMacro(rd, rn, operand, ANDS);
816 void MacroAssembler::Tst(const Register& rn, const Operand& operand) {
818 Ands(AppropriateZeroRegFor(rn), rn, operand);
823 const Register& rn,
826 LogicalMacro(rd, rn, operand, BIC);
831 const Register& rn,
834 LogicalMacro(rd, rn, operand, BICS);
839 const Register& rn,
842 LogicalMacro(rd, rn, operand, ORR);
847 const Register& rn,
850 LogicalMacro(rd, rn, operand, ORN);
855 const Register& rn,
858 LogicalMacro(rd, rn, operand, EOR);
863 const Register& rn,
866 LogicalMacro(rd, rn, operand, EON);
871 const Register& rn,
882 // We read `rn` after evaluating `operand`.
883 temps.Exclude(rn);
916 Mov(rd, rn);
929 Mov(rd, rn);
935 Mvn(rd, rn);
949 LogicalImmediate(rd, rn, n, imm_s, imm_r, op);
952 Register temp = temps.AcquireSameSizeAs(rn);
953 VIXL_ASSERT(!temp.Aliases(rn));
957 PreShiftImmMode mode = rn.IsSP() ? kNoShift : kAnyShift;
963 Logical(temp, rn, imm_operand, op);
966 Logical(rd, rn, imm_operand, op);
978 Register temp = temps.AcquireSameSizeAs(rn);
979 VIXL_ASSERT(!temp.Aliases(rn));
984 Logical(rd, rn, Operand(temp), op);
988 Logical(rd, rn, operand, op);
1238 void MacroAssembler::Ccmp(const Register& rn,
1244 ConditionalCompareMacro(rn, -operand.GetImmediate(), nzcv, cond, CCMN);
1246 ConditionalCompareMacro(rn, operand, nzcv, cond, CCMP);
1251 void MacroAssembler::Ccmn(const Register& rn,
1257 ConditionalCompareMacro(rn, -operand.GetImmediate(), nzcv, cond, CCMP);
1259 ConditionalCompareMacro(rn, operand, nzcv, cond, CCMN);
1264 void MacroAssembler::ConditionalCompareMacro(const Register& rn,
1280 ConditionalCompare(rn, operand, nzcv, cond, op);
1285 Register temp = temps.AcquireSameSizeAs(rn);
1287 ConditionalCompare(rn, temp, nzcv, cond, op);
1488 const Register& rn,
1496 AddSubMacro(rd, rn, -imm, S, SUB);
1500 AddSubMacro(rd, rn, operand, S, ADD);
1505 const Register& rn,
1507 Add(rd, rn, operand, SetFlags);
1518 const Register& rn, \
1527 MASM(rd, rn, temp); \
1532 ASM(rd, rn, op); \
1576 const Register& rn,
1584 AddSubMacro(rd, rn, -imm, S, ADD);
1588 AddSubMacro(rd, rn, operand, S, SUB);
1593 const Register& rn,
1595 Sub(rd, rn, operand, SetFlags);
1599 void MacroAssembler::Cmn(const Register& rn, const Operand& operand) {
1601 Adds(AppropriateZeroRegFor(rn), rn, operand);
1605 void MacroAssembler::Cmp(const Register& rn, const Operand& operand) {
1607 Subs(AppropriateZeroRegFor(rn), rn, operand);
1888 const Register& rn,
1897 if (operand.IsZero() && rd.Is(rn) && rd.Is64Bits() && rn.Is64Bits() &&
1904 (rn.IsZero() && !operand.IsShiftedRegister()) ||
1909 // We read `rn` after evaluating `operand`.
1910 temps.Exclude(rn);
1913 Register temp = temps.AcquireSameSizeAs(rn);
1924 } else if (rn.IsSP()) {
1930 AddSub(rd, rn, imm_operand, S, op);
1933 AddSub(rd, rn, temp, S, op);
1936 AddSub(rd, rn, operand, S, op);
1942 const Register& rn,
1945 AddSubWithCarryMacro(rd, rn, operand, LeaveFlags, ADC);
1950 const Register& rn,
1953 AddSubWithCarryMacro(rd, rn, operand, SetFlags, ADC);
1958 const Register& rn,
1961 AddSubWithCarryMacro(rd, rn, operand, LeaveFlags, SBC);
1966 const Register& rn,
1969 AddSubWithCarryMacro(rd, rn, operand, SetFlags, SBC);
1988 const Register& rn,
1992 VIXL_ASSERT(rd.GetSizeInBits() == rn.GetSizeInBits());
2000 // We read `rn` after evaluating `operand`.
2001 temps.Exclude(rn);
2008 Register temp = temps.AcquireSameSizeAs(rn);
2010 AddSubWithCarry(rd, rn, Operand(temp), S, op);
2018 Register temp = temps.AcquireSameSizeAs(rn);
2023 AddSubWithCarry(rd, rn, Operand(temp), S, op);
2033 Register temp = temps.AcquireSameSizeAs(rn);
2038 AddSubWithCarry(rd, rn, Operand(temp), S, op);
2041 AddSubWithCarry(rd, rn, operand, S, op);