Lines Matching refs:VIXL_ASSERT
38 VIXL_ASSERT(masm_->GetCursorOffset() < checkpoint_);
67 VIXL_ASSERT(!IsBlocked());
69 VIXL_ASSERT(IsEmpty());
131 VIXL_ASSERT(!IsBlocked());
132 VIXL_ASSERT(!IsEmpty());
143 VIXL_ASSERT(emit_size % kInstructionSize == 0);
160 VIXL_ASSERT((pool_size % kWRegSizeInBytes) == 0);
172 VIXL_ASSERT((*it)->IsUsed());
190 VIXL_ASSERT(masm_->GetCursorOffset() == literal->GetLastUse());
193 VIXL_ASSERT(masm_->GetCursorOffset() >= first_use_);
206 VIXL_ASSERT(use_position > first_use_);
221 VIXL_ASSERT(IsEmpty() || masm_->GetCursorOffset() <
233 VIXL_ASSERT(!label->IsBound());
244 VIXL_ASSERT(checkpoint_ == kNoCheckpointRequired);
278 VIXL_ASSERT(masm_->GetCursorOffset() + kPoolNonVeneerCodeSize <
296 VIXL_ASSERT(!IsBlocked());
297 VIXL_ASSERT(!IsEmpty());
455 VIXL_ASSERT(!literal_pool_.IsBlocked());
470 VIXL_ASSERT(veneer_pool_.IsEmpty());
493 VIXL_ASSERT(IsUint32(imm) || IsInt32(imm) || rd.Is64Bits());
548 VIXL_ASSERT((reg_size % 16) == 0);
570 VIXL_ASSERT(first_mov_done);
584 VIXL_ASSERT((reg.Is(NoReg) || (type >= kBranchTypeFirstUsingReg)) &&
618 VIXL_ASSERT(Instruction::GetImmBranchForwardRange(UncondBranchType) >
629 VIXL_ASSERT(Instruction::GetImmBranchForwardRange(CondBranchType) >
631 VIXL_ASSERT(allow_macro_instructions_);
632 VIXL_ASSERT((cond != al) && (cond != nv));
659 VIXL_ASSERT(Instruction::GetImmBranchForwardRange(CompareBranchType) >
661 VIXL_ASSERT(allow_macro_instructions_);
662 VIXL_ASSERT(!rt.IsZero());
689 VIXL_ASSERT(Instruction::GetImmBranchForwardRange(CompareBranchType) >
691 VIXL_ASSERT(allow_macro_instructions_);
692 VIXL_ASSERT(!rt.IsZero());
720 VIXL_ASSERT(allow_macro_instructions_);
721 VIXL_ASSERT(!rt.IsZero());
749 VIXL_ASSERT(allow_macro_instructions_);
750 VIXL_ASSERT(!rt.IsZero());
773 VIXL_ASSERT(allow_macro_instructions_);
794 VIXL_ASSERT(allow_macro_instructions_);
803 VIXL_ASSERT(allow_macro_instructions_);
811 VIXL_ASSERT(allow_macro_instructions_);
817 VIXL_ASSERT(allow_macro_instructions_);
825 VIXL_ASSERT(allow_macro_instructions_);
833 VIXL_ASSERT(allow_macro_instructions_);
841 VIXL_ASSERT(allow_macro_instructions_);
849 VIXL_ASSERT(allow_macro_instructions_);
857 VIXL_ASSERT(allow_macro_instructions_);
865 VIXL_ASSERT(allow_macro_instructions_);
900 VIXL_ASSERT(((immediate >> kWRegSize) == 0) ||
905 VIXL_ASSERT(rd.Is64Bits() || IsUint32(immediate));
953 VIXL_ASSERT(!temp.Aliases(rn));
970 VIXL_ASSERT(operand.GetRegister().GetSizeInBits() <= rd.GetSizeInBits());
973 VIXL_ASSERT(operand.GetShiftAmount() <= 4);
974 VIXL_ASSERT(
979 VIXL_ASSERT(!temp.Aliases(rn));
987 VIXL_ASSERT(operand.IsShiftedRegister());
996 VIXL_ASSERT(allow_macro_instructions_);
1025 VIXL_ASSERT(IsUint16(imm));
1048 VIXL_ASSERT(IsUint32(imm));
1166 VIXL_ASSERT(allow_macro_instructions_);
1172 VIXL_ASSERT(IsUint8(imm));
1189 VIXL_ASSERT(vd.Is128Bits());
1209 VIXL_ASSERT(allow_macro_instructions_);
1233 VIXL_ASSERT(allow_macro_instructions_);
1242 VIXL_ASSERT(allow_macro_instructions_);
1255 VIXL_ASSERT(allow_macro_instructions_);
1269 VIXL_ASSERT((cond != al) && (cond != nv));
1301 VIXL_ASSERT(!emit_code || masm->allow_macro_instructions_);
1302 VIXL_ASSERT((cond != al) && (cond != nv));
1303 VIXL_ASSERT(!rd.IsZero() && !rd.IsSP());
1304 VIXL_ASSERT(left.IsImmediate() || !left.GetRegister().IsSP());
1305 VIXL_ASSERT(right.IsImmediate() || !right.GetRegister().IsSP());
1379 VIXL_ASSERT(left.IsPlainRegister() && right.IsPlainRegister());
1458 VIXL_ASSERT((right.IsImmediate() || right.IsZero()) &&
1480 VIXL_ASSERT(imm == -1);
1491 VIXL_ASSERT(allow_macro_instructions_);
1520 VIXL_ASSERT(allow_macro_instructions_); \
1538 VIXL_ASSERT(allow_macro_instructions_);
1544 VIXL_ASSERT(allow_macro_instructions_);
1552 VIXL_ASSERT(allow_macro_instructions_);
1558 VIXL_ASSERT(allow_macro_instructions_);
1564 VIXL_ASSERT(allow_macro_instructions_);
1570 VIXL_ASSERT(allow_macro_instructions_);
1579 VIXL_ASSERT(allow_macro_instructions_);
1600 VIXL_ASSERT(allow_macro_instructions_);
1606 VIXL_ASSERT(allow_macro_instructions_);
1612 VIXL_ASSERT(allow_macro_instructions_);
1634 VIXL_ASSERT(allow_macro_instructions_);
1654 VIXL_ASSERT(vd.Is1D() || vd.Is2D());
1674 VIXL_ASSERT(allow_macro_instructions_);
1694 VIXL_ASSERT(vd.Is1S() || vd.Is2S() || vd.Is4S());
1714 VIXL_ASSERT(allow_macro_instructions_);
1727 VIXL_ASSERT(vd.Is1H() || vd.Is4H() || vd.Is8H());
1751 VIXL_ASSERT(allow_macro_instructions_);
1761 VIXL_ASSERT(allow_macro_instructions_);
1792 VIXL_ASSERT((shift_low >= 0) && (shift_low < 64));
1799 VIXL_ASSERT((shift_high >= 0) && (shift_high < 64));
1824 VIXL_ASSERT(dst.IsValid() && src.IsValid());
1827 VIXL_ASSERT(dst.GetSizeInBits() == src.GetSizeInBits());
1828 VIXL_ASSERT(dst.GetSizeInBits() <= kXRegSize);
1867 VIXL_ASSERT(mem_op.GetAddrMode() == Offset);
1872 VIXL_ASSERT(mem_op.IsRegisterOffset());
1877 VIXL_ASSERT(extend != NO_EXTEND);
1880 VIXL_ASSERT(extend == NO_EXTEND);
1944 VIXL_ASSERT(allow_macro_instructions_);
1952 VIXL_ASSERT(allow_macro_instructions_);
1960 VIXL_ASSERT(allow_macro_instructions_);
1968 VIXL_ASSERT(allow_macro_instructions_);
1974 VIXL_ASSERT(allow_macro_instructions_);
1981 VIXL_ASSERT(allow_macro_instructions_);
1992 VIXL_ASSERT(rd.GetSizeInBits() == rn.GetSizeInBits());
2013 VIXL_ASSERT(operand.GetRegister().GetSizeInBits() == rd.GetSizeInBits());
2014 VIXL_ASSERT(operand.GetShift() != ROR);
2015 VIXL_ASSERT(
2026 VIXL_ASSERT(operand.GetRegister().GetSizeInBits() <= rd.GetSizeInBits());
2029 VIXL_ASSERT(operand.GetShiftAmount() <= 4);
2030 VIXL_ASSERT(
2049 VIXL_ASSERT(allow_macro_instructions_);
2056 VIXL_ASSERT(allow_macro_instructions_);
2063 VIXL_ASSERT(allow_macro_instructions_);
2071 VIXL_ASSERT(allow_macro_instructions_); \
2081 VIXL_ASSERT(addr.IsImmediateOffset() || addr.IsImmediatePostIndex() ||
2123 VIXL_ASSERT(allow_macro_instructions_); \
2134 VIXL_ASSERT(!addr.IsRegisterOffset());
2160 VIXL_ASSERT(addr.IsImmediatePreIndex());
2172 VIXL_ASSERT(addr.IsImmediateOffset() || addr.IsRegisterOffset());
2199 VIXL_ASSERT(allow_macro_instructions_);
2200 VIXL_ASSERT(AreSameSizeAndType(src0, src1, src2, src3));
2201 VIXL_ASSERT(src0.IsValid());
2217 VIXL_ASSERT(allow_macro_instructions_);
2218 VIXL_ASSERT(!AreAliased(dst0, dst1, dst2, dst3));
2219 VIXL_ASSERT(AreSameSizeAndType(dst0, dst1, dst2, dst3));
2220 VIXL_ASSERT(dst0.IsValid());
2231 VIXL_ASSERT(!registers.Overlaps(*GetScratchRegisterList()));
2232 VIXL_ASSERT(!registers.Overlaps(*GetScratchVRegisterList()));
2233 VIXL_ASSERT(allow_macro_instructions_);
2263 VIXL_ASSERT(!registers.Overlaps(*GetScratchRegisterList()));
2264 VIXL_ASSERT(!registers.Overlaps(*GetScratchVRegisterList()));
2265 VIXL_ASSERT(allow_macro_instructions_);
2297 VIXL_ASSERT(allow_macro_instructions_);
2316 VIXL_ASSERT(count == 0);
2332 VIXL_ASSERT(AreSameSizeAndType(src0, src1, src2, src3));
2333 VIXL_ASSERT(size == src0.GetSizeInBytes());
2339 VIXL_ASSERT(src1.IsNone() && src2.IsNone() && src3.IsNone());
2343 VIXL_ASSERT(src2.IsNone() && src3.IsNone());
2347 VIXL_ASSERT(src3.IsNone());
2376 VIXL_ASSERT(AreSameSizeAndType(dst0, dst1, dst2, dst3));
2377 VIXL_ASSERT(size == dst0.GetSizeInBytes());
2383 VIXL_ASSERT(dst1.IsNone() && dst2.IsNone() && dst3.IsNone());
2387 VIXL_ASSERT(dst2.IsNone() && dst3.IsNone());
2391 VIXL_ASSERT(dst3.IsNone());
2414 VIXL_ASSERT((count * size) % 16 == 0);
2430 VIXL_ASSERT((count * size) % 16 == 0);
2435 VIXL_ASSERT(allow_macro_instructions_);
2437 VIXL_ASSERT(offset.GetImmediate() >= 0);
2445 VIXL_ASSERT(allow_macro_instructions_);
2447 VIXL_ASSERT(offset.GetImmediate() >= 0);
2455 VIXL_ASSERT(allow_macro_instructions_);
2462 VIXL_ASSERT(size.GetImmediate() > 0);
2464 VIXL_ASSERT((size.GetImmediate() % 16) == 0);
2477 VIXL_ASSERT(allow_macro_instructions_);
2484 VIXL_ASSERT(size.GetImmediate() > 0);
2486 VIXL_ASSERT((size.GetImmediate() % 16) == 0);
2501 VIXL_ASSERT(sp.Is(StackPointer()));
2526 VIXL_ASSERT(sp.Is(StackPointer()));
2558 VIXL_ASSERT(!(mem.IsPreIndex() || mem.IsPostIndex()));
2560 VIXL_ASSERT(!registers.Overlaps(tmp_list_));
2562 VIXL_ASSERT(!registers.Overlaps(v_tmp_list_));
2563 VIXL_ASSERT(!registers.Overlaps(p_tmp_list_));
2564 VIXL_ASSERT(!registers.IncludesAliasOf(sp));
2571 VIXL_ASSERT(IsPowerOf2(reg_size));
2583 VIXL_ASSERT(op == kLoad);
2594 VIXL_ASSERT(op == kLoad);
2603 VIXL_ASSERT(op == kLoad);
2638 VIXL_ASSERT(!sp.Is(StackPointer()));
2658 VIXL_ASSERT(!kCallerSaved.IncludesAliasOf(StackPointer()));
2701 VIXL_ASSERT(args[i].IsNone());
2730 VIXL_ASSERT(pcs[i].GetType() == args[i].GetType());
2734 VIXL_ASSERT(pcs[i].IsVRegister());
2801 VIXL_ASSERT(pcs[i].Is64Bits());
2804 VIXL_ASSERT(arg_pattern < (1 << kPrintfArgPatternBits));
2823 VIXL_ASSERT(!sp.Aliases(arg0));
2824 VIXL_ASSERT(!sp.Aliases(arg1));
2825 VIXL_ASSERT(!sp.Aliases(arg2));
2826 VIXL_ASSERT(!sp.Aliases(arg3));
2888 VIXL_ASSERT(allow_macro_instructions_);
2906 VIXL_ASSERT(GetSizeOfCodeGeneratedSince(&start) == kTraceParamsOffset);
2909 VIXL_ASSERT(GetSizeOfCodeGeneratedSince(&start) == kTraceCommandOffset);
2919 VIXL_ASSERT(allow_macro_instructions_);
2937 VIXL_ASSERT(GetSizeOfCodeGeneratedSince(&start) == kLogParamsOffset);
2963 VIXL_ASSERT(allow_macro_instructions_);
2964 VIXL_ASSERT(generate_simulator_code_);
2967 VIXL_ASSERT(CPUFeatures::kNumberOfFeatures <=
3004 VIXL_ASSERT(allow_macro_instructions_);
3005 VIXL_ASSERT(generate_simulator_code_);
3012 VIXL_ASSERT(allow_macro_instructions_);
3013 VIXL_ASSERT(generate_simulator_code_);
3020 VIXL_ASSERT(masm_ == NULL);
3021 VIXL_ASSERT(masm != NULL);
3030 VIXL_ASSERT(available->GetType() == CPURegister::kRegister);
3031 VIXL_ASSERT(available_v->GetType() == CPURegister::kVRegister);
3032 VIXL_ASSERT(available_p->GetType() == CPURegister::kPRegister);
3076 VIXL_ASSERT(masm_ != NULL);
3086 VIXL_ASSERT(masm_ != NULL);
3090 VIXL_ASSERT(list.GetType() != CPURegister::kNoRegister);
3106 VIXL_ASSERT(masm_ != NULL);
3141 VIXL_ASSERT(regs[i].IsNone());
3201 VIXL_ASSERT(regs[i].IsNone());
3235 VIXL_ASSERT(!AreAliased(result, xzr, sp));