Lines Matching defs:regs
3134 const CPURegister regs[] = {reg1, reg2, reg3, reg4};
3136 for (size_t i = 0; i < ArrayLength(regs); i++) {
3137 RegList bit = regs[i].GetBit();
3138 switch (regs[i].GetBank()) {
3141 VIXL_ASSERT(regs[i].IsNone());
3194 const CPURegister regs[] = {reg1, reg2, reg3, reg4};
3196 for (size_t i = 0; i < ArrayLength(regs); i++) {
3197 RegList bit = regs[i].GetBit();
3198 switch (regs[i].GetBank()) {
3201 VIXL_ASSERT(regs[i].IsNone());
3246 RegList regs) {
3247 available->SetList(available->GetList() | regs);
3252 RegList regs) {
3253 available->SetList(available->GetList() | regs);