Lines Matching defs:operand
802 const Operand& operand) {
804 LogicalMacro(rd, rn, operand, AND);
810 const Operand& operand) {
812 LogicalMacro(rd, rn, operand, ANDS);
816 void MacroAssembler::Tst(const Register& rn, const Operand& operand) {
818 Ands(AppropriateZeroRegFor(rn), rn, operand);
824 const Operand& operand) {
826 LogicalMacro(rd, rn, operand, BIC);
832 const Operand& operand) {
834 LogicalMacro(rd, rn, operand, BICS);
840 const Operand& operand) {
842 LogicalMacro(rd, rn, operand, ORR);
848 const Operand& operand) {
850 LogicalMacro(rd, rn, operand, ORN);
856 const Operand& operand) {
858 LogicalMacro(rd, rn, operand, EOR);
864 const Operand& operand) {
866 LogicalMacro(rd, rn, operand, EON);
872 const Operand& operand,
882 // We read `rn` after evaluating `operand`.
884 // It doesn't matter if `operand` is in `temps` (e.g. because it alises `rd`)
887 if (operand.IsImmediate()) {
888 uint64_t immediate = operand.GetImmediate();
969 } else if (operand.IsExtendedRegister()) {
970 VIXL_ASSERT(operand.GetRegister().GetSizeInBits() <= rd.GetSizeInBits());
973 VIXL_ASSERT(operand.GetShiftAmount() <= 4);
975 operand.GetRegister().Is64Bits() ||
976 ((operand.GetExtend() != UXTX) && (operand.GetExtend() != SXTX)));
981 operand.GetRegister(),
982 operand.GetExtend(),
983 operand.GetShiftAmount());
986 // The operand can be encoded in the instruction.
987 VIXL_ASSERT(operand.IsShiftedRegister());
988 Logical(rd, rn, operand, op);
994 const Operand& operand,
1000 if (operand.IsImmediate()) {
1002 Mov(rd, operand.GetImmediate());
1003 } else if (operand.IsShiftedRegister() && (operand.GetShiftAmount() != 0)) {
1008 operand.GetRegister(),
1009 operand.GetShift(),
1010 operand.GetShiftAmount());
1011 } else if (operand.IsExtendedRegister()) {
1015 operand.GetRegister(),
1016 operand.GetExtend(),
1017 operand.GetShiftAmount());
1019 Mov(rd, operand.GetRegister(), discard_mode);
1208 void MacroAssembler::Mvn(const Register& rd, const Operand& operand) {
1213 if (operand.IsImmediate()) {
1215 Mvn(rd, operand.GetImmediate());
1216 } else if (operand.IsExtendedRegister()) {
1220 operand.GetRegister(),
1221 operand.GetExtend(),
1222 operand.GetShiftAmount());
1227 mvn(rd, operand);
1239 const Operand& operand,
1243 if (operand.IsImmediate() && (operand.GetImmediate() < 0)) {
1244 ConditionalCompareMacro(rn, -operand.GetImmediate(), nzcv, cond, CCMN);
1246 ConditionalCompareMacro(rn, operand, nzcv, cond, CCMP);
1252 const Operand& operand,
1256 if (operand.IsImmediate() && (operand.GetImmediate() < 0)) {
1257 ConditionalCompareMacro(rn, -operand.GetImmediate(), nzcv, cond, CCMP);
1259 ConditionalCompareMacro(rn, operand, nzcv, cond, CCMN);
1265 const Operand& operand,
1275 if ((operand.IsShiftedRegister() && (operand.GetShiftAmount() == 0)) ||
1276 (operand.IsImmediate() &&
1277 IsImmConditionalCompare(operand.GetImmediate()))) {
1278 // The immediate can be encoded in the instruction, or the operand is an
1280 ConditionalCompare(rn, operand, nzcv, cond, op);
1283 // The operand isn't directly supported by the instruction: perform the
1286 Mov(temp, operand);
1489 const Operand& operand,
1492 if (operand.IsImmediate()) {
1493 int64_t imm = operand.GetImmediate();
1500 AddSubMacro(rd, rn, operand, S, ADD);
1506 const Operand& operand) {
1507 Add(rd, rn, operand, SetFlags);
1577 const Operand& operand,
1580 if (operand.IsImmediate()) {
1581 int64_t imm = operand.GetImmediate();
1588 AddSubMacro(rd, rn, operand, S, SUB);
1594 const Operand& operand) {
1595 Sub(rd, rn, operand, SetFlags);
1599 void MacroAssembler::Cmn(const Register& rn, const Operand& operand) {
1601 Adds(AppropriateZeroRegFor(rn), rn, operand);
1605 void MacroAssembler::Cmp(const Register& rn, const Operand& operand) {
1607 Subs(AppropriateZeroRegFor(rn), rn, operand);
1750 void MacroAssembler::Neg(const Register& rd, const Operand& operand) {
1752 if (operand.IsImmediate()) {
1753 Mov(rd, -operand.GetImmediate());
1755 Sub(rd, AppropriateZeroRegFor(rd), operand);
1760 void MacroAssembler::Negs(const Register& rd, const Operand& operand) {
1762 Subs(rd, AppropriateZeroRegFor(rd), operand);
1804 // return a new leftward-shifting operand.
1808 // return a new rightward-shifting operand.
1889 const Operand& operand,
1897 if (operand.IsZero() && rd.Is(rn) && rd.Is64Bits() && rn.Is64Bits() &&
1903 if ((operand.IsImmediate() && !IsImmAddSub(operand.GetImmediate())) ||
1904 (rn.IsZero() && !operand.IsShiftedRegister()) ||
1905 (operand.IsShiftedRegister() && (operand.GetShift() == ROR))) {
1909 // We read `rn` after evaluating `operand`.
1911 // It doesn't matter if `operand` is in `temps` (e.g. because it alises
1914 if (operand.IsImmediate()) {
1929 MoveImmediateForShiftedOp(temp, operand.GetImmediate(), mode);
1932 Mov(temp, operand);
1936 AddSub(rd, rn, operand, S, op);
1943 const Operand& operand) {
1945 AddSubWithCarryMacro(rd, rn, operand, LeaveFlags, ADC);
1951 const Operand& operand) {
1953 AddSubWithCarryMacro(rd, rn, operand, SetFlags, ADC);
1959 const Operand& operand) {
1961 AddSubWithCarryMacro(rd, rn, operand, LeaveFlags, SBC);
1967 const Operand& operand) {
1969 AddSubWithCarryMacro(rd, rn, operand, SetFlags, SBC);
1973 void MacroAssembler::Ngc(const Register& rd, const Operand& operand) {
1976 Sbc(rd, zr, operand);
1980 void MacroAssembler::Ngcs(const Register& rd, const Operand& operand) {
1983 Sbcs(rd, zr, operand);
1989 const Operand& operand,
2000 // We read `rn` after evaluating `operand`.
2002 // It doesn't matter if `operand` is in `temps` (e.g. because it alises `rd`)
2005 if (operand.IsImmediate() ||
2006 (operand.IsShiftedRegister() && (operand.GetShift() == ROR))) {
2009 Mov(temp, operand);
2011 } else if (operand.IsShiftedRegister() && (operand.GetShiftAmount() != 0)) {
2013 VIXL_ASSERT(operand.GetRegister().GetSizeInBits() == rd.GetSizeInBits());
2014 VIXL_ASSERT(operand.GetShift() != ROR);
2017 operand.GetShiftAmount()));
2020 operand.GetRegister(),
2021 operand.GetShift(),
2022 operand.GetShiftAmount());
2024 } else if (operand.IsExtendedRegister()) {
2026 VIXL_ASSERT(operand.GetRegister().GetSizeInBits() <= rd.GetSizeInBits());
2029 VIXL_ASSERT(operand.GetShiftAmount() <= 4);
2031 operand.GetRegister().Is64Bits() ||
2032 ((operand.GetExtend() != UXTX) && (operand.GetExtend() != SXTX)));
2035 operand.GetRegister(),
2036 operand.GetExtend(),
2037 operand.GetShiftAmount());
2041 AddSubWithCarry(rd, rn, operand, S, op);