Lines Matching defs:immediate
494 // The worst case for size is mov 64-bit immediate to sp:
506 // 4. 32-bit orr immediate.
507 // 5. 64-bit orr immediate.
514 // Try to move the immediate in one instruction, and if that fails, switch to
522 // Generic immediate case. Imm will be represented by
874 // The worst case for size is logical immediate to sp:
888 uint64_t immediate = operand.GetImmediate();
891 // If the operation is NOT, invert the operation and immediate.
894 immediate = ~immediate;
897 // Ignore the top 32 bits of an immediate if we're moving to a W register.
900 VIXL_ASSERT(((immediate >> kWRegSize) == 0) ||
901 ((immediate >> kWRegSize) == 0xffffffff));
902 immediate &= kWRegMask;
905 VIXL_ASSERT(rd.Is64Bits() || IsUint32(immediate));
908 if (immediate == 0) {
925 } else if ((rd.Is64Bits() && (immediate == UINT64_C(0xffffffffffffffff))) ||
926 (rd.Is32Bits() && (immediate == UINT64_C(0x00000000ffffffff)))) {
932 Mov(rd, immediate);
947 if (IsImmLogical(immediate, reg_size, &n, &imm_s, &imm_r)) {
951 // Immediate can't be encoded: synthesize using move immediate.
956 // immediate, as the encoding won't allow the subsequent post shift.
958 Operand imm_operand = MoveImmediateForShiftedOp(temp, immediate, mode);
997 // The worst case for size is mov immediate with up to 4 instructions.
1171 // 8-bit immediate.
1175 // 16-bit immediate.
1178 // 32-bit immediate.
1181 // 64-bit immediate.
1200 // immediate is better.
1210 // The worst case for size is mvn immediate with up to 4 instructions.
1270 // The worst case for size is ccmp immediate:
1278 // The immediate can be encoded in the instruction, or the operand is an
1777 // Encode the immediate in a single move instruction, if possible.
1781 // Pre-shift the immediate to the least-significant bits of the register.
1787 // immediate is tested.
1796 // Pre-shift the immediate to the most-significant bits of the register,
1803 // The new immediate has been moved into the destination's low bits:
1807 // The new immediate has been moved into the destination's high bits:
1892 // Worst case is add/sub immediate:
1918 // only pre-shift the immediate right by values supported in the add/sub
1922 // the immediate at all.
1993 // Worst case is addc/subc immediate:
2007 // Add/sub with carry (immediate or ROR shifted register.)
2093 // Check if an immediate offset fits in the immediate field of the
2135 // Worst case is ldp/stp immediate:
2144 // Check if the offset fits in the immediate field of the appropriate
2177 // Check if an immediate offset fits in the immediate field of the
2640 // the assembler directly here. However, this means that large immediate