Lines Matching refs:vform_dst
1252 VectorFormat vform_dst =
1261 dst.ClearForWrite(vform_dst);
1262 dst.SetInt(vform_dst, 0, dst_val);
1270 VectorFormat vform_dst =
1278 dst.ClearForWrite(vform_dst);
1279 dst.SetInt(vform_dst, 0, dst_val);
1287 VectorFormat vform_dst =
1295 dst.ClearForWrite(vform_dst);
1296 dst.SetUint(vform_dst, 0, dst_val);
2113 VectorFormat vform_dst =
2115 dst.ClearForWrite(vform_dst);
2116 dst.SetUint(vform_dst, 0, result);
2132 VectorFormat vform_dst =
2134 dst.ClearForWrite(vform_dst);
2135 dst.SetUint(vform_dst, 0, result);
2151 VectorFormat vform_dst =
2153 dst.ClearForWrite(vform_dst);
2154 dst.SetUint(vform_dst, 0, result);
2544 VectorFormat vform_dst =
2546 acc.ClearForWrite(vform_dst);
3202 VectorFormat vform_dst = vform;
3204 return extractnarrow(vform_dst, dst, false, shifted_src, false);
7760 LogicVRegister Simulator::matmul(VectorFormat vform_dst,
7768 VIXL_ASSERT((vform_dst == kFormat4S) || (vform_dst == kFormatVnS));
7773 int segment_count = LaneCountFromFormat(vform_dst) / 4;
7778 int64_t sum = srcdst.Int(vform_dst, dstidx);
7792 srcdst.SetIntArray(vform_dst, result);