Lines Matching refs:uxtl2
1571 LogicVRegister extendedreg = uxtl2(vform, temp2, src);
3151 LogicVRegister Simulator::uxtl2(VectorFormat vform,
3497 uxtl2(vform, temp1, src1);
3498 uxtl2(vform, temp2, src2);
3520 uxtl2(vform, temp, src2);
3589 uxtl2(vform, temp1, src1);
3590 uxtl2(vform, temp2, src2);
3612 uxtl2(vform, temp, src2);
3681 uxtl2(vform, temp1, src1);
3682 uxtl2(vform, temp2, src2);
3729 uxtl2(vform, temp1, src1);
3730 uxtl2(vform, temp2, src2);