Lines Matching refs:sxtl
1519 LogicVRegister extendedreg = sxtl(vform, temp2, src);
3135 LogicVRegister Simulator::sxtl(VectorFormat vform,
3161 return sxtl(vform, dst, src, /* is_2 = */ true);
3531 sxtl(vform, temp1, src1);
3532 sxtl(vform, temp2, src2);
3555 sxtl(vform, temp, src2);
3623 sxtl(vform, temp1, src1);
3624 sxtl(vform, temp2, src2);
3647 sxtl(vform, temp, src2);
3693 sxtl(vform, temp1, src1);
3694 sxtl(vform, temp2, src2);
3741 sxtl(vform, temp1, src1);
3742 sxtl(vform, temp2, src2);
3787 sxtl(vform, temp1, src1, is_2);
3788 sxtl(vform, temp2, src2, is_2);
3829 sxtl(vform, temp1, src1, is_2);
3830 sxtl(vform, temp2, src2, is_2);
3871 sxtl(vform, temp1, src1, is_2);
3872 sxtl(vform, temp2, src2, is_2);