Lines Matching refs:src1
509 const LogicVRegister& src1,
514 int64_t sa = src1.Int(vform, i);
516 uint64_t ua = src1.Uint(vform, i);
553 const LogicVRegister& src1,
558 return cmp(vform, dst, src1, imm_reg, cond);
564 const LogicVRegister& src1,
568 uint64_t ua = src1.Uint(vform, i);
578 const LogicVRegister& src1,
585 uint64_t ua = src1.UintLeftJustified(vform, i);
608 const LogicVRegister& src1,
617 uint64_t ua = src1.UintLeftJustified(vform, i);
637 const LogicVRegister& src1,
640 uzp1(vform, temp1, src1, src2);
641 uzp2(vform, temp2, src1, src2);
651 const LogicVRegister& src1,
656 int64_t val1 = src1.Int(vform, i);
673 const LogicVRegister& src1,
678 uint64_t val1 = src1.Uint(vform, i);
694 const LogicVRegister& src1,
697 mul(vform, temp, src1, src2);
706 const LogicVRegister& src1,
709 mul(vform, temp, src1, src2);
717 const LogicVRegister& src1,
722 dst.SetUint(vform, i, src1.Uint(vform, i) * src2.Uint(vform, i));
730 const LogicVRegister& src1,
735 return mul(vform, dst, src1, dup_element(indexform, temp, src2, index));
741 const LogicVRegister& src1,
745 int64_t val1 = src1.Int(vform, i);
772 const LogicVRegister& src1,
776 uint64_t val1 = src1.Uint(vform, i);
803 const LogicVRegister& src1,
808 return mla(vform, dst, dst, src1, dup_element(indexform, temp, src2, index));
814 const LogicVRegister& src1,
819 return mls(vform, dst, dst, src1, dup_element(indexform, temp, src2, index));
824 const LogicVRegister& src1,
830 return sqdmull(vform, dst, src1, dup_element(indexform, temp, src2, index));
835 const LogicVRegister& src1,
841 return sqdmlal(vform, dst, src1, dup_element(indexform, temp, src2, index));
846 const LogicVRegister& src1,
852 return sqdmlsl(vform, dst, src1, dup_element(indexform, temp, src2, index));
857 const LogicVRegister& src1,
862 return sqdmulh(vform, dst, src1, dup_element(indexform, temp, src2, index));
868 const LogicVRegister& src1,
873 return sqrdmulh(vform, dst, src1, dup_element(indexform, temp, src2, index));
879 const LogicVRegister& src1,
884 return sqrdmlah(vform, dst, src1, dup_element(indexform, temp, src2, index));
890 const LogicVRegister& src1,
895 return sqrdmlsh(vform, dst, src1, dup_element(indexform, temp, src2, index));
917 const LogicVRegister& src1,
923 PolynomialMult(src1.Uint(vform, i),
933 const LogicVRegister& src1,
941 PolynomialMult(src1.Uint(vform_src, i),
952 const LogicVRegister& src1,
960 PolynomialMult(src1.Uint(vform_src, lane_count + i),
970 const LogicVRegister& src1,
976 uint64_t ua = src1.UintLeftJustified(vform, i);
1000 const LogicVRegister& src1,
1009 uint64_t ua = src1.UintLeftJustified(vform, i);
1029 const LogicVRegister& src1,
1033 dst.SetUint(vform, i, src1.Uint(vform, i) & src2.Uint(vform, i));
1041 const LogicVRegister& src1,
1045 dst.SetUint(vform, i, src1.Uint(vform, i) | src2.Uint(vform, i));
1053 const LogicVRegister& src1,
1057 dst.SetUint(vform, i, src1.Uint(vform, i) | ~src2.Uint(vform, i));
1065 const LogicVRegister& src1,
1069 dst.SetUint(vform, i, src1.Uint(vform, i) ^ src2.Uint(vform, i));
1077 const LogicVRegister& src1,
1081 dst.SetUint(vform, i, src1.Uint(vform, i) & ~src2.Uint(vform, i));
1106 const LogicVRegister& src1,
1112 uint64_t operand3 = src1.Uint(vform, i);
1122 const LogicVRegister& src1,
1128 uint64_t operand3 = src1.Uint(vform, i);
1139 const LogicVRegister& src1,
1145 uint64_t operand3 = src1.Uint(vform, i);
1155 const LogicVRegister& src1,
1160 int64_t src1_val = src1.Int(vform, i);
1176 const LogicVRegister& src1,
1178 return sminmax(vform, dst, src1, src2, true);
1184 const LogicVRegister& src1,
1186 return sminmax(vform, dst, src1, src2, false);
1192 const LogicVRegister& src1,
1197 const LogicVRegister* src = &src1;
1223 const LogicVRegister& src1,
1225 return sminmaxp(vform, dst, src1, src2, true);
1231 const LogicVRegister& src1,
1233 return sminmaxp(vform, dst, src1, src2, false);
1361 const LogicVRegister& src1,
1366 uint64_t src1_val = src1.Uint(vform, i);
1382 const LogicVRegister& src1,
1384 return uminmax(vform, dst, src1, src2, true);
1390 const LogicVRegister& src1,
1392 return uminmax(vform, dst, src1, src2, false);
1398 const LogicVRegister& src1,
1403 const LogicVRegister* src = &src1;
1429 const LogicVRegister& src1,
1431 return uminmaxp(vform, dst, src1, src2, true);
1437 const LogicVRegister& src1,
1439 return uminmaxp(vform, dst, src1, src2, false);
1608 const LogicVRegister& src1,
1620 result[dst_idx++] = src1.Uint(vform, i);
1637 const LogicVRegister& src1,
1643 ? src1.Uint(vform, lane)
1653 const LogicPRegister& src1,
1658 (mask & src1.GetChunk(i)) | (~mask & src2.GetChunk(i));
1894 const LogicVRegister& src1,
1904 int64_t lj_src_val = src1.IntLeftJustified(vform, i);
1919 int64_t src_val = src1.Int(vform, i);
1959 const LogicVRegister& src1,
1969 uint64_t lj_src_val = src1.UintLeftJustified(vform, i);
1976 uint64_t src_val = src1.Uint(vform, i);
2002 const LogicVRegister& src1,
2007 sshl(vform, dst, src1, temp, false);
2013 const LogicVRegister& src1,
2018 ushl(vform, dst, src1, temp, false);
2040 const LogicVRegister& src1,
2044 int64_t sa = src1.IntLeftJustified(vform, i);
2053 dst.SetUint(vform, i, src1.Int(vform, i) + src2.Uint(vform, i));
2062 const LogicVRegister& src1,
2066 uint64_t ua = src1.UintLeftJustified(vform, i);
2075 dst.SetUint(vform, i, src1.Uint(vform, i) + src2.Int(vform, i));
2297 const LogicVRegister& src1,
2302 bool src1_gt_src2 = is_signed ? (src1.Int(vform, i) > src2.Int(vform, i))
2303 : (src1.Uint(vform, i) > src2.Uint(vform, i));
2307 dst.SetUint(vform, i, src1.Uint(vform, i) - src2.Uint(vform, i));
2309 dst.SetUint(vform, i, src2.Uint(vform, i) - src1.Uint(vform, i));
2318 const LogicVRegister& src1,
2322 absdiff(vform, temp, src1, src2, true);
2330 const LogicVRegister& src1,
2334 absdiff(vform, temp, src1, src2, false);
2504 const LogicVRegister& src1,
2510 result[i] = src1.Uint(vform, i + index);
2574 const LogicVRegister& src1, // n
2601 dst.SetFloat<T>(e * 2, FPAdd(src1.Float<T>(e * 2), element1));
2602 dst.SetFloat<T>(e * 2 + 1, FPAdd(src1.Float<T>(e * 2 + 1), element3));
2610 const LogicVRegister& src1, // n
2614 fcadd<SimFloat16>(vform, dst, src1, src2, rot);
2616 fcadd<float>(vform, dst, src1, src2, rot);
2619 fcadd<double>(vform, dst, src1, src2, rot);
2627 const LogicVRegister& src1,
2649 element2 = src1.Float<T>(e * 2);
2651 element4 = src1.Float<T>(e * 2);
2655 element2 = src1.Float<T>(e * 2 + 1);
2657 element4 = src1.Float<T>(e * 2 + 1);
2661 element2 = src1.Float<T>(e * 2);
2663 element4 = src1.Float<T>(e * 2);
2667 element2 = src1.Float<T>(e * 2 + 1);
2669 element4 = src1.Float<T>(e * 2 + 1);
2688 const LogicVRegister& src1,
2693 fcmla<SimFloat16>(vform, dst, src1, src2, acc, -1, rot);
2695 fcmla<float>(vform, dst, src1, src2, acc, -1, rot);
2697 fcmla<double>(vform, dst, src1, src2, acc, -1, rot);
2705 const LogicVRegister& src1, // n
2712 fcmla<float>(vform, dst, src1, src2, dst, index, rot);
2714 fcmla<double>(vform, dst, src1, src2, dst, index, rot);
2721 const LogicVRegister& src1,
2729 uzp1(vform, src1_r, src1, zero);
2730 uzp2(vform, src1_i, src1, zero);
2760 const LogicVRegister& src1,
2770 uzp1(vform, src1_a, src1, zero);
2774 uzp2(vform, src1_a, src1, zero);
2806 const LogicVRegister& src1,
2812 return cmla(vform, dst, srca, src1, temp, rot);
2817 const LogicVRegister& src1,
2821 uint64_t value = src1.Uint(vform, i);
2850 const LogicVRegister& src1,
2853 uint64_t value = src1.Uint(vform, i);
2871 const LogicVRegister& src1,
2879 uint64_t value = src1.Uint(vform, i);
3482 const LogicVRegister& src1,
3485 uxtl(vform, temp1, src1);
3494 const LogicVRegister& src1,
3497 uxtl2(vform, temp1, src1);
3506 const LogicVRegister& src1,
3510 add(vform, dst, src1, temp);
3517 const LogicVRegister& src1,
3521 add(vform, dst, src1, temp);
3528 const LogicVRegister& src1,
3531 sxtl(vform, temp1, src1);
3540 const LogicVRegister& src1,
3543 sxtl2(vform, temp1, src1);
3552 const LogicVRegister& src1,
3556 add(vform, dst, src1, temp);
3563 const LogicVRegister& src1,
3567 add(vform, dst, src1, temp);
3574 const LogicVRegister& src1,
3577 uxtl(vform, temp1, src1);
3586 const LogicVRegister& src1,
3589 uxtl2(vform, temp1, src1);
3598 const LogicVRegister& src1,
3602 sub(vform, dst, src1, temp);
3609 const LogicVRegister& src1,
3613 sub(vform, dst, src1, temp);
3620 const LogicVRegister& src1,
3623 sxtl(vform, temp1, src1);
3632 const LogicVRegister& src1,
3635 sxtl2(vform, temp1, src1);
3644 const LogicVRegister& src1,
3648 sub(vform, dst, src1, temp);
3655 const LogicVRegister& src1,
3659 sub(vform, dst, src1, temp);
3666 const LogicVRegister& src1,
3669 uxtl(vform, temp1, src1);
3678 const LogicVRegister& src1,
3681 uxtl2(vform, temp1, src1);
3690 const LogicVRegister& src1,
3693 sxtl(vform, temp1, src1);
3702 const LogicVRegister& src1,
3705 sxtl2(vform, temp1, src1);
3714 const LogicVRegister& src1,
3717 uxtl(vform, temp1, src1);
3726 const LogicVRegister& src1,
3729 uxtl2(vform, temp1, src1);
3738 const LogicVRegister& src1,
3741 sxtl(vform, temp1, src1);
3750 const LogicVRegister& src1,
3753 sxtl2(vform, temp1, src1);
3762 const LogicVRegister& src1,
3766 uxtl(vform, temp1, src1, is_2);
3775 const LogicVRegister& src1,
3777 return umull(vform, dst, src1, src2, /* is_2 = */ true);
3783 const LogicVRegister& src1,
3787 sxtl(vform, temp1, src1, is_2);
3796 const LogicVRegister& src1,
3798 return smull(vform, dst, src1, src2, /* is_2 = */ true);
3804 const LogicVRegister& src1,
3808 uxtl(vform, temp1, src1, is_2);
3817 const LogicVRegister& src1,
3819 return umlsl(vform, dst, src1, src2, /* is_2 = */ true);
3825 const LogicVRegister& src1,
3829 sxtl(vform, temp1, src1, is_2);
3838 const LogicVRegister& src1,
3840 return smlsl(vform, dst, src1, src2, /* is_2 = */ true);
3846 const LogicVRegister& src1,
3850 uxtl(vform, temp1, src1, is_2);
3859 const LogicVRegister& src1,
3861 return umlal(vform, dst, src1, src2, /* is_2 = */ true);
3867 const LogicVRegister& src1,
3871 sxtl(vform, temp1, src1, is_2);
3880 const LogicVRegister& src1,
3882 return smlal(vform, dst, src1, src2, /* is_2 = */ true);
3888 const LogicVRegister& src1,
3892 LogicVRegister product = sqdmull(vform, temp, src1, src2, is_2);
3899 const LogicVRegister& src1,
3901 return sqdmlal(vform, dst, src1, src2, /* is_2 = */ true);
3907 const LogicVRegister& src1,
3911 LogicVRegister product = sqdmull(vform, temp, src1, src2, is_2);
3918 const LogicVRegister& src1,
3920 return sqdmlsl(vform, dst, src1, src2, /* is_2 = */ true);
3926 const LogicVRegister& src1,
3930 LogicVRegister product = smull(vform, temp, src1, src2, is_2);
3937 const LogicVRegister& src1,
3939 return sqdmull(vform, dst, src1, src2, /* is_2 = */ true);
3944 const LogicVRegister& src1,
3952 mul(vform, temp_lo, src1, src2);
3953 smulh(vform, temp_hi, src1, src2);
3971 // Saturation only occurs when src1 = src2 = minimum representable value.
3974 if ((src1.Int(vform, i) == MinIntFromFormat(vform)) &&
3988 const LogicVRegister& src1,
4002 element1 = src1.Int(quarter_vform, index);
4004 element1 = src1.Uint(quarter_vform, index);
4021 const LogicVRegister& src1,
4023 return dot(vform, dst, src1, src2, true, true);
4029 const LogicVRegister& src1,
4031 return dot(vform, dst, src1, src2, false, false);
4036 const LogicVRegister& src1,
4038 return dot(vform, dst, src1, src2, false, true);
4044 const LogicVRegister& src1,
4058 int64_t r1 = src1.Int(quarter_vform, (4 * i) + (2 * j) + 0);
4059 int64_t i1 = src1.Int(quarter_vform, (4 * i) + (2 * j) + 1);
4072 const LogicVRegister& src1,
4082 uzp1(vform, src1_a, src1, zero);
4086 uzp2(vform, src1_a, src1, zero);
4107 const LogicVRegister& src1,
4113 return sqrdcmlah(vform, dst, srca, src1, temp, rot);
4118 const LogicVRegister& src1,
4124 // (dst << (esize - 1) + src1 * src2 + 1 << (esize - 2)) >> (esize - 1)
4126 // (dst << esize + 2 * src1 * src2 + 1 << (esize - 1)) >> esize.
4144 vixl_uint128_t product = Mul64(src1.Int(vform, i), src2.Int(vform, i));
4176 const LogicVRegister& src1,
4182 // (dst << (esize - 1) + src1 * src2 + 1 << (esize - 2)) >> (esize - 1)
4184 // (dst << esize + 2 * src1 * src2 + 1 << (esize - 1)) >> esize.
4187 return sqrdmlash_d(vform, dst, src1, src2, round, sub_op);
4198 accum -= src1.Int(vform, i) * src2.Int(vform, i);
4200 accum += src1.Int(vform, i) * src2.Int(vform, i);
4218 const LogicVRegister& src1,
4221 return sqrdmlash(vform, dst, src1, src2, round, false);
4227 const LogicVRegister& src1,
4230 return sqrdmlash(vform, dst, src1, src2, round, true);
4236 const LogicVRegister& src1,
4238 return sqrdmulh(vform, dst, src1, src2, false);
4244 const LogicVRegister& src1,
4247 add(VectorFormatDoubleWidth(vform), temp, src1, src2);
4255 const LogicVRegister& src1,
4258 add(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2);
4266 const LogicVRegister& src1,
4269 add(VectorFormatDoubleWidth(vform), temp, src1, src2);
4277 const LogicVRegister& src1,
4280 add(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2);
4288 const LogicVRegister& src1,
4291 sub(VectorFormatDoubleWidth(vform), temp, src1, src2);
4299 const LogicVRegister& src1,
4302 sub(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2);
4310 const LogicVRegister& src1,
4313 sub(VectorFormatDoubleWidth(vform), temp, src1, src2);
4321 const LogicVRegister& src1,
4324 sub(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2);
4332 const LogicVRegister& src1,
4338 result[2 * i] = src1.Uint(vform, 2 * i);
4352 const LogicVRegister& src1,
4358 result[2 * i] = src1.Uint(vform, (2 * i) + 1);
4372 const LogicVRegister& src1,
4378 result[2 * i] = src1.Uint(vform, i);
4392 const LogicVRegister& src1,
4398 result[2 * i] = src1.Uint(vform, pairs + i);
4412 const LogicVRegister& src1,
4417 result[i] = src1.Uint(vform, i);
4431 const LogicVRegister& src1,
4436 result[i] = src1.Uint(vform, i);
4998 const LogicVRegister& src1, \
5002 T op1 = src1.Float<T>(i); \
5020 const LogicVRegister& src1, \
5023 FN<SimFloat16>(vform, dst, src1, src2); \
5025 FN<float>(vform, dst, src1, src2); \
5028 FN<double>(vform, dst, src1, src2); \
5038 const LogicVRegister& src1,
5041 LogicVRegister product = fmul(vform, temp, src1, src2);
5049 const LogicVRegister& src1,
5053 T op1 = -src1.Float<T>(i);
5064 const LogicVRegister& src1,
5067 frecps<SimFloat16>(vform, dst, src1, src2);
5069 frecps<float>(vform, dst, src1, src2);
5072 frecps<double>(vform, dst, src1, src2);
5081 const LogicVRegister& src1,
5085 T op1 = -src1.Float<T>(i);
5096 const LogicVRegister& src1,
5099 frsqrts<SimFloat16>(vform, dst, src1, src2);
5101 frsqrts<float>(vform, dst, src1, src2);
5104 frsqrts<double>(vform, dst, src1, src2);
5113 const LogicVRegister& src1,
5119 T op1 = src1.Float<T>(i);
5164 const LogicVRegister& src1,
5168 fcmp<SimFloat16>(vform, dst, src1, src2, cond);
5170 fcmp<float>(vform, dst, src1, src2, cond);
5173 fcmp<double>(vform, dst, src1, src2, cond);
5202 const LogicVRegister& src1,
5207 LogicVRegister abs_src1 = fabs_<SimFloat16>(vform, temp1, src1);
5211 LogicVRegister abs_src1 = fabs_<float>(vform, temp1, src1);
5216 LogicVRegister abs_src1 = fabs_<double>(vform, temp1, src1);
5228 const LogicVRegister& src1,
5232 T op1 = src1.Float<T>(i);
5245 const LogicVRegister& src1,
5248 fmla<SimFloat16>(vform, dst, srca, src1, src2);
5250 fmla<float>(vform, dst, srca, src1, src2);
5253 fmla<double>(vform, dst, srca, src1, src2);
5263 const LogicVRegister& src1,
5267 T op1 = -src1.Float<T>(i);
5280 const LogicVRegister& src1,
5283 fmls<SimFloat16>(vform, dst, srca, src1, src2);
5285 fmls<float>(vform, dst, srca, src1, src2);
5288 fmls<double>(vform, dst, srca, src1, src2);
5296 const LogicVRegister& src1,
5301 float op1 = FPToFloat(src1.Float<SimFloat16>(i), kIgnoreDefaultNaN);
5313 const LogicVRegister& src1,
5319 float op1 = FPToFloat(src1.Float<SimFloat16>(src), kIgnoreDefaultNaN);
5331 const LogicVRegister& src1,
5336 float op1 = -FPToFloat(src1.Float<SimFloat16>(i), kIgnoreDefaultNaN);
5348 const LogicVRegister& src1,
5354 float op1 = -FPToFloat(src1.Float<SimFloat16>(src), kIgnoreDefaultNaN);
5366 const LogicVRegister& src1,
5373 float op1 = FPToFloat(src1.Float<SimFloat16>(i), kIgnoreDefaultNaN);
5384 const LogicVRegister& src1,
5392 float op1 = FPToFloat(src1.Float<SimFloat16>(src), kIgnoreDefaultNaN);
5403 const LogicVRegister& src1,
5410 float op1 = -FPToFloat(src1.Float<SimFloat16>(i), kIgnoreDefaultNaN);
5421 const LogicVRegister& src1,
5429 float op1 = -FPToFloat(src1.Float<SimFloat16>(src), kIgnoreDefaultNaN);
5500 const LogicVRegister& src1,
5503 fsub(vform, temp, src1, src2);
5537 const LogicVRegister& src1, \
5540 uzp1(vform, temp1, src1, src2); \
5541 uzp2(vform, temp2, src1, src2); \
5701 const LogicVRegister& src1,
5708 fmul<SimFloat16>(vform, dst, src1, index_reg);
5711 fmul<float>(vform, dst, src1, index_reg);
5715 fmul<double>(vform, dst, src1, index_reg);
5723 const LogicVRegister& src1,
5730 fmla<SimFloat16>(vform, dst, dst, src1, index_reg);
5733 fmla<float>(vform, dst, dst, src1, index_reg);
5737 fmla<double>(vform, dst, dst, src1, index_reg);
5745 const LogicVRegister& src1,
5752 fmls<SimFloat16>(vform, dst, dst, src1, index_reg);
5755 fmls<float>(vform, dst, dst, src1, index_reg);
5759 fmls<double>(vform, dst, dst, src1, index_reg);
5767 const LogicVRegister& src1,
5774 fmulx<SimFloat16>(vform, dst, src1, index_reg);
5777 fmulx<float>(vform, dst, src1, index_reg);
5781 fmulx<double>(vform, dst, src1, index_reg);
6546 const LogicVRegister& src1,
6553 eor(vform, maybe_neg_src1, maybe_neg_src1, src1);
6555 // Multiply src1 by the modified neg_src1, which is potentially its negation.
6556 // In the case of NaNs, NaN * -NaN will return the first NaN intact, so src1,
6558 fmul(vform, dst, src1, maybe_neg_src1);
6565 const LogicVRegister& src1,
6583 uint64_t op = src1.Uint(vform, i);
6586 // the quadrant. Bit 0 controls whether src1 or 1.0 is written to dst. Bit 1
6601 const LogicVRegister& src1,
6629 fmla<T>(vform, cf, cf, src1, temp);
6637 const LogicVRegister& src1,
6697 src1,
6704 src1,
6712 src1,
6798 const LogicVRegister& src1,
6802 T src1_val = src1.Float<T>(i);
6831 const LogicVRegister& src1,
6834 fscale<SimFloat16>(vform, dst, src1, src2);
6836 fscale<float>(vform, dst, src1, src2);
6839 fscale<double>(vform, dst, src1, src2);
7002 const LogicVRegister& src1,
7019 op1 = src1.Int(vform, lane);
7027 op1 = src1.Uint(vform, lane);
7081 const LogicVRegister& src1,
7099 uint64_t value = src1.Uint(vform, lane);
7112 const LogicVRegister& src1,
7118 int64_t value = src1.Int(vform, i);
7717 const LogicVRegister& src1,
7724 uint64_t left = src1.Uint(vform, i + (top ? 1 : 0));
7740 // Multiply the 2x8 8-bit matrix in src1 by the 8x2 8-bit matrix in src2, add
7745 // src1 = ( a b c d e f g h ) src2 = ( A B )
7757 // src1 = [ p | o | n | m | l | k | j | i | h | g | f | e | d | c | b | a ]
7762 const LogicVRegister& src1,
7782 int64_t e1 = src1_signed ? src1.Int(vform_src, idx1)
7783 : src1.Uint(vform_src, idx1);
7796 // Multiply the 2x2 FP matrix in src1 by the 2x2 FP matrix in src2, add the 2x2
7801 // src1 = ( a b ) src2 = ( A B )
7807 // src1 = [ d | c | b | a ]
7813 const LogicVRegister& src1,
7822 T prod0 = FPMulNaNs(src1.Float<T>(2 * i + 0 + segoff),
7824 T prod1 = FPMulNaNs(src1.Float<T>(2 * i + 1 + segoff),
7843 const LogicVRegister& src1,
7846 fmatmul<float>(vform, dst, src1, src2);
7849 fmatmul<double>(vform, dst, src1, src2);