Lines Matching refs:src
87 double Simulator::FixedToDouble(int64_t src, int fbits, FPRounding round) {
88 if (src >= 0) {
89 return UFixedToDouble(src, fbits, round);
90 } else if (src == INT64_MIN) {
91 return -UFixedToDouble(src, fbits, round);
93 return -UFixedToDouble(-src, fbits, round);
98 double Simulator::UFixedToDouble(uint64_t src, int fbits, FPRounding round) {
101 if (src == 0) {
107 const int highest_significant_bit = 63 - CountLeadingZeros(src);
110 return FPRoundToDouble(0, exponent, src, round);
114 float Simulator::FixedToFloat(int64_t src, int fbits, FPRounding round) {
115 if (src >= 0) {
116 return UFixedToFloat(src, fbits, round);
117 } else if (src == INT64_MIN) {
118 return -UFixedToFloat(src, fbits, round);
120 return -UFixedToFloat(-src, fbits, round);
125 float Simulator::UFixedToFloat(uint64_t src, int fbits, FPRounding round) {
128 if (src == 0) {
134 const int highest_significant_bit = 63 - CountLeadingZeros(src);
137 return FPRoundToFloat(0, exponent, src, round);
141 SimFloat16 Simulator::FixedToFloat16(int64_t src, int fbits, FPRounding round) {
142 if (src >= 0) {
143 return UFixedToFloat16(src, fbits, round);
144 } else if (src == INT64_MIN) {
145 return -UFixedToFloat16(src, fbits, round);
147 return -UFixedToFloat16(-src, fbits, round);
152 SimFloat16 Simulator::UFixedToFloat16(uint64_t src,
157 if (src == 0) {
163 const int highest_significant_bit = 63 - CountLeadingZeros(src);
166 return FPRoundToFloat16(0, exponent, src, round);
395 void Simulator::st1(VectorFormat vform, LogicVRegister src, uint64_t addr) {
397 StoreLane(src, vform, i, addr);
404 LogicVRegister src,
407 StoreLane(src, vform, index, addr);
412 LogicVRegister src,
418 StoreLane(src, vform, i, addr);
427 LogicVRegister src,
432 StoreLane(src, vform, index, addr);
438 LogicVRegister src,
446 StoreLane(src, vform, i, addr);
457 LogicVRegister src,
463 StoreLane(src, vform, index, addr);
470 LogicVRegister src,
480 StoreLane(src, vform, i, addr);
493 LogicVRegister src,
500 StoreLane(src, vform, index, addr);
1089 const LogicVRegister& src,
1094 result[i] = src.Uint(vform, i) & ~imm;
1197 const LogicVRegister* src = &src1;
1200 int64_t first_val = src->Int(vform, i);
1201 int64_t second_val = src->Int(vform, i + 1);
1211 src = &src2;
1239 const LogicVRegister& src) {
1242 uint64_t dst_val = src.Uint(kFormat2D, 0) + src.Uint(kFormat2D, 1);
1251 const LogicVRegister& src) {
1258 dst_val += src.Int(vform, i);
1269 const LogicVRegister& src) {
1275 dst_val += src.Int(vform, i);
1286 const LogicVRegister& src) {
1292 dst_val += src.Uint(vform, i);
1304 const LogicVRegister& src,
1310 int64_t src_val = src.Int(vform, i);
1325 const LogicVRegister& src) {
1326 sminmaxv(vform, dst, GetPTrue(), src, true);
1333 const LogicVRegister& src) {
1334 sminmaxv(vform, dst, GetPTrue(), src, false);
1342 const LogicVRegister& src) {
1344 sminmaxv(vform, dst, pg, src, true);
1352 const LogicVRegister& src) {
1354 sminmaxv(vform, dst, pg, src, false);
1403 const LogicVRegister* src = &src1;
1406 uint64_t first_val = src->Uint(vform, i);
1407 uint64_t second_val = src->Uint(vform, i + 1);
1417 src = &src2;
1446 const LogicVRegister& src,
1452 uint64_t src_val = src.Uint(vform, i);
1467 const LogicVRegister& src) {
1468 uminmaxv(vform, dst, GetPTrue(), src, true);
1475 const LogicVRegister& src) {
1476 uminmaxv(vform, dst, GetPTrue(), src, false);
1484 const LogicVRegister& src) {
1486 uminmaxv(vform, dst, pg, src, true);
1494 const LogicVRegister& src) {
1496 uminmaxv(vform, dst, pg, src, false);
1503 const LogicVRegister& src,
1508 return ushl(vform, dst, src, shiftreg);
1514 const LogicVRegister& src,
1519 LogicVRegister extendedreg = sxtl(vform, temp2, src);
1526 const LogicVRegister& src,
1531 LogicVRegister extendedreg = sxtl2(vform, temp2, src);
1538 const LogicVRegister& src) {
1540 return sshll(vform, dst, src, shift);
1546 const LogicVRegister& src) {
1548 return sshll2(vform, dst, src, shift);
1554 const LogicVRegister& src,
1559 LogicVRegister extendedreg = uxtl(vform, temp2, src);
1566 const LogicVRegister& src,
1571 LogicVRegister extendedreg = uxtl2(vform, temp2, src);
1577 const LogicVRegister& src,
1586 return std::make_pair(last_active >= 0, src.Uint(vform, index));
1592 const LogicVRegister& src) {
1596 dst.SetUint(vform, j++, src.Uint(vform, i));
1667 const LogicVRegister& src,
1672 uint64_t src_lane = src.Uint(vform, i);
1684 const LogicVRegister& src,
1689 return sshl(vform, dst, src, shiftreg).SignedSaturate(vform);
1695 const LogicVRegister& src,
1700 return ushl(vform, dst, src, shiftreg).UnsignedSaturate(vform);
1706 const LogicVRegister& src,
1711 return sshl(vform, dst, src, shiftreg).UnsignedSaturate(vform);
1717 const LogicVRegister& src,
1724 uint64_t src_lane = src.Uint(vform, i);
1743 const LogicVRegister& src,
1748 return ushl(vform, dst, src, shiftreg);
1754 const LogicVRegister& src,
1759 return sshl(vform, dst, src, shiftreg);
1765 const LogicVRegister& src,
1768 LogicVRegister shifted_reg = sshr(vform, temp, src, shift);
1775 const LogicVRegister& src,
1778 LogicVRegister shifted_reg = ushr(vform, temp, src, shift);
1785 const LogicVRegister& src,
1788 LogicVRegister shifted_reg = sshr(vform, temp, src, shift).Round(vform);
1795 const LogicVRegister& src,
1798 LogicVRegister shifted_reg = ushr(vform, temp, src, shift).Round(vform);
1805 const LogicVRegister& src) {
1813 result[i] = CountLeadingSignBits(src.Int(vform, i), lane_size_in_bits);
1826 const LogicVRegister& src) {
1834 result[i] = CountLeadingZeros(src.Uint(vform, i), lane_size_in_bits);
1847 const LogicVRegister& src) {
1850 uint64_t value = (src.Uint(vform, i) == 0) ? 1 : 0;
1859 const LogicVRegister& src) {
1867 result[i] = CountSetBits(src.Uint(vform, i), lane_size_in_bits);
2024 const LogicVRegister& src) {
2028 int64_t sa = src.Int(vform, i);
2084 const LogicVRegister& src) {
2088 int64_t sa = src.Int(vform, i);
2105 const LogicVRegister& src) {
2111 result &= src.Uint(vform, i);
2124 const LogicVRegister& src) {
2130 result ^= src.Uint(vform, i);
2143 const LogicVRegister& src) {
2149 result |= src.Uint(vform, i);
2162 const LogicVRegister& src) {
2172 result += src.Int(vform, i);
2184 const LogicVRegister& src) {
2190 result += src.Uint(vform, i);
2202 const LogicVRegister& src,
2213 LogicVRegister src_copy = src;
2269 const LogicVRegister& src) {
2270 return extractnarrow(vform, dst, true, src, true);
2276 const LogicVRegister& src) {
2277 return extractnarrow(vform, dst, true, src, true).SignedSaturate(vform);
2283 const LogicVRegister& src) {
2284 return extractnarrow(vform, dst, false, src, true).UnsignedSaturate(vform);
2290 const LogicVRegister& src) {
2291 return extractnarrow(vform, dst, false, src, false).UnsignedSaturate(vform);
2342 const LogicVRegister& src) {
2345 dst.SetUint(vform, i, ~src.Uint(vform, i));
2353 const LogicVRegister& src) {
2360 value = src.Uint(vform, i);
2379 const LogicVRegister& src) {
2383 uint64_t t = src.Uint(vform, i);
2384 dst.SetUint(vform, i, src.Uint(vform, lane_count - i - 1));
2393 const LogicVRegister& src,
2401 result[i + lanes_per_loop - 1 - j] = src.Uint(vform, i + j);
2414 const LogicVRegister& src) {
2415 return rev_byte(vform, dst, src, 2);
2421 const LogicVRegister& src) {
2422 return rev_byte(vform, dst, src, 4);
2428 const LogicVRegister& src) {
2429 return rev_byte(vform, dst, src, 8);
2434 const LogicVRegister& src,
2444 result[i] = static_cast<uint64_t>(src.Int(vformsrc, 2 * i) +
2445 src.Int(vformsrc, 2 * i + 1));
2447 result[i] = src.Uint(vformsrc, 2 * i) + src.Uint(vformsrc, 2 * i + 1);
2465 const LogicVRegister& src) {
2466 return addlp(vform, dst, src, true, false);
2472 const LogicVRegister& src) {
2473 return addlp(vform, dst, src, false, false);
2479 const LogicVRegister& src) {
2480 return addlp(vform, dst, src, true, true);
2486 const LogicVRegister& src) {
2487 return addlp(vform, dst, src, false, true);
2492 const LogicVRegister& src,
2496 uint64_t value = src.Uint(vform, i);
2524 const LogicVRegister& src,
2529 return ext(kFormatVnB, dst, src, src, index);
2537 const LogicVRegister& src) {
2542 result = FPAdd(result, src.Float<T>(i));
2554 const LogicVRegister& src) {
2557 fadda<SimFloat16>(vform, acc, pg, src);
2560 fadda<float>(vform, acc, pg, src);
2563 fadda<double>(vform, acc, pg, src);
2898 const LogicVRegister& src,
2906 d[i] = src.Uint(kFormatVnD, (src_index * count) + i);
2914 uint64_t value = src.Uint(vform, src_index);
2925 const LogicVRegister& src,
2939 uint64_t value = src.Uint(vform, j + src_index);
2973 const LogicVRegister& src,
2975 dst.SetUint(vform, dst_index, src.Uint(vform, src_index));
3018 const LogicVRegister& src) {
3021 dst.SetUint(vform, lane, src.Uint(vform, lane));
3027 LogicPRegister Simulator::mov(LogicPRegister dst, const LogicPRegister& src) {
3029 if (dst.Aliases(src)) return dst;
3032 dst.SetChunk(i, src.GetChunk(i));
3041 const LogicVRegister& src) {
3042 return sel(vform, dst, pg, src, dst);
3048 const LogicVRegister& src) {
3051 return sel(vform, dst, pg, src, zero);
3056 const LogicVRegister& src,
3060 dst.SetUint(vform, i, src.Uint(vform, i));
3067 const LogicPRegister& src) {
3068 return sel(dst, pg, src, dst);
3073 const LogicPRegister& src) {
3075 return sel(dst, pg, src, pfalse(all_false));
3104 const LogicVRegister& src,
3109 result[i] = src.Uint(vform, i) | imm;
3121 const LogicVRegister& src,
3129 dst.SetUint(vform, i, src.Uint(vform_half, src_offset + i));
3137 const LogicVRegister& src,
3145 dst.SetInt(vform, i, src.Int(vform_half, src_offset + i));
3153 const LogicVRegister& src) {
3154 return uxtl(vform, dst, src, /* is_2 = */ true);
3160 const LogicVRegister& src) {
3161 return sxtl(vform, dst, src, /* is_2 = */ true);
3167 const LogicVRegister& src,
3174 dst.SetInt(vform, i, src.Uint(vform, i) & mask);
3182 const LogicVRegister& src,
3189 ExtractSignedBitfield64(from_size_in_bits - 1, 0, src.Uint(vform, i));
3198 const LogicVRegister& src,
3203 LogicVRegister shifted_src = ushr(vform_src, temp, src, shift);
3210 const LogicVRegister& src,
3215 LogicVRegister shifted_src = ushr(vformsrc, temp, src, shift);
3222 const LogicVRegister& src,
3227 LogicVRegister shifted_src = ushr(vformsrc, temp, src, shift).Round(vformsrc);
3234 const LogicVRegister& src,
3239 LogicVRegister shifted_src = ushr(vformsrc, temp, src, shift).Round(vformsrc);
3354 const LogicVRegister& src,
3356 return shrn(vform, dst, src, shift).UnsignedSaturate(vform);
3362 const LogicVRegister& src,
3364 return shrn2(vform, dst, src, shift).UnsignedSaturate(vform);
3370 const LogicVRegister& src,
3372 return rshrn(vform, dst, src, shift).UnsignedSaturate(vform);
3378 const LogicVRegister& src,
3380 return rshrn2(vform, dst, src, shift).UnsignedSaturate(vform);
3386 const LogicVRegister& src,
3391 LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift);
3398 const LogicVRegister& src,
3403 LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift);
3410 const LogicVRegister& src,
3415 LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift).Round(vformsrc);
3422 const LogicVRegister& src,
3427 LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift).Round(vformsrc);
3434 const LogicVRegister& src,
3439 LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift);
3446 const LogicVRegister& src,
3451 LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift);
3458 const LogicVRegister& src,
3463 LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift).Round(vformsrc);
3470 const LogicVRegister& src,
3475 LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift).Round(vformsrc);
4449 const LogicVRegister& src) {
4462 result[i] = src.Uint(vform, i / 2);
4463 result[i + 1] = src.Uint(vform, (lane_count / 2) + (i / 2));
5181 const LogicVRegister& src,
5187 fcmp<SimFloat16>(vform, dst, src, zero_reg, cond);
5190 fcmp<float>(vform, dst, src, zero_reg, cond);
5194 fcmp<double>(vform, dst, src, zero_reg, cond);
5318 int src = i + LaneCountFromFormat(vform);
5319 float op1 = FPToFloat(src1.Float<SimFloat16>(src), kIgnoreDefaultNaN);
5320 float op2 = FPToFloat(src2.Float<SimFloat16>(src), kIgnoreDefaultNaN);
5353 int src = i + LaneCountFromFormat(vform);
5354 float op1 = -FPToFloat(src1.Float<SimFloat16>(src), kIgnoreDefaultNaN);
5355 float op2 = FPToFloat(src2.Float<SimFloat16>(src), kIgnoreDefaultNaN);
5391 int src = i + LaneCountFromFormat(vform);
5392 float op1 = FPToFloat(src1.Float<SimFloat16>(src), kIgnoreDefaultNaN);
5428 int src = i + LaneCountFromFormat(vform);
5429 float op1 = -FPToFloat(src1.Float<SimFloat16>(src), kIgnoreDefaultNaN);
5441 const LogicVRegister& src) {
5444 T op = src.Float<T>(i);
5454 const LogicVRegister& src) {
5456 fneg<SimFloat16>(vform, dst, src);
5458 fneg<float>(vform, dst, src);
5461 fneg<double>(vform, dst, src);
5470 const LogicVRegister& src) {
5473 T op = src.Float<T>(i);
5485 const LogicVRegister& src) {
5487 fabs_<SimFloat16>(vform, dst, src);
5489 fabs_<float>(vform, dst, src);
5492 fabs_<double>(vform, dst, src);
5511 const LogicVRegister& src) {
5515 SimFloat16 result = FPSqrt(src.Float<SimFloat16>(i));
5520 float result = FPSqrt(src.Float<float>(i));
5526 double result = FPSqrt(src.Float<double>(i));
5551 const LogicVRegister& src) { \
5553 SimFloat16 result(OP(SimFloat16(RawbitsToFloat16(src.Uint(vform, 0))), \
5554 SimFloat16(RawbitsToFloat16(src.Uint(vform, 1))))); \
5557 float result = OP(src.Float<float>(0), src.Float<float>(1)); \
5561 double result = OP(src.Float<double>(0), src.Float<double>(1)); \
5573 const LogicVRegister& src,
5582 ? src.Float<T>(i)
5601 const LogicVRegister& src,
5610 src,
5614 return FPPairedAcrossHelper<float>(vform, dst, src, fn32, inactive_value);
5619 src,
5627 const LogicVRegister& src) {
5630 src,
5639 const LogicVRegister& src) {
5645 src,
5655 const LogicVRegister& src) {
5661 src,
5671 const LogicVRegister& src) {
5676 src,
5686 const LogicVRegister& src) {
5691 src,
5789 const LogicVRegister& src,
5797 SimFloat16 input = src.Float<SimFloat16>(i);
5806 float input = src.Float<float>(i);
5817 double input = src.Float<double>(i);
5832 const LogicVRegister& src) {
5843 src.Uint(vform, i));
5861 const LogicVRegister& src,
5872 src.Uint(vform, i));
5897 const LogicVRegister& src,
5906 src,
5916 const LogicVRegister& src,
5927 src.Uint(vform, i));
5952 const LogicVRegister& src,
5961 src,
5968 const LogicVRegister& src) {
5973 FPToFloat(RawbitsToFloat16(src.Float<uint16_t>(i)),
5979 dst.SetFloat(i, FPToDouble(src.Float<float>(i), ReadDN()));
5988 const LogicVRegister& src) {
5995 src.Float<uint16_t>(i + lane_count)),
6001 dst.SetFloat(i, FPToDouble(src.Float<float>(i + lane_count), ReadDN()));
6010 const LogicVRegister& src) {
6012 LogicVRegister srctmp = mov(kFormat2D, tmp, src);
6033 const LogicVRegister& src) {
6039 FPToFloat16(src.Float<float>(i), FPTieEven, ReadDN())));
6045 FPToFloat(src.Float<double>(i), FPTieEven, ReadDN()));
6054 const LogicVRegister& src) {
6056 LogicVRegister srctmp = mov(kFormat2D, tmp, src);
6059 mov(kFormatVnB, tmp, src);
6075 const LogicVRegister& src) {
6080 FPToFloat(src.Float<double>(i), FPRoundOdd, ReadDN()));
6184 const LogicVRegister& src) {
6188 SimFloat16 input = src.Float<SimFloat16>(i);
6193 float input = src.Float<float>(i);
6199 double input = src.Float<double>(i);
6328 const LogicVRegister& src,
6333 SimFloat16 input = src.Float<SimFloat16>(i);
6338 float input = src.Float<float>(i);
6344 double input = src.Float<double>(i);
6354 const LogicVRegister& src) {
6360 operand = src.Uint(vform, i);
6387 const LogicVRegister& src) {
6393 operand = src.Uint(vform, i);
6413 const LogicPRegister& src) {
6416 mov(dst, src);
6434 const LogicPRegister& src) {
6435 int next = GetLastActive(vform, src) + 1;
6450 const LogicVRegister& src) {
6453 T op = src.Float<T>(i);
6486 const LogicVRegister& src) {
6488 frecpx<SimFloat16>(vform, dst, src);
6490 frecpx<float>(vform, dst, src);
6493 frecpx<double>(vform, dst, src);
6500 const LogicVRegister& src) {
6505 op = FPToDouble(src.Float<SimFloat16>(i), kIgnoreDefaultNaN);
6508 op = src.Float<float>(i);
6511 op = src.Float<double>(i);
6722 const LogicVRegister& src) {
6787 uint64_t op = src.Uint(vform, i);
6849 const LogicVRegister& src,
6861 src.Uint(vform, i));
6890 const LogicVRegister& src,
6898 src,
6908 const LogicVRegister& src,
6920 src.Uint(vform, i));
6949 const LogicVRegister& src,
6957 src,
6964 const LogicVRegister& src,
6975 result[i] = src.Int(vform_half, i + src_start_lane);
6985 result[i] = src.Uint(vform_half, i + src_start_lane);
7701 const LogicVRegister& src) {
7704 return uzp2(vform, dst, src, zero);
7709 const LogicVRegister& src) {
7712 return uzp1(vform, dst, src, zero);