Lines Matching refs:pg
1303 const LogicPRegister& pg,
1308 if (!pg.IsActive(vform, i)) continue;
1341 const LogicPRegister& pg,
1344 sminmaxv(vform, dst, pg, src, true);
1351 const LogicPRegister& pg,
1354 sminmaxv(vform, dst, pg, src, false);
1445 const LogicPRegister& pg,
1450 if (!pg.IsActive(vform, i)) continue;
1483 const LogicPRegister& pg,
1486 uminmaxv(vform, dst, pg, src, true);
1493 const LogicPRegister& pg,
1496 uminmaxv(vform, dst, pg, src, false);
1576 const LogicPRegister& pg,
1582 int last_active = GetLastActive(vform, pg);
1591 const LogicPRegister& pg,
1595 if (pg.IsActive(vform, i)) {
1607 const LogicPRegister& pg,
1611 int first_active = GetFirstActive(vform, pg);
1612 int last_active = GetLastActive(vform, pg);
1636 const SimPRegister& pg,
1642 uint64_t lane_value = pg.GetBit(lane * p_reg_bits_per_lane)
1652 const LogicPRegister& pg,
1656 LogicPRegister::ChunkType mask = pg.GetChunk(i);
2104 const LogicPRegister& pg,
2109 if (!pg.IsActive(vform, i)) continue;
2123 const LogicPRegister& pg,
2128 if (!pg.IsActive(vform, i)) continue;
2142 const LogicPRegister& pg,
2147 if (!pg.IsActive(vform, i)) continue;
2161 const LogicPRegister& pg,
2167 if (!pg.IsActive(vform, i)) continue;
2183 const LogicPRegister& pg,
2188 if (!pg.IsActive(vform, i)) continue;
2536 const LogicPRegister& pg,
2540 if (!pg.IsActive(vform, i)) continue;
2553 const LogicPRegister& pg,
2557 fadda<SimFloat16>(vform, acc, pg, src);
2560 fadda<float>(vform, acc, pg, src);
2563 fadda<double>(vform, acc, pg, src);
2870 const LogicPRegister& pg,
2885 if (pg.IsActive(vform, j) &&
3040 const SimPRegister& pg,
3042 return sel(vform, dst, pg, src, dst);
3047 const SimPRegister& pg,
3051 return sel(vform, dst, pg, src, zero);
3066 const LogicPRegister& pg,
3068 return sel(dst, pg, src, dst);
3072 const LogicPRegister& pg,
3075 return sel(dst, pg, src, pfalse(all_false));
5831 const LogicPRegister& pg,
5839 if (!pg.IsActive(vform, i)) continue;
5860 const LogicPRegister& pg,
5868 if (!pg.IsActive(vform, i)) continue;
5915 const LogicPRegister& pg,
5923 if (!pg.IsActive(vform, i)) continue;
6412 const LogicPRegister& pg,
6414 int first_pg = GetFirstActive(kFormatVnB, pg);
6433 const LogicPRegister& pg,
6437 if (pg.IsActive(vform, next)) break;
6848 const LogicPRegister& pg,
6857 if (!pg.IsActive(vform, i)) continue;
6907 const LogicPRegister& pg,
6916 if (!pg.IsActive(vform, i)) continue;
7240 const LogicPRegister& pg,
7273 if (!pg.IsActive(vform, i)) continue;
7293 pg,
7302 const LogicPRegister& pg,
7330 if (!pg.IsActive(vform, i)) {
7351 pg,
7360 const LogicPRegister& pg,
7364 if (pg.IsActive(kFormatVnB, i)) {
7374 const LogicPRegister& pg,
7378 if (pg.IsActive(kFormatVnB, i)) {
7388 const LogicPRegister& pg,
7390 if (!IsLastActive(kFormatVnB, pg, pn)) {
7397 const LogicPRegister& pg,
7400 bool last_active = IsLastActive(kFormatVnB, pg, pn);
7404 if (pg.IsActive(kFormatVnB, i)) {
7415 const LogicPRegister& pg,
7418 bool last_active = IsLastActive(kFormatVnB, pg, pn);
7422 if (pg.IsActive(kFormatVnB, i)) {
7433 const LogicPRegister& pg,
7457 if (pg.IsActive(vform, i)) {
7491 // Note that this behaviour takes precedence over pg's zeroing predication.
7509 // Log accessed lanes that are active in both pg and ffr. PrintZStructAccess
7512 SVEPredicateLogicalHelper(AND_p_p_pp_z, mask, pg, ffr);
7549 const LogicPRegister& pg) const {
7551 if (pg.IsActive(vform, i)) return i;
7557 const LogicPRegister& pg) const {
7559 if (pg.IsActive(vform, i)) return i;
7565 const LogicPRegister& pg) const {
7568 count += pg.IsActive(vform, i) ? 1 : 0;
7574 const LogicPRegister& pg,
7578 count += (pg.IsActive(vform, i) && pn.IsActive(vform, i)) ? 1 : 0;