Lines Matching refs:op2
900 uint64_t op2,
904 VIXL_ASSERT(IsUintN(lane_size_in_bits, op2));
908 result = result ^ (op2 << i);
4475 T Simulator::FPAdd(T op1, T op2) {
4476 T result = FPProcessNaNs(op1, op2);
4481 if (IsInf(op1) && IsInf(op2) && (op1 != op2)) {
4487 return op1 + op2;
4493 T Simulator::FPSub(T op1, T op2) {
4495 VIXL_ASSERT(!IsNaN(op1) && !IsNaN(op2));
4497 if (IsInf(op1) && IsInf(op2) && (op1 == op2)) {
4503 return op1 - op2;
4508 T Simulator::FPMulNaNs(T op1, T op2) {
4509 T result = FPProcessNaNs(op1, op2);
4510 return IsNaN(result) ? result : FPMul(op1, op2);
4514 T Simulator::FPMul(T op1, T op2) {
4516 VIXL_ASSERT(!IsNaN(op1) && !IsNaN(op2));
4518 if ((IsInf(op1) && (op2 == 0.0)) || (IsInf(op2) && (op1 == 0.0))) {
4524 return op1 * op2;
4530 T Simulator::FPMulx(T op1, T op2) {
4531 if ((IsInf(op1) && (op2 == 0.0)) || (IsInf(op2) && (op1 == 0.0))) {
4534 return copysign(1.0, op1) * copysign(1.0, op2) * two;
4536 return FPMul(op1, op2);
4541 T Simulator::FPMulAdd(T a, T op1, T op2) {
4542 T result = FPProcessNaNs3(a, op1, op2);
4545 T sign_prod = copysign(1.0, op1) * copysign(1.0, op2);
4546 bool isinf_prod = IsInf(op1) || IsInf(op2);
4548 (IsInf(op1) && (op2 == 0.0)) || // inf * 0.0
4549 (IsInf(op2) && (op1 == 0.0)) || // 0.0 * inf
4569 // exact 0.0 results is positive unless both a and op1 * op2 are negative.
4570 if (((op1 == 0.0) || (op2 == 0.0)) && (a == 0.0)) {
4574 result = FusedMultiplyAdd(op1, op2, a);
4578 // 0.0, the sign of the result is the sign of op1 * op2 before rounding.
4586 template float Simulator::FPMulAdd(float a, float op1, float op2);
4588 template double Simulator::FPMulAdd(double a, double op1, double op2);
4591 T Simulator::FPDiv(T op1, T op2) {
4593 VIXL_ASSERT(!IsNaN(op1) && !IsNaN(op2));
4595 if ((IsInf(op1) && IsInf(op2)) || ((op1 == 0.0) && (op2 == 0.0))) {
4600 if (op2 == 0.0) {
4604 double op2_sign = copysign(1.0, op2);
4610 return op1 / op2;
4683 T Simulator::FPRecipStepFused(T op1, T op2) {
4685 if ((IsInf(op1) && (op2 == 0.0)) || ((op1 == 0.0) && (IsInf(op2)))) {
4687 } else if (IsInf(op1) || IsInf(op2)) {
4689 return ((op1 >= 0.0) == (op2 >= 0.0)) ? kFP64PositiveInfinity
4692 return FusedMultiplyAdd(op1, op2, two);
4711 T Simulator::FPRSqrtStepFused(T op1, T op2) {
4715 if ((IsInf(op1) && (op2 == 0.0)) || ((op1 == 0.0) && (IsInf(op2)))) {
4717 } else if (IsInf(op1) || IsInf(op2)) {
4719 return ((op1 >= 0.0) == (op2 >= 0.0)) ? kFP64PositiveInfinity
4726 return FusedMultiplyAdd(op1 / two, op2, one_point_five);
4727 } else if (IsNormal(op2 / two)) {
4728 return FusedMultiplyAdd(op1, op2 / two, one_point_five);
5003 T op2 = src2.Float<T>(i); \
5006 result = FPProcessNaNs(op1, op2); \
5008 result = OP(op1, op2); \
5011 result = OP(op1, op2); \
5054 T op2 = src2.Float<T>(i);
5055 T result = FPProcessNaNs(op1, op2);
5056 dst.SetFloat(vform, i, IsNaN(result) ? result : FPRecipStepFused(op1, op2));
5086 T op2 = src2.Float<T>(i);
5087 T result = FPProcessNaNs(op1, op2);
5088 dst.SetFloat(vform, i, IsNaN(result) ? result : FPRSqrtStepFused(op1, op2));
5120 T op2 = src2.Float<T>(i);
5121 bool unordered = IsNaN(FPProcessNaNs(op1, op2));
5125 result = (op1 == op2);
5128 result = (op1 >= op2);
5131 result = (op1 > op2);
5134 result = (op1 <= op2);
5137 result = (op1 < op2);
5140 result = (op1 != op2);
5233 T op2 = src2.Float<T>(i);
5235 T result = FPMulAdd(acc, op1, op2);
5268 T op2 = src2.Float<T>(i);
5270 T result = FPMulAdd(acc, op1, op2);
5302 float op2 = FPToFloat(src2.Float<SimFloat16>(i), kIgnoreDefaultNaN);
5304 float result = FPMulAdd(acc, op1, op2);
5320 float op2 = FPToFloat(src2.Float<SimFloat16>(src), kIgnoreDefaultNaN);
5322 float result = FPMulAdd(acc, op1, op2);
5337 float op2 = FPToFloat(src2.Float<SimFloat16>(i), kIgnoreDefaultNaN);
5339 float result = FPMulAdd(acc, op1, op2);
5355 float op2 = FPToFloat(src2.Float<SimFloat16>(src), kIgnoreDefaultNaN);
5357 float result = FPMulAdd(acc, op1, op2);
5371 float op2 = FPToFloat(src2.Float<SimFloat16>(index), kIgnoreDefaultNaN);
5375 float result = FPMulAdd(acc, op1, op2);
5389 float op2 = FPToFloat(src2.Float<SimFloat16>(index), kIgnoreDefaultNaN);
5394 float result = FPMulAdd(acc, op1, op2);
5408 float op2 = FPToFloat(src2.Float<SimFloat16>(index), kIgnoreDefaultNaN);
5412 float result = FPMulAdd(acc, op1, op2);
5426 float op2 = FPToFloat(src2.Float<SimFloat16>(index), kIgnoreDefaultNaN);
5431 float result = FPMulAdd(acc, op1, op2);
7010 int64_t op2 = 0xbadbeef;
7020 op2 = is_wide_elements ? src2.Int(kFormatVnD, d_lane)
7028 op2 = is_wide_elements ? src2.Uint(kFormatVnD, d_lane)
7037 result = (op1 == op2);
7040 result = (op1 != op2);
7043 result = (op1 >= op2);
7046 result = (op1 > op2);
7049 result = (op1 <= op2);
7052 result = (op1 < op2);
7055 result = (static_cast<uint64_t>(op1) >= static_cast<uint64_t>(op2));
7058 result = (static_cast<uint64_t>(op1) > static_cast<uint64_t>(op2));
7061 result = (static_cast<uint64_t>(op1) <= static_cast<uint64_t>(op2));
7064 result = (static_cast<uint64_t>(op1) < static_cast<uint64_t>(op2));
7143 uint64_t op2 = zm.Uint(vform, i);
7147 result = op1 & op2;
7150 result = op1 & ~op2;
7153 result = op1 ^ op2;
7156 result = op1 | op2;
7173 LogicPRegister::ChunkType op2 = pm.GetChunk(i);
7178 result = op1 & op2;
7182 result = op1 & ~op2;
7186 result = op1 ^ op2;
7190 result = ~(op1 & op2);
7194 result = ~(op1 | op2);
7198 result = op1 | ~op2;
7202 result = op1 | op2;