Lines Matching refs:dst
185 void Simulator::ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr) {
186 dst.ClearForWrite(vform);
188 LoadLane(dst, vform, i, addr);
195 LogicVRegister dst,
198 LoadLane(dst, vform, index, addr);
204 LogicVRegister dst,
208 dst.ClearForWrite(vform);
211 LoadIntToLane(dst, vform, unpack_size, i, addr);
213 LoadUintToLane(dst, vform, unpack_size, i, addr);
219 void Simulator::ld1r(VectorFormat vform, LogicVRegister dst, uint64_t addr) {
220 ld1r(vform, vform, dst, addr);
508 LogicVRegister dst,
512 dst.ClearForWrite(vform);
545 dst.SetUint(vform, i, result ? MaxUintFromFormat(vform) : 0);
547 return dst;
552 LogicVRegister dst,
558 return cmp(vform, dst, src1, imm_reg, cond);
563 LogicVRegister dst,
566 dst.ClearForWrite(vform);
570 dst.SetUint(vform, i, ((ua & ub) != 0) ? MaxUintFromFormat(vform) : 0);
572 return dst;
577 LogicVRegister dst,
581 dst.ClearForWrite(vform);
589 dst.SetUnsignedSat(i, true);
599 dst.SetSignedSat(i, pos_a);
601 dst.SetInt(vform, i, ur >> (64 - lane_size));
603 return dst;
607 LogicVRegister dst,
612 dst.ClearForWrite(vform);
620 dst.SetUnsignedSat(i, true);
627 dst.SetSignedSat(i, true);
630 dst.SetInt(vform, i, ur >> (64 - lane_size));
632 return dst;
636 LogicVRegister dst,
642 add(vform, dst, temp1, temp2);
644 interleave_top_bottom(vform, dst, dst);
646 return dst;
650 LogicVRegister dst,
665 dst.SetInt(vform, i, quotient);
668 return dst;
672 LogicVRegister dst,
684 dst.SetUint(vform, i, quotient);
687 return dst;
692 LogicVRegister dst,
698 add(vform, dst, srca, temp);
699 return dst;
704 LogicVRegister dst,
710 sub(vform, dst, srca, temp);
711 return dst;
716 LogicVRegister dst,
719 dst.ClearForWrite(vform);
722 dst.SetUint(vform, i, src1.Uint(vform, i) * src2.Uint(vform, i));
724 return dst;
729 LogicVRegister dst,
735 return mul(vform, dst, src1, dup_element(indexform, temp, src2, index));
740 LogicVRegister dst,
764 dst.SetInt(vform, i, dst_val);
766 return dst;
771 LogicVRegister dst,
795 dst.SetUint(vform, i, dst_val);
797 return dst;
802 LogicVRegister dst,
808 return mla(vform, dst, dst, src1, dup_element(indexform, temp, src2, index));
813 LogicVRegister dst,
819 return mls(vform, dst, dst, src1, dup_element(indexform, temp, src2, index));
823 LogicVRegister dst,
830 return sqdmull(vform, dst, src1, dup_element(indexform, temp, src2, index));
834 LogicVRegister dst,
841 return sqdmlal(vform, dst, src1, dup_element(indexform, temp, src2, index));
845 LogicVRegister dst,
852 return sqdmlsl(vform, dst, src1, dup_element(indexform, temp, src2, index));
856 LogicVRegister dst,
862 return sqdmulh(vform, dst, src1, dup_element(indexform, temp, src2, index));
867 LogicVRegister dst,
873 return sqrdmulh(vform, dst, src1, dup_element(indexform, temp, src2, index));
878 LogicVRegister dst,
884 return sqrdmlah(vform, dst, src1, dup_element(indexform, temp, src2, index));
889 LogicVRegister dst,
895 return sqrdmlsh(vform, dst, src1, dup_element(indexform, temp, src2, index));
916 LogicVRegister dst,
919 dst.ClearForWrite(vform);
921 dst.SetUint(vform,
927 return dst;
932 LogicVRegister dst,
935 dst.ClearForWrite(vform);
939 dst.SetUint(vform,
946 return dst;
951 LogicVRegister dst,
955 dst.ClearForWrite(vform);
958 dst.SetUint(vform,
964 return dst;
969 LogicVRegister dst,
973 dst.ClearForWrite(vform);
980 dst.SetUnsignedSat(i, false);
990 dst.SetSignedSat(i, pos_a);
993 dst.SetInt(vform, i, ur >> (64 - lane_size));
995 return dst;
999 LogicVRegister dst,
1004 dst.ClearForWrite(vform);
1012 dst.SetUnsignedSat(i, false);
1019 dst.SetSignedSat(i, false);
1022 dst.SetInt(vform, i, ur >> (64 - lane_size));
1024 return dst;
1028 LogicVRegister dst,
1031 dst.ClearForWrite(vform);
1033 dst.SetUint(vform, i, src1.Uint(vform, i) & src2.Uint(vform, i));
1035 return dst;
1040 LogicVRegister dst,
1043 dst.ClearForWrite(vform);
1045 dst.SetUint(vform, i, src1.Uint(vform, i) | src2.Uint(vform, i));
1047 return dst;
1052 LogicVRegister dst,
1055 dst.ClearForWrite(vform);
1057 dst.SetUint(vform, i, src1.Uint(vform, i) | ~src2.Uint(vform, i));
1059 return dst;
1064 LogicVRegister dst,
1067 dst.ClearForWrite(vform);
1069 dst.SetUint(vform, i, src1.Uint(vform, i) ^ src2.Uint(vform, i));
1071 return dst;
1076 LogicVRegister dst,
1079 dst.ClearForWrite(vform);
1081 dst.SetUint(vform, i, src1.Uint(vform, i) & ~src2.Uint(vform, i));
1083 return dst;
1088 LogicVRegister dst,
1096 dst.ClearForWrite(vform);
1098 dst.SetUint(vform, i, result[i]);
1100 return dst;
1105 LogicVRegister dst,
1108 dst.ClearForWrite(vform);
1110 uint64_t operand1 = dst.Uint(vform, i);
1114 dst.SetUint(vform, i, result);
1116 return dst;
1121 LogicVRegister dst,
1124 dst.ClearForWrite(vform);
1126 uint64_t operand1 = dst.Uint(vform, i);
1130 dst.SetUint(vform, i, result);
1132 return dst;
1137 LogicVRegister dst,
1141 dst.ClearForWrite(vform);
1147 dst.SetUint(vform, i, result);
1149 return dst;
1154 LogicVRegister dst,
1158 dst.ClearForWrite(vform);
1168 dst.SetInt(vform, i, dst_val);
1170 return dst;
1175 LogicVRegister dst,
1178 return sminmax(vform, dst, src1, src2, true);
1183 LogicVRegister dst,
1186 return sminmax(vform, dst, src1, src2, false);
1191 LogicVRegister dst,
1213 dst.SetIntArray(vform, result);
1215 interleave_top_bottom(vform, dst, dst);
1217 return dst;
1222 LogicVRegister dst,
1225 return sminmaxp(vform, dst, src1, src2, true);
1230 LogicVRegister dst,
1233 return sminmaxp(vform, dst, src1, src2, false);
1238 LogicVRegister dst,
1243 dst.ClearForWrite(vform);
1244 dst.SetUint(vform, 0, dst_val);
1245 return dst;
1250 LogicVRegister dst,
1261 dst.ClearForWrite(vform_dst);
1262 dst.SetInt(vform_dst, 0, dst_val);
1263 return dst;
1268 LogicVRegister dst,
1278 dst.ClearForWrite(vform_dst);
1279 dst.SetInt(vform_dst, 0, dst_val);
1280 return dst;
1285 LogicVRegister dst,
1295 dst.ClearForWrite(vform_dst);
1296 dst.SetUint(vform_dst, 0, dst_val);
1297 return dst;
1302 LogicVRegister dst,
1317 dst.ClearForWrite(ScalarFormatFromFormat(vform));
1318 dst.SetInt(vform, 0, dst_val);
1319 return dst;
1324 LogicVRegister dst,
1326 sminmaxv(vform, dst, GetPTrue(), src, true);
1327 return dst;
1332 LogicVRegister dst,
1334 sminmaxv(vform, dst, GetPTrue(), src, false);
1335 return dst;
1340 LogicVRegister dst,
1344 sminmaxv(vform, dst, pg, src, true);
1345 return dst;
1350 LogicVRegister dst,
1354 sminmaxv(vform, dst, pg, src, false);
1355 return dst;
1360 LogicVRegister dst,
1364 dst.ClearForWrite(vform);
1374 dst.SetUint(vform, i, dst_val);
1376 return dst;
1381 LogicVRegister dst,
1384 return uminmax(vform, dst, src1, src2, true);
1389 LogicVRegister dst,
1392 return uminmax(vform, dst, src1, src2, false);
1397 LogicVRegister dst,
1419 dst.SetUintArray(vform, result);
1421 interleave_top_bottom(vform, dst, dst);
1423 return dst;
1428 LogicVRegister dst,
1431 return uminmaxp(vform, dst, src1, src2, true);
1436 LogicVRegister dst,
1439 return uminmaxp(vform, dst, src1, src2, false);
1444 LogicVRegister dst,
1459 dst.ClearForWrite(ScalarFormatFromFormat(vform));
1460 dst.SetUint(vform, 0, dst_val);
1461 return dst;
1466 LogicVRegister dst,
1468 uminmaxv(vform, dst, GetPTrue(), src, true);
1469 return dst;
1474 LogicVRegister dst,
1476 uminmaxv(vform, dst, GetPTrue(), src, false);
1477 return dst;
1482 LogicVRegister dst,
1486 uminmaxv(vform, dst, pg, src, true);
1487 return dst;
1492 LogicVRegister dst,
1496 uminmaxv(vform, dst, pg, src, false);
1497 return dst;
1502 LogicVRegister dst,
1508 return ushl(vform, dst, src, shiftreg);
1513 LogicVRegister dst,
1520 return sshl(vform, dst, extendedreg, shiftreg);
1525 LogicVRegister dst,
1532 return sshl(vform, dst, extendedreg, shiftreg);
1537 LogicVRegister dst,
1540 return sshll(vform, dst, src, shift);
1545 LogicVRegister dst,
1548 return sshll2(vform, dst, src, shift);
1553 LogicVRegister dst,
1560 return ushl(vform, dst, extendedreg, shiftreg);
1565 LogicVRegister dst,
1572 return ushl(vform, dst, extendedreg, shiftreg);
1590 LogicVRegister dst,
1596 dst.SetUint(vform, j++, src.Uint(vform, i));
1600 dst.SetUint(vform, j, 0);
1602 return dst;
1606 LogicVRegister dst,
1629 dst.SetUintArray(vform, result);
1631 return dst;
1635 LogicVRegister dst,
1645 dst.SetUint(vform, lane, lane_value);
1647 return dst;
1651 LogicPRegister Simulator::sel(LogicPRegister dst,
1655 for (int i = 0; i < dst.GetChunkCount(); i++) {
1659 dst.SetChunk(i, result);
1661 return dst;
1666 LogicVRegister dst,
1669 dst.ClearForWrite(vform);
1673 uint64_t dst_lane = dst.Uint(vform, i);
1676 dst.SetUint(vform, i, (dst_lane & ~mask) | shifted);
1678 return dst;
1683 LogicVRegister dst,
1689 return sshl(vform, dst, src, shiftreg).SignedSaturate(vform);
1694 LogicVRegister dst,
1700 return ushl(vform, dst, src, shiftreg).UnsignedSaturate(vform);
1705 LogicVRegister dst,
1711 return sshl(vform, dst, src, shiftreg).UnsignedSaturate(vform);
1716 LogicVRegister dst,
1719 dst.ClearForWrite(vform);
1725 uint64_t dst_lane = dst.Uint(vform, i);
1735 dst.SetUint(vform, i, (dst_lane & ~mask) | shifted);
1737 return dst;
1742 LogicVRegister dst,
1748 return ushl(vform, dst, src, shiftreg);
1753 LogicVRegister dst,
1759 return sshl(vform, dst, src, shiftreg);
1764 LogicVRegister dst,
1769 return add(vform, dst, dst, shifted_reg);
1774 LogicVRegister dst,
1779 return add(vform, dst, dst, shifted_reg);
1784 LogicVRegister dst,
1789 return add(vform, dst, dst, shifted_reg);
1794 LogicVRegister dst,
1799 return add(vform, dst, dst, shifted_reg);
1804 LogicVRegister dst,
1816 dst.ClearForWrite(vform);
1818 dst.SetUint(vform, i, result[i]);
1820 return dst;
1825 LogicVRegister dst,
1837 dst.ClearForWrite(vform);
1839 dst.SetUint(vform, i, result[i]);
1841 return dst;
1846 LogicVRegister dst,
1848 dst.ClearForWrite(vform);
1851 dst.SetUint(vform, i, value);
1853 return dst;
1858 LogicVRegister dst,
1870 dst.ClearForWrite(vform);
1872 dst.SetUint(vform, i, result[i]);
1874 return dst;
1893 LogicVRegister dst,
1897 dst.ClearForWrite(vform);
1908 dst.SetSignedSat(i, lj_src_val >= 0);
1913 dst.SetUnsignedSat(i, false);
1916 dst.SetUnsignedSat(i, true);
1922 dst.SetInt(vform, i, 0);
1924 dst.SetRounding(i, src_is_negative);
1925 dst.SetInt(vform, i, src_is_negative ? -1 : 0);
1938 dst.SetRounding(i, true);
1950 dst.SetUint(vform, i, usrc_val);
1953 return dst;
1958 LogicVRegister dst,
1962 dst.ClearForWrite(vform);
1973 dst.SetUnsignedSat(i, true);
1978 dst.SetUint(vform, i, 0);
1983 dst.SetRounding(i, true);
1994 dst.SetUint(vform, i, src_val);
1997 return dst;
2001 LogicVRegister dst,
2007 sshl(vform, dst, src1, temp, false);
2008 return dst;
2012 LogicVRegister dst,
2018 ushl(vform, dst, src1, temp, false);
2019 return dst;
2023 LogicVRegister dst,
2025 dst.ClearForWrite(vform);
2030 dst.SetSignedSat(i, true);
2032 dst.SetInt(vform, i, (sa == INT64_MIN) ? sa : -sa);
2034 return dst;
2039 LogicVRegister dst,
2042 dst.ClearForWrite(vform);
2051 dst.SetInt(vform, i, MaxIntFromFormat(vform));
2053 dst.SetUint(vform, i, src1.Int(vform, i) + src2.Uint(vform, i));
2056 return dst;
2061 LogicVRegister dst,
2064 dst.ClearForWrite(vform);
2071 dst.SetUint(vform, i, MaxUintFromFormat(vform)); // Positive saturation.
2073 dst.SetUint(vform, i, 0); // Negative saturation.
2075 dst.SetUint(vform, i, src1.Uint(vform, i) + src2.Int(vform, i));
2078 return dst;
2083 LogicVRegister dst,
2085 dst.ClearForWrite(vform);
2090 dst.SetSignedSat(i, true);
2093 dst.SetInt(vform, i, (sa == INT64_MIN) ? sa : -sa);
2095 dst.SetInt(vform, i, sa);
2098 return dst;
2103 LogicVRegister dst,
2115 dst.ClearForWrite(vform_dst);
2116 dst.SetUint(vform_dst, 0, result);
2117 return dst;
2122 LogicVRegister dst,
2134 dst.ClearForWrite(vform_dst);
2135 dst.SetUint(vform_dst, 0, result);
2136 return dst;
2141 LogicVRegister dst,
2153 dst.ClearForWrite(vform_dst);
2154 dst.SetUint(vform_dst, 0, result);
2155 return dst;
2160 LogicVRegister dst,
2175 dst.ClearForWrite(kFormatD);
2176 dst.SetInt(kFormatD, 0, result);
2177 return dst;
2182 LogicVRegister dst,
2193 dst.ClearForWrite(kFormatD);
2194 dst.SetUint(kFormatD, 0, result);
2195 return dst;
2200 LogicVRegister dst,
2228 dst.SetSignedSat(offset + i, true);
2230 dst.SetSignedSat(offset + i, false);
2236 dst.SetUnsignedSat(offset + i, true);
2238 dst.SetUnsignedSat(offset + i, false);
2242 dst.SetUnsignedSat(offset + i, true);
2254 dst.SetInt(dstform, offset + i, result);
2256 dst.SetUint(dstform, offset + i, result);
2261 dst.ClearForWrite(dstform);
2263 return dst;
2268 LogicVRegister dst,
2270 return extractnarrow(vform, dst, true, src, true);
2275 LogicVRegister dst,
2277 return extractnarrow(vform, dst, true, src, true).SignedSaturate(vform);
2282 LogicVRegister dst,
2284 return extractnarrow(vform, dst, false, src, true).UnsignedSaturate(vform);
2289 LogicVRegister dst,
2291 return extractnarrow(vform, dst, false, src, false).UnsignedSaturate(vform);
2296 LogicVRegister dst,
2300 dst.ClearForWrite(vform);
2307 dst.SetUint(vform, i, src1.Uint(vform, i) - src2.Uint(vform, i));
2309 dst.SetUint(vform, i, src2.Uint(vform, i) - src1.Uint(vform, i));
2312 return dst;
2317 LogicVRegister dst,
2321 dst.ClearForWrite(vform);
2323 add(vform, dst, dst, temp);
2324 return dst;
2329 LogicVRegister dst,
2333 dst.ClearForWrite(vform);
2335 add(vform, dst, dst, temp);
2336 return dst;
2341 LogicVRegister dst,
2343 dst.ClearForWrite(vform);
2345 dst.SetUint(vform, i, ~src.Uint(vform, i));
2347 return dst;
2352 LogicVRegister dst,
2369 dst.ClearForWrite(vform);
2371 dst.SetUint(vform, i, result[i]);
2373 return dst;
2378 LogicVRegister dst,
2384 dst.SetUint(vform, i, src.Uint(vform, lane_count - i - 1));
2385 dst.SetUint(vform, lane_count - i - 1, t);
2387 return dst;
2392 LogicVRegister dst,
2404 dst.ClearForWrite(vform);
2406 dst.SetUint(vform, i, result[i]);
2408 return dst;
2413 LogicVRegister dst,
2415 return rev_byte(vform, dst, src, 2);
2420 LogicVRegister dst,
2422 return rev_byte(vform, dst, src, 4);
2427 LogicVRegister dst,
2429 return rev_byte(vform, dst, src, 8);
2433 LogicVRegister dst,
2451 dst.ClearForWrite(vform);
2454 result[i] += dst.Uint(vform, i);
2456 dst.SetUint(vform, i, result[i]);
2459 return dst;
2464 LogicVRegister dst,
2466 return addlp(vform, dst, src, true, false);
2471 LogicVRegister dst,
2473 return addlp(vform, dst, src, false, false);
2478 LogicVRegister dst,
2480 return addlp(vform, dst, src, true, true);
2485 LogicVRegister dst,
2487 return addlp(vform, dst, src, false, true);
2491 LogicVRegister dst,
2497 dst.SetUint(vform, i, RotateRight(value, rotation, width));
2499 return dst;
2503 LogicVRegister dst,
2515 dst.ClearForWrite(vform);
2517 dst.SetUint(vform, i, result[i]);
2519 return dst;
2523 LogicVRegister dst,
2529 return ext(kFormatVnB, dst, src, src, index);
2573 LogicVRegister dst, // d
2598 return dst; // prevents "element(n) may be unintialized" errors
2600 dst.ClearForWrite(vform);
2601 dst.SetFloat<T>(e * 2, FPAdd(src1.Float<T>(e * 2), element1));
2602 dst.SetFloat<T>(e * 2 + 1, FPAdd(src1.Float<T>(e * 2 + 1), element3));
2604 return dst;
2609 LogicVRegister dst, // d
2614 fcadd<SimFloat16>(vform, dst, src1, src2, rot);
2616 fcadd<float>(vform, dst, src1, src2, rot);
2619 fcadd<double>(vform, dst, src1, src2, rot);
2621 return dst;
2626 LogicVRegister dst,
2673 return dst; // prevents "element(n) may be unintialized" errors
2675 dst.ClearForWrite(vform);
2676 dst.SetFloat<T>(vform,
2679 dst.SetFloat<T>(vform,
2683 return dst;
2687 LogicVRegister dst,
2693 fcmla<SimFloat16>(vform, dst, src1, src2, acc, -1, rot);
2695 fcmla<float>(vform, dst, src1, src2, acc, -1, rot);
2697 fcmla<double>(vform, dst, src1, src2, acc, -1, rot);
2699 return dst;
2704 LogicVRegister dst, // d
2712 fcmla<float>(vform, dst, src1, src2, dst, index, rot);
2714 fcmla<double>(vform, dst, src1, src2, dst, index, rot);
2716 return dst;
2720 LogicVRegister dst,
2753 zip1(vform, dst, src1_r, src1_i);
2754 return dst;
2758 LogicVRegister dst,
2799 zip1(vform, dst, srca_r, srca_i);
2800 return dst;
2804 LogicVRegister dst,
2812 return cmla(vform, dst, srca, src1, temp, rot);
2816 LogicVRegister dst,
2843 dst.SetUint(vform, i, result_low);
2845 return dst;
2849 LogicVRegister dst,
2863 dst.SetUint(vform, i, result);
2865 return dst;
2869 LogicVRegister dst,
2892 dst.SetUintArray(vform, result);
2893 return dst;
2897 LogicVRegister dst,
2908 dst.Clear();
2910 dst.SetUint(kFormatVnD, i, d[i % count]);
2915 dst.ClearForWrite(vform);
2917 dst.SetUint(vform, i, value);
2920 return dst;
2924 LogicVRegister dst,
2937 dst.ClearForWrite(vform);
2941 dst.SetUint(vform, j + i, value);
2944 return dst;
2949 LogicVRegister dst,
2952 dst,
2958 LogicVRegister dst,
2962 dst.ClearForWrite(vform);
2964 dst.SetUint(vform, i, value);
2966 return dst;
2971 LogicVRegister dst,
2975 dst.SetUint(vform, dst_index, src.Uint(vform, src_index));
2976 return dst;
2981 LogicVRegister dst,
2985 dst.SetUint(vform, dst_index, value);
2986 return dst;
2991 LogicVRegister dst,
2997 dst.SetUint(vform, i, value);
3000 return dst;
3005 LogicVRegister dst,
3009 dst.SetUint(vform, i, dst.Uint(vform, i - 1));
3011 dst.SetUint(vform, 0, imm);
3012 return dst;
3017 LogicVRegister dst,
3019 dst.ClearForWrite(vform);
3021 dst.SetUint(vform, lane, src.Uint(vform, lane));
3023 return dst;
3027 LogicPRegister Simulator::mov(LogicPRegister dst, const LogicPRegister& src) {
3029 if (dst.Aliases(src)) return dst;
3031 for (int i = 0; i < dst.GetChunkCount(); i++) {
3032 dst.SetChunk(i, src.GetChunk(i));
3034 return dst;
3039 LogicVRegister dst,
3042 return sel(vform, dst, pg, src, dst);
3046 LogicVRegister dst,
3051 return sel(vform, dst, pg, src, zero);
3055 LogicVRegister dst,
3060 dst.SetUint(vform, i, src.Uint(vform, i));
3062 return dst;
3065 LogicPRegister Simulator::mov_merging(LogicPRegister dst,
3068 return sel(dst, pg, src, dst);
3071 LogicPRegister Simulator::mov_zeroing(LogicPRegister dst,
3075 return sel(dst, pg, src, pfalse(all_false));
3079 LogicVRegister dst,
3082 dst.ClearForWrite(vform);
3084 dst.SetUint(vform, i, imm);
3086 return dst;
3091 LogicVRegister dst,
3094 dst.ClearForWrite(vform);
3096 dst.SetUint(vform, i, ~imm);
3098 return dst;
3103 LogicVRegister dst,
3111 dst.ClearForWrite(vform);
3113 dst.SetUint(vform, i, result[i]);
3115 return dst;
3120 LogicVRegister dst,
3127 dst.ClearForWrite(vform);
3129 dst.SetUint(vform, i, src.Uint(vform_half, src_offset + i));
3131 return dst;
3136 LogicVRegister dst,
3143 dst.ClearForWrite(vform);
3145 dst.SetInt(vform, i, src.Int(vform_half, src_offset + i));
3147 return dst;
3152 LogicVRegister dst,
3154 return uxtl(vform, dst, src, /* is_2 = */ true);
3159 LogicVRegister dst,
3161 return sxtl(vform, dst, src, /* is_2 = */ true);
3166 LogicVRegister dst,
3172 dst.ClearForWrite(vform);
3174 dst.SetInt(vform, i, src.Uint(vform, i) & mask);
3176 return dst;
3181 LogicVRegister dst,
3186 dst.ClearForWrite(vform);
3190 dst.SetInt(vform, i, value);
3192 return dst;
3197 LogicVRegister dst,
3204 return extractnarrow(vform_dst, dst, false, shifted_src, false);
3209 LogicVRegister dst,
3216 return extractnarrow(vformdst, dst, false, shifted_src, false);
3221 LogicVRegister dst,
3228 return extractnarrow(vformdst, dst, false, shifted_src, false);
3233 LogicVRegister dst,
3240 return extractnarrow(vformdst, dst, false, shifted_src, false);
3244 LogicVRegister dst,
3269 result[i] = zero_out_of_bounds ? 0 : dst.Uint(vform, i);
3272 dst.SetUintArray(vform, result);
3273 return dst;
3277 LogicVRegister dst,
3280 return Table(vform, dst, ind, true, &tab);
3285 LogicVRegister dst,
3289 return Table(vform, dst, ind, true, &tab, &tab2);
3294 LogicVRegister dst,
3299 return Table(vform, dst, ind, true, &tab, &tab2, &tab3);
3304 LogicVRegister dst,
3310 return Table(vform, dst, ind, true, &tab, &tab2, &tab3, &tab4);
3315 LogicVRegister dst,
3318 return Table(vform, dst, ind, false, &tab);
3323 LogicVRegister dst,
3327 return Table(vform, dst, ind, false, &tab, &tab2);
3332 LogicVRegister dst,
3337 return Table(vform, dst, ind, false, &tab, &tab2, &tab3);
3342 LogicVRegister dst,
3348 return Table(vform, dst, ind, false, &tab, &tab2, &tab3, &tab4);
3353 LogicVRegister dst,
3356 return shrn(vform, dst, src, shift).UnsignedSaturate(vform);
3361 LogicVRegister dst,
3364 return shrn2(vform, dst, src, shift).UnsignedSaturate(vform);
3369 LogicVRegister dst,
3372 return rshrn(vform, dst, src, shift).UnsignedSaturate(vform);
3377 LogicVRegister dst,
3380 return rshrn2(vform, dst, src, shift).UnsignedSaturate(vform);
3385 LogicVRegister dst,
3392 return sqxtn(vformdst, dst, shifted_src);
3397 LogicVRegister dst,
3404 return sqxtn(vformdst, dst, shifted_src);
3409 LogicVRegister dst,
3416 return sqxtn(vformdst, dst, shifted_src);
3421 LogicVRegister dst,
3428 return sqxtn(vformdst, dst, shifted_src);
3433 LogicVRegister dst,
3440 return sqxtun(vformdst, dst, shifted_src);
3445 LogicVRegister dst,
3452 return sqxtun(vformdst, dst, shifted_src);
3457 LogicVRegister dst,
3464 return sqxtun(vformdst, dst, shifted_src);
3469 LogicVRegister dst,
3476 return sqxtun(vformdst, dst, shifted_src);
3481 LogicVRegister dst,
3487 add(vform, dst, temp1, temp2);
3488 return dst;
3493 LogicVRegister dst,
3499 add(vform, dst, temp1, temp2);
3500 return dst;
3505 LogicVRegister dst,
3510 add(vform, dst, src1, temp);
3511 return dst;
3516 LogicVRegister dst,
3521 add(vform, dst, src1, temp);
3522 return dst;
3527 LogicVRegister dst,
3533 add(vform, dst, temp1, temp2);
3534 return dst;
3539 LogicVRegister dst,
3545 add(vform, dst, temp1, temp2);
3546 return dst;
3551 LogicVRegister dst,
3556 add(vform, dst, src1, temp);
3557 return dst;
3562 LogicVRegister dst,
3567 add(vform, dst, src1, temp);
3568 return dst;
3573 LogicVRegister dst,
3579 sub(vform, dst, temp1, temp2);
3580 return dst;
3585 LogicVRegister dst,
3591 sub(vform, dst, temp1, temp2);
3592 return dst;
3597 LogicVRegister dst,
3602 sub(vform, dst, src1, temp);
3603 return dst;
3608 LogicVRegister dst,
3613 sub(vform, dst, src1, temp);
3614 return dst;
3619 LogicVRegister dst,
3625 sub(vform, dst, temp1, temp2);
3626 return dst;
3631 LogicVRegister dst,
3637 sub(vform, dst, temp1, temp2);
3638 return dst;
3643 LogicVRegister dst,
3648 sub(vform, dst, src1, temp);
3649 return dst;
3654 LogicVRegister dst,
3659 sub(vform, dst, src1, temp);
3660 return dst;
3665 LogicVRegister dst,
3671 uaba(vform, dst, temp1, temp2);
3672 return dst;
3677 LogicVRegister dst,
3683 uaba(vform, dst, temp1, temp2);
3684 return dst;
3689 LogicVRegister dst,
3695 saba(vform, dst, temp1, temp2);
3696 return dst;
3701 LogicVRegister dst,
3707 saba(vform, dst, temp1, temp2);
3708 return dst;
3713 LogicVRegister dst,
3719 absdiff(vform, dst, temp1, temp2, false);
3720 return dst;
3725 LogicVRegister dst,
3731 absdiff(vform, dst, temp1, temp2, false);
3732 return dst;
3737 LogicVRegister dst,
3743 absdiff(vform, dst, temp1, temp2, true);
3744 return dst;
3749 LogicVRegister dst,
3755 absdiff(vform, dst, temp1, temp2, true);
3756 return dst;
3761 LogicVRegister dst,
3768 mul(vform, dst, temp1, temp2);
3769 return dst;
3774 LogicVRegister dst,
3777 return umull(vform, dst, src1, src2, /* is_2 = */ true);
3782 LogicVRegister dst,
3789 mul(vform, dst, temp1, temp2);
3790 return dst;
3795 LogicVRegister dst,
3798 return smull(vform, dst, src1, src2, /* is_2 = */ true);
3803 LogicVRegister dst,
3810 mls(vform, dst, dst, temp1, temp2);
3811 return dst;
3816 LogicVRegister dst,
3819 return umlsl(vform, dst, src1, src2, /* is_2 = */ true);
3824 LogicVRegister dst,
3831 mls(vform, dst, dst, temp1, temp2);
3832 return dst;
3837 LogicVRegister dst,
3840 return smlsl(vform, dst, src1, src2, /* is_2 = */ true);
3845 LogicVRegister dst,
3852 mla(vform, dst, dst, temp1, temp2);
3853 return dst;
3858 LogicVRegister dst,
3861 return umlal(vform, dst, src1, src2, /* is_2 = */ true);
3866 LogicVRegister dst,
3873 mla(vform, dst, dst, temp1, temp2);
3874 return dst;
3879 LogicVRegister dst,
3882 return smlal(vform, dst, src1, src2, /* is_2 = */ true);
3887 LogicVRegister dst,
3893 return add(vform, dst, dst, product).SignedSaturate(vform);
3898 LogicVRegister dst,
3901 return sqdmlal(vform, dst, src1, src2, /* is_2 = */ true);
3906 LogicVRegister dst,
3912 return sub(vform, dst, dst, product).SignedSaturate(vform);
3917 LogicVRegister dst,
3920 return sqdmlsl(vform, dst, src1, src2, /* is_2 = */ true);
3925 LogicVRegister dst,
3931 return add(vform, dst, product, product).SignedSaturate(vform);
3936 LogicVRegister dst,
3939 return sqdmull(vform, dst, src1, src2, /* is_2 = */ true);
3943 LogicVRegister dst,
3969 dst.ClearForWrite(vform);
3978 dst.SetInt(vform, i, MaxIntFromFormat(vform));
3981 mov_merging(vform, dst, not_sat, temp_hi);
3982 return dst;
3987 LogicVRegister dst,
3995 dst.ClearForWrite(vform);
4013 dst.SetUint(vform, e, result + dst.Uint(vform, e));
4015 return dst;
4020 LogicVRegister dst,
4023 return dot(vform, dst, src1, src2, true, true);
4028 LogicVRegister dst,
4031 return dot(vform, dst, src1, src2, false, false);
4035 LogicVRegister dst,
4038 return dot(vform, dst, src1, src2, false, true);
4042 LogicVRegister dst,
4064 dst.SetInt(vform, i, result);
4066 return dst;
4070 LogicVRegister dst,
4100 zip1(vform, dst, srca_r, srca_i);
4101 return dst;
4105 LogicVRegister dst,
4113 return sqrdcmlah(vform, dst, srca, src1, temp, rot);
4117 LogicVRegister dst,
4124 // (dst << (esize - 1) + src1 * src2 + 1 << (esize - 2)) >> (esize - 1)
4126 // (dst << esize + 2 * src1 * src2 + 1 << (esize - 1)) >> esize.
4138 dst.ClearForWrite(vform);
4141 accum.first = dst.Int(vform, i) >> 1;
4142 accum.second = dst.Int(vform, i) << (esize - 1);
4168 dst.SetInt(vform, i, accum.second);
4171 return dst;
4175 LogicVRegister dst,
4182 // (dst << (esize - 1) + src1 * src2 + 1 << (esize - 2)) >> (esize - 1)
4184 // (dst << esize + 2 * src1 * src2 + 1 << (esize - 1)) >> esize.
4187 return sqrdmlash_d(vform, dst, src1, src2, round, sub_op);
4194 dst.ClearForWrite(vform);
4196 accum = dst.Int(vform, i) << (esize - 1);
4210 dst.SetInt(vform, i, accum);
4212 return dst;
4217 LogicVRegister dst,
4221 return sqrdmlash(vform, dst, src1, src2, round, false);
4226 LogicVRegister dst,
4230 return sqrdmlash(vform, dst, src1, src2, round, true);
4235 LogicVRegister dst,
4238 return sqrdmulh(vform, dst, src1, src2, false);
4243 LogicVRegister dst,
4248 shrn(vform, dst, temp, LaneSizeInBitsFromFormat(vform));
4249 return dst;
4254 LogicVRegister dst,
4259 shrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform));
4260 return dst;
4265 LogicVRegister dst,
4270 rshrn(vform, dst, temp, LaneSizeInBitsFromFormat(vform));
4271 return dst;
4276 LogicVRegister dst,
4281 rshrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform));
4282 return dst;
4287 LogicVRegister dst,
4292 shrn(vform, dst, temp, LaneSizeInBitsFromFormat(vform));
4293 return dst;
4298 LogicVRegister dst,
4303 shrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform));
4304 return dst;
4309 LogicVRegister dst,
4314 rshrn(vform, dst, temp, LaneSizeInBitsFromFormat(vform));
4315 return dst;
4320 LogicVRegister dst,
4325 rshrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform));
4326 return dst;
4331 LogicVRegister dst,
4342 dst.ClearForWrite(vform);
4344 dst.SetUint(vform, i, result[i]);
4346 return dst;
4351 LogicVRegister dst,
4362 dst.ClearForWrite(vform);
4364 dst.SetUint(vform, i, result[i]);
4366 return dst;
4371 LogicVRegister dst,
4382 dst.ClearForWrite(vform);
4384 dst.SetUint(vform, i, result[i]);
4386 return dst;
4391 LogicVRegister dst,
4402 dst.ClearForWrite(vform);
4404 dst.SetUint(vform, i, result[i]);
4406 return dst;
4411 LogicVRegister dst,
4421 dst.ClearForWrite(vform);
4423 dst.SetUint(vform, i, result[2 * i]);
4425 return dst;
4430 LogicVRegister dst,
4440 dst.ClearForWrite(vform);
4442 dst.SetUint(vform, i, result[(2 * i) + 1]);
4444 return dst;
4448 LogicVRegister dst,
4465 dst.SetUintArray(vform, result);
4466 return dst;
4997 LogicVRegister dst, \
5000 dst.ClearForWrite(vform); \
5013 dst.SetFloat(vform, i, result); \
5015 return dst; \
5019 LogicVRegister dst, \
5023 FN<SimFloat16>(vform, dst, src1, src2); \
5025 FN<float>(vform, dst, src1, src2); \
5028 FN<double>(vform, dst, src1, src2); \
5030 return dst; \
5037 LogicVRegister dst,
5042 return fneg(vform, dst, product);
5048 LogicVRegister dst,
5051 dst.ClearForWrite(vform);
5056 dst.SetFloat(vform, i, IsNaN(result) ? result : FPRecipStepFused(op1, op2));
5058 return dst;
5063 LogicVRegister dst,
5067 frecps<SimFloat16>(vform, dst, src1, src2);
5069 frecps<float>(vform, dst, src1, src2);
5072 frecps<double>(vform, dst, src1, src2);
5074 return dst;
5080 LogicVRegister dst,
5083 dst.ClearForWrite(vform);
5088 dst.SetFloat(vform, i, IsNaN(result) ? result : FPRSqrtStepFused(op1, op2));
5090 return dst;
5095 LogicVRegister dst,
5099 frsqrts<SimFloat16>(vform, dst, src1, src2);
5101 frsqrts<float>(vform, dst, src1, src2);
5104 frsqrts<double>(vform, dst, src1, src2);
5106 return dst;
5112 LogicVRegister dst,
5116 dst.ClearForWrite(vform);
5156 dst.SetUint(vform, i, result ? MaxUintFromFormat(vform) : 0);
5158 return dst;
5163 LogicVRegister dst,
5168 fcmp<SimFloat16>(vform, dst, src1, src2, cond);
5170 fcmp<float>(vform, dst, src1, src2, cond);
5173 fcmp<double>(vform, dst, src1, src2, cond);
5175 return dst;
5180 LogicVRegister dst,
5187 fcmp<SimFloat16>(vform, dst, src, zero_reg, cond);
5190 fcmp<float>(vform, dst, src, zero_reg, cond);
5194 fcmp<double>(vform, dst, src, zero_reg, cond);
5196 return dst;
5201 LogicVRegister dst,
5209 fcmp<SimFloat16>(vform, dst, abs_src1, abs_src2, cond);
5213 fcmp<float>(vform, dst, abs_src1, abs_src2, cond);
5218 fcmp<double>(vform, dst, abs_src1, abs_src2, cond);
5220 return dst;
5226 LogicVRegister dst,
5230 dst.ClearForWrite(vform);
5236 dst.SetFloat(vform, i, result);
5238 return dst;
5243 LogicVRegister dst,
5248 fmla<SimFloat16>(vform, dst, srca, src1, src2);
5250 fmla<float>(vform, dst, srca, src1, src2);
5253 fmla<double>(vform, dst, srca, src1, src2);
5255 return dst;
5261 LogicVRegister dst,
5265 dst.ClearForWrite(vform);
5271 dst.SetFloat(i, result);
5273 return dst;
5278 LogicVRegister dst,
5283 fmls<SimFloat16>(vform, dst, srca, src1, src2);
5285 fmls<float>(vform, dst, srca, src1, src2);
5288 fmls<double>(vform, dst, srca, src1, src2);
5290 return dst;
5295 LogicVRegister dst,
5299 dst.ClearForWrite(vform);
5303 float acc = dst.Float<float>(i);
5305 dst.SetFloat(i, result);
5307 return dst;
5312 LogicVRegister dst,
5316 dst.ClearForWrite(vform);
5321 float acc = dst.Float<float>(i);
5323 dst.SetFloat(i, result);
5325 return dst;
5330 LogicVRegister dst,
5334 dst.ClearForWrite(vform);
5338 float acc = dst.Float<float>(i);
5340 dst.SetFloat(i, result);
5342 return dst;
5347 LogicVRegister dst,
5351 dst.ClearForWrite(vform);
5356 float acc = dst.Float<float>(i);
5358 dst.SetFloat(i, result);
5360 return dst;
5365 LogicVRegister dst,
5370 dst.ClearForWrite(vform);
5374 float acc = dst.Float<float>(i);
5376 dst.SetFloat(i, result);
5378 return dst;
5383 LogicVRegister dst,
5388 dst.ClearForWrite(vform);
5393 float acc = dst.Float<float>(i);
5395 dst.SetFloat(i, result);
5397 return dst;
5402 LogicVRegister dst,
5407 dst.ClearForWrite(vform);
5411 float acc = dst.Float<float>(i);
5413 dst.SetFloat(i, result);
5415 return dst;
5420 LogicVRegister dst,
5425 dst.ClearForWrite(vform);
5430 float acc = dst.Float<float>(i);
5432 dst.SetFloat(i, result);
5434 return dst;
5440 LogicVRegister dst,
5442 dst.ClearForWrite(vform);
5446 dst.SetFloat(i, op);
5448 return dst;
5453 LogicVRegister dst,
5456 fneg<SimFloat16>(vform, dst, src);
5458 fneg<float>(vform, dst, src);
5461 fneg<double>(vform, dst, src);
5463 return dst;
5469 LogicVRegister dst,
5471 dst.ClearForWrite(vform);
5477 dst.SetFloat(i, op);
5479 return dst;
5484 LogicVRegister dst,
5487 fabs_<SimFloat16>(vform, dst, src);
5489 fabs_<float>(vform, dst, src);
5492 fabs_<double>(vform, dst, src);
5494 return dst;
5499 LogicVRegister dst,
5504 fabs_(vform, dst, temp);
5505 return dst;
5510 LogicVRegister dst,
5512 dst.ClearForWrite(vform);
5516 dst.SetFloat(i, result);
5521 dst.SetFloat(i, result);
5527 dst.SetFloat(i, result);
5530 return dst;
5536 LogicVRegister dst, \
5542 FN(vform, dst, temp1, temp2); \
5544 interleave_top_bottom(vform, dst, dst); \
5546 return dst; \
5550 LogicVRegister dst, \
5555 dst.SetUint(vform, 0, Float16ToRawbits(result)); \
5558 dst.SetFloat(0, result); \
5562 dst.SetFloat(0, result); \
5564 dst.ClearForWrite(vform); \
5565 return dst; \
5572 LogicVRegister dst,
5593 dst.ClearForWrite(ScalarFormatFromFormat(vform));
5594 dst.SetFloat<T>(0, result[0]);
5595 return dst;
5600 LogicVRegister dst,
5609 dst,
5614 return FPPairedAcrossHelper<float>(vform, dst, src, fn32, inactive_value);
5618 dst,
5626 LogicVRegister dst,
5629 dst,
5638 LogicVRegister dst,
5644 dst,
5654 LogicVRegister dst,
5660 dst,
5670 LogicVRegister dst,
5675 dst,
5685 LogicVRegister dst,
5690 dst,
5700 LogicVRegister dst,
5704 dst.ClearForWrite(vform);
5708 fmul<SimFloat16>(vform, dst, src1, index_reg);
5711 fmul<float>(vform, dst, src1, index_reg);
5715 fmul<double>(vform, dst, src1, index_reg);
5717 return dst;
5722 LogicVRegister dst,
5726 dst.ClearForWrite(vform);
5730 fmla<SimFloat16>(vform, dst, dst, src1, index_reg);
5733 fmla<float>(vform, dst, dst, src1, index_reg);
5737 fmla<double>(vform, dst, dst, src1, index_reg);
5739 return dst;
5744 LogicVRegister dst,
5748 dst.ClearForWrite(vform);
5752 fmls<SimFloat16>(vform, dst, dst, src1, index_reg);
5755 fmls<float>(vform, dst, dst, src1, index_reg);
5759 fmls<double>(vform, dst, dst, src1, index_reg);
5761 return dst;
5766 LogicVRegister dst,
5770 dst.ClearForWrite(vform);
5774 fmulx<SimFloat16>(vform, dst, src1, index_reg);
5777 fmulx<float>(vform, dst, src1, index_reg);
5781 fmulx<double>(vform, dst, src1, index_reg);
5783 return dst;
5788 LogicVRegister dst,
5793 dst.ClearForWrite(vform);
5802 dst.SetFloat<SimFloat16>(i, rounded);
5812 dst.SetFloat<float>(i, rounded);
5822 dst.SetFloat<double>(i, rounded);
5825 return dst;
5830 LogicVRegister dst,
5850 dst.SetUint(vform, i, dst_raw_bits);
5853 return dst;
5859 LogicVRegister dst,
5878 dst.SetInt(vform, i, FPToInt16(result, round));
5881 dst.SetInt(vform, i, FPToInt32(result, round));
5884 dst.SetInt(vform, i, FPToInt64(result, round));
5892 return dst;
5896 LogicVRegister dst,
5900 dst.ClearForWrite(vform);
5904 dst,
5914 LogicVRegister dst,
5933 dst.SetUint(vform, i, FPToUInt16(result, round));
5936 dst.SetUint(vform, i, FPToUInt32(result, round));
5939 dst.SetUint(vform, i, FPToUInt64(result, round));
5947 return dst;
5951 LogicVRegister dst,
5955 dst.ClearForWrite(vform);
5959 dst,
5967 LogicVRegister dst,
5972 dst.SetFloat(i,
5979 dst.SetFloat(i, FPToDouble(src.Float<float>(i), ReadDN()));
5982 return dst;
5987 LogicVRegister dst,
5993 dst.SetFloat(i,
6001 dst.SetFloat(i, FPToDouble(src.Float<float>(i + lane_count), ReadDN()));
6004 return dst;
6009 LogicVRegister dst,
6013 dst.ClearForWrite(vform);
6016 dst.SetFloat(i,
6024 dst.SetFloat(i, FPToFloat(srctmp.Float<double>(i), FPTieEven, ReadDN()));
6027 return dst;
6032 LogicVRegister dst,
6037 dst.SetFloat(i + lane_count,
6044 dst.SetFloat(i + lane_count,
6048 return dst;
6053 LogicVRegister dst,
6063 dst.ClearForWrite(vform);
6067 dst.SetFloat(i, FPToFloat(srctmp.Float<double>(i), FPRoundOdd, ReadDN()));
6069 return dst;
6074 LogicVRegister dst,
6079 dst.SetFloat(i + lane_count,
6082 return dst;
6183 LogicVRegister dst,
6185 dst.ClearForWrite(vform);
6189 dst.SetFloat(vform, i, FPRecipSqrtEstimate<SimFloat16>(input));
6194 dst.SetFloat(vform, i, FPRecipSqrtEstimate<float>(input));
6200 dst.SetFloat(vform, i, FPRecipSqrtEstimate<double>(input));
6203 return dst;
6327 LogicVRegister dst,
6330 dst.ClearForWrite(vform);
6334 dst.SetFloat(vform, i, FPRecipEstimate<SimFloat16>(input, round));
6339 dst.SetFloat(vform, i, FPRecipEstimate<float>(input, round));
6345 dst.SetFloat(vform, i, FPRecipEstimate<double>(input, round));
6348 return dst;
6353 LogicVRegister dst,
6355 dst.ClearForWrite(vform);
6368 dst.SetUint(vform, i, result);
6370 return dst;
6386 LogicVRegister dst,
6388 dst.ClearForWrite(vform);
6401 dst.SetUint(vform, i, result);
6403 return dst;
6406 LogicPRegister Simulator::pfalse(LogicPRegister dst) {
6407 dst.Clear();
6408 return dst;
6411 LogicPRegister Simulator::pfirst(LogicPRegister dst,
6416 mov(dst, src);
6417 if (first_pg >= 0) dst.SetActive(kFormatVnB, first_pg, true);
6418 return dst;
6422 LogicPRegister dst,
6426 dst.SetActive(vform, i, i < count);
6428 return dst;
6432 LogicPRegister dst,
6442 dst.SetActive(vform, i, (i == next));
6444 return dst;
6449 LogicVRegister dst,
6451 dst.ClearForWrite(vform);
6478 dst.SetFloat(i, result);
6480 return dst;
6485 LogicVRegister dst,
6488 frecpx<SimFloat16>(vform, dst, src);
6490 frecpx<float>(vform, dst, src);
6493 frecpx<double>(vform, dst, src);
6495 return dst;
6499 LogicVRegister dst,
6519 dst.SetInt(vform, i, MaxIntFromFormat(vform));
6523 dst.SetInt(vform, i, MinIntFromFormat(vform));
6532 dst.SetInt(vform, i, -1023 - mant_zero_count);
6537 dst.SetInt(vform, i, static_cast<int64_t>(DoubleExp(op)) - 1023);
6541 return dst;
6545 LogicVRegister dst,
6558 fmul(vform, dst, src1, maybe_neg_src1);
6560 return dst;
6564 LogicVRegister dst,
6586 // the quadrant. Bit 0 controls whether src1 or 1.0 is written to dst. Bit 1
6587 // determines the sign of the value written to dst.
6592 dst.SetUint(vform, i, op);
6595 return dst;
6600 LogicVRegister dst,
6630 mov(vform, dst, cf);
6631 return dst;
6636 LogicVRegister dst,
6696 dst,
6703 dst,
6711 dst,
6717 return dst;
6721 LogicVRegister dst,
6790 dst.SetUint(vform, i, result);
6792 return dst;
6797 LogicVRegister dst,
6824 dst.SetFloat<T>(i, src1_val);
6826 return dst;
6830 LogicVRegister dst,
6834 fscale<SimFloat16>(vform, dst, src1, src2);
6836 fscale<float>(vform, dst, src1, src2);
6839 fscale<double>(vform, dst, src1, src2);
6841 return dst;
6847 LogicVRegister dst,
6854 dst.ClearForWrite(vform);
6866 dst.SetUint(vform, i, Float16ToRawbits(result));
6871 dst.SetUint(vform, i, FloatToRawbits(result));
6876 dst.SetUint(vform, i, DoubleToRawbits(result));
6885 return dst;
6889 LogicVRegister dst,
6896 dst,
6906 LogicVRegister dst,
6913 dst.ClearForWrite(vform);
6925 dst.SetUint(vform, i, Float16ToRawbits(result));
6930 dst.SetUint(vform, i, FloatToRawbits(result));
6935 dst.SetUint(vform, i, DoubleToRawbits(result));
6944 return dst;
6948 LogicVRegister dst,
6955 dst,
6963 LogicVRegister dst,
6978 dst.SetInt(vform, i, result[i]);
6988 dst.SetUint(vform, i, result[i]);
6995 return dst;
7000 LogicPRegister dst,
7070 dst.SetActive(vform, lane, result);
7073 if (flags == SetFlags) PredTest(vform, mask, dst);
7075 return dst;
7080 LogicVRegister dst,
7104 dst.SetUint(vform, lane, result);
7107 return dst;
7111 LogicVRegister dst,
7129 dst.SetInt(vform, i, value);
7131 return dst;
7626 LogicPRegister dst,
7633 pfalse(dst);
7645 SVEPredicateLogicalHelper(ORR_p_p_pp_z, dst, dst, ptemp);
7649 SVEPredicateLogicalHelper(EOR_p_p_pp_z, dst, dst, ptemp);
7651 return dst;
7700 LogicVRegister dst,
7704 return uzp2(vform, dst, src, zero);
7708 LogicVRegister dst,
7712 return uzp1(vform, dst, src, zero);
7716 LogicVRegister dst,
7725 uint64_t right = dst.Uint(vform, i);
7731 dst.SetUint(vform, i, val_and_flags.first);
7735 dst.SetUint(vform, i + 1, carry_out);
7737 return dst;
7842 LogicVRegister dst,
7846 fmatmul<float>(vform, dst, src1, src2);
7849 fmatmul<double>(vform, dst, src1, src2);
7851 return dst;