Lines Matching refs:Simulator
70 double Simulator::FPDefaultNaN<double>() {
76 float Simulator::FPDefaultNaN<float>() {
82 SimFloat16 Simulator::FPDefaultNaN<SimFloat16>() {
87 double Simulator::FixedToDouble(int64_t src, int fbits, FPRounding round) {
98 double Simulator::UFixedToDouble(uint64_t src, int fbits, FPRounding round) {
114 float Simulator::FixedToFloat(int64_t src, int fbits, FPRounding round) {
125 float Simulator::UFixedToFloat(uint64_t src, int fbits, FPRounding round) {
141 SimFloat16 Simulator::FixedToFloat16(int64_t src, int fbits, FPRounding round) {
152 SimFloat16 Simulator::UFixedToFloat16(uint64_t src,
170 uint64_t Simulator::GenerateRandomTag(uint16_t exclude) {
185 void Simulator::ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr) {
194 void Simulator::ld1(VectorFormat vform,
202 void Simulator::ld1r(VectorFormat vform,
219 void Simulator::ld1r(VectorFormat vform, LogicVRegister dst, uint64_t addr) {
224 void Simulator::ld2(VectorFormat vform,
241 void Simulator::ld2(VectorFormat vform,
254 void Simulator::ld2r(VectorFormat vform,
268 void Simulator::ld3(VectorFormat vform,
290 void Simulator::ld3(VectorFormat vform,
307 void Simulator::ld3r(VectorFormat vform,
325 void Simulator::ld4(VectorFormat vform,
352 void Simulator::ld4(VectorFormat vform,
373 void Simulator::ld4r(VectorFormat vform,
395 void Simulator::st1(VectorFormat vform, LogicVRegister src, uint64_t addr) {
403 void Simulator::st1(VectorFormat vform,
411 void Simulator::st2(VectorFormat vform,
426 void Simulator::st2(VectorFormat vform,
437 void Simulator::st3(VectorFormat vform,
456 void Simulator::st3(VectorFormat vform,
469 void Simulator::st4(VectorFormat vform,
492 void Simulator::st4(VectorFormat vform,
507 LogicVRegister Simulator::cmp(VectorFormat vform,
551 LogicVRegister Simulator::cmp(VectorFormat vform,
562 LogicVRegister Simulator::cmptst(VectorFormat vform,
576 LogicVRegister Simulator::add(VectorFormat vform,
606 LogicVRegister Simulator::add_uint(VectorFormat vform,
635 LogicVRegister Simulator::addp(VectorFormat vform,
649 LogicVRegister Simulator::sdiv(VectorFormat vform,
671 LogicVRegister Simulator::udiv(VectorFormat vform,
691 LogicVRegister Simulator::mla(VectorFormat vform,
703 LogicVRegister Simulator::mls(VectorFormat vform,
715 LogicVRegister Simulator::mul(VectorFormat vform,
728 LogicVRegister Simulator::mul(VectorFormat vform,
739 LogicVRegister Simulator::smulh(VectorFormat vform,
770 LogicVRegister Simulator::umulh(VectorFormat vform,
801 LogicVRegister Simulator::mla(VectorFormat vform,
812 LogicVRegister Simulator::mls(VectorFormat vform,
822 LogicVRegister Simulator::sqdmull(VectorFormat vform,
833 LogicVRegister Simulator::sqdmlal(VectorFormat vform,
844 LogicVRegister Simulator::sqdmlsl(VectorFormat vform,
855 LogicVRegister Simulator::sqdmulh(VectorFormat vform,
866 LogicVRegister Simulator::sqrdmulh(VectorFormat vform,
877 LogicVRegister Simulator::sqrdmlah(VectorFormat vform,
888 LogicVRegister Simulator::sqrdmlsh(VectorFormat vform,
899 uint64_t Simulator::PolynomialMult(uint64_t op1,
915 LogicVRegister Simulator::pmul(VectorFormat vform,
931 LogicVRegister Simulator::pmull(VectorFormat vform,
950 LogicVRegister Simulator::pmull2(VectorFormat vform,
968 LogicVRegister Simulator::sub(VectorFormat vform,
998 LogicVRegister Simulator::sub_uint(VectorFormat vform,
1027 LogicVRegister Simulator::and_(VectorFormat vform,
1039 LogicVRegister Simulator::orr(VectorFormat vform,
1051 LogicVRegister Simulator::orn(VectorFormat vform,
1063 LogicVRegister Simulator::eor(VectorFormat vform,
1075 LogicVRegister Simulator::bic(VectorFormat vform,
1087 LogicVRegister Simulator::bic(VectorFormat vform,
1104 LogicVRegister Simulator::bif(VectorFormat vform,
1120 LogicVRegister Simulator::bit(VectorFormat vform,
1136 LogicVRegister Simulator::bsl(VectorFormat vform,
1153 LogicVRegister Simulator::sminmax(VectorFormat vform,
1174 LogicVRegister Simulator::smax(VectorFormat vform,
1182 LogicVRegister Simulator::smin(VectorFormat vform,
1190 LogicVRegister Simulator::sminmaxp(VectorFormat vform,
1221 LogicVRegister Simulator::smaxp(VectorFormat vform,
1229 LogicVRegister Simulator::sminp(VectorFormat vform,
1237 LogicVRegister Simulator::addp(VectorFormat vform,
1249 LogicVRegister Simulator::addv(VectorFormat vform,
1267 LogicVRegister Simulator::saddlv(VectorFormat vform,
1284 LogicVRegister Simulator::uaddlv(VectorFormat vform,
1301 LogicVRegister Simulator::sminmaxv(VectorFormat vform,
1323 LogicVRegister Simulator::smaxv(VectorFormat vform,
1331 LogicVRegister Simulator::sminv(VectorFormat vform,
1339 LogicVRegister Simulator::smaxv(VectorFormat vform,
1349 LogicVRegister Simulator::sminv(VectorFormat vform,
1359 LogicVRegister Simulator::uminmax(VectorFormat vform,
1380 LogicVRegister Simulator::umax(VectorFormat vform,
1388 LogicVRegister Simulator::umin(VectorFormat vform,
1396 LogicVRegister Simulator::uminmaxp(VectorFormat vform,
1427 LogicVRegister Simulator::umaxp(VectorFormat vform,
1435 LogicVRegister Simulator::uminp(VectorFormat vform,
1443 LogicVRegister Simulator::uminmaxv(VectorFormat vform,
1465 LogicVRegister Simulator::umaxv(VectorFormat vform,
1473 LogicVRegister Simulator::uminv(VectorFormat vform,
1481 LogicVRegister Simulator::umaxv(VectorFormat vform,
1491 LogicVRegister Simulator::uminv(VectorFormat vform,
1501 LogicVRegister Simulator::shl(VectorFormat vform,
1512 LogicVRegister Simulator::sshll(VectorFormat vform,
1524 LogicVRegister Simulator::sshll2(VectorFormat vform,
1536 LogicVRegister Simulator::shll(VectorFormat vform,
1544 LogicVRegister Simulator::shll2(VectorFormat vform,
1552 LogicVRegister Simulator::ushll(VectorFormat vform,
1564 LogicVRegister Simulator::ushll2(VectorFormat vform,
1575 std::pair<bool, uint64_t> Simulator::clast(VectorFormat vform,
1589 LogicVRegister Simulator::compact(VectorFormat vform,
1605 LogicVRegister Simulator::splice(VectorFormat vform,
1634 LogicVRegister Simulator::sel(VectorFormat vform,
1651 LogicPRegister Simulator::sel(LogicPRegister dst,
1665 LogicVRegister Simulator::sli(VectorFormat vform,
1682 LogicVRegister Simulator::sqshl(VectorFormat vform,
1693 LogicVRegister Simulator::uqshl(VectorFormat vform,
1704 LogicVRegister Simulator::sqshlu(VectorFormat vform,
1715 LogicVRegister Simulator::sri(VectorFormat vform,
1741 LogicVRegister Simulator::ushr(VectorFormat vform,
1752 LogicVRegister Simulator::sshr(VectorFormat vform,
1763 LogicVRegister Simulator::ssra(VectorFormat vform,
1773 LogicVRegister Simulator::usra(VectorFormat vform,
1783 LogicVRegister Simulator::srsra(VectorFormat vform,
1793 LogicVRegister Simulator::ursra(VectorFormat vform,
1803 LogicVRegister Simulator::cls(VectorFormat vform,
1824 LogicVRegister Simulator::clz(VectorFormat vform,
1845 LogicVRegister Simulator::cnot(VectorFormat vform,
1857 LogicVRegister Simulator::cnt(VectorFormat vform,
1892 LogicVRegister Simulator::sshl(VectorFormat vform,
1957 LogicVRegister Simulator::ushl(VectorFormat vform,
2000 LogicVRegister Simulator::sshr(VectorFormat vform,
2011 LogicVRegister Simulator::ushr(VectorFormat vform,
2022 LogicVRegister Simulator::neg(VectorFormat vform,
2038 LogicVRegister Simulator::suqadd(VectorFormat vform,
2060 LogicVRegister Simulator::usqadd(VectorFormat vform,
2082 LogicVRegister Simulator::abs(VectorFormat vform,
2102 LogicVRegister Simulator::andv(VectorFormat vform,
2121 LogicVRegister Simulator::eorv(VectorFormat vform,
2140 LogicVRegister Simulator::orv(VectorFormat vform,
2159 LogicVRegister Simulator::saddv(VectorFormat vform,
2181 LogicVRegister Simulator::uaddv(VectorFormat vform,
2199 LogicVRegister Simulator::extractnarrow(VectorFormat dstform,
2267 LogicVRegister Simulator::xtn(VectorFormat vform,
2274 LogicVRegister Simulator::sqxtn(VectorFormat vform,
2281 LogicVRegister Simulator::sqxtun(VectorFormat vform,
2288 LogicVRegister Simulator::uqxtn(VectorFormat vform,
2295 LogicVRegister Simulator::absdiff(VectorFormat vform,
2316 LogicVRegister Simulator::saba(VectorFormat vform,
2328 LogicVRegister Simulator::uaba(VectorFormat vform,
2340 LogicVRegister Simulator::not_(VectorFormat vform,
2351 LogicVRegister Simulator::rbit(VectorFormat vform,
2377 LogicVRegister Simulator::rev(VectorFormat vform,
2391 LogicVRegister Simulator::rev_byte(VectorFormat vform,
2412 LogicVRegister Simulator::rev16(VectorFormat vform,
2419 LogicVRegister Simulator::rev32(VectorFormat vform,
2426 LogicVRegister Simulator::rev64(VectorFormat vform,
2432 LogicVRegister Simulator::addlp(VectorFormat vform,
2463 LogicVRegister Simulator::saddlp(VectorFormat vform,
2470 LogicVRegister Simulator::uaddlp(VectorFormat vform,
2477 LogicVRegister Simulator::sadalp(VectorFormat vform,
2484 LogicVRegister Simulator::uadalp(VectorFormat vform,
2490 LogicVRegister Simulator::ror(VectorFormat vform,
2502 LogicVRegister Simulator::ext(VectorFormat vform,
2522 LogicVRegister Simulator::rotate_elements_right(VectorFormat vform,
2534 LogicVRegister Simulator::fadda(VectorFormat vform,
2551 LogicVRegister Simulator::fadda(VectorFormat vform,
2572 LogicVRegister Simulator::fcadd(VectorFormat vform,
2608 LogicVRegister Simulator::fcadd(VectorFormat vform,
2625 LogicVRegister Simulator::fcmla(VectorFormat vform,
2686 LogicVRegister Simulator::fcmla(VectorFormat vform,
2703 LogicVRegister Simulator::fcmla(VectorFormat vform,
2719 LogicVRegister Simulator::cadd(VectorFormat vform,
2757 LogicVRegister Simulator::cmla(VectorFormat vform,
2803 LogicVRegister Simulator::cmla(VectorFormat vform,
2815 LogicVRegister Simulator::bgrp(VectorFormat vform,
2848 LogicVRegister Simulator::bdep(VectorFormat vform,
2868 LogicVRegister Simulator::histogram(VectorFormat vform,
2896 LogicVRegister Simulator::dup_element(VectorFormat vform,
2923 LogicVRegister Simulator::dup_elements_to_segments(VectorFormat vform,
2947 LogicVRegister Simulator::dup_elements_to_segments(
2957 LogicVRegister Simulator::dup_immediate(VectorFormat vform,
2970 LogicVRegister Simulator::ins_element(VectorFormat vform,
2980 LogicVRegister Simulator::ins_immediate(VectorFormat vform,
2990 LogicVRegister Simulator::index(VectorFormat vform,
3004 LogicVRegister Simulator::insr(VectorFormat vform,
3016 LogicVRegister Simulator::mov(VectorFormat vform,
3027 LogicPRegister Simulator::mov(LogicPRegister dst, const LogicPRegister& src) {
3038 LogicVRegister Simulator::mov_merging(VectorFormat vform,
3045 LogicVRegister Simulator::mov_zeroing(VectorFormat vform,
3054 LogicVRegister Simulator::mov_alternating(VectorFormat vform,
3065 LogicPRegister Simulator::mov_merging(LogicPRegister dst,
3071 LogicPRegister Simulator::mov_zeroing(LogicPRegister dst,
3078 LogicVRegister Simulator::movi(VectorFormat vform,
3090 LogicVRegister Simulator::mvni(VectorFormat vform,
3102 LogicVRegister Simulator::orr(VectorFormat vform,
3119 LogicVRegister Simulator::uxtl(VectorFormat vform,
3135 LogicVRegister Simulator::sxtl(VectorFormat vform,
3151 LogicVRegister Simulator::uxtl2(VectorFormat vform,
3158 LogicVRegister Simulator::sxtl2(VectorFormat vform,
3165 LogicVRegister Simulator::uxt(VectorFormat vform,
3180 LogicVRegister Simulator::sxt(VectorFormat vform,
3196 LogicVRegister Simulator::shrn(VectorFormat vform,
3208 LogicVRegister Simulator::shrn2(VectorFormat vform,
3220 LogicVRegister Simulator::rshrn(VectorFormat vform,
3232 LogicVRegister Simulator::rshrn2(VectorFormat vform,
3243 LogicVRegister Simulator::Table(VectorFormat vform,
3276 LogicVRegister Simulator::tbl(VectorFormat vform,
3284 LogicVRegister Simulator::tbl(VectorFormat vform,
3293 LogicVRegister Simulator::tbl(VectorFormat vform,
3303 LogicVRegister Simulator::tbl(VectorFormat vform,
3314 LogicVRegister Simulator::tbx(VectorFormat vform,
3322 LogicVRegister Simulator::tbx(VectorFormat vform,
3331 LogicVRegister Simulator::tbx(VectorFormat vform,
3341 LogicVRegister Simulator::tbx(VectorFormat vform,
3352 LogicVRegister Simulator::uqshrn(VectorFormat vform,
3360 LogicVRegister Simulator::uqshrn2(VectorFormat vform,
3368 LogicVRegister Simulator::uqrshrn(VectorFormat vform,
3376 LogicVRegister Simulator::uqrshrn2(VectorFormat vform,
3384 LogicVRegister Simulator::sqshrn(VectorFormat vform,
3396 LogicVRegister Simulator::sqshrn2(VectorFormat vform,
3408 LogicVRegister Simulator::sqrshrn(VectorFormat vform,
3420 LogicVRegister Simulator::sqrshrn2(VectorFormat vform,
3432 LogicVRegister Simulator::sqshrun(VectorFormat vform,
3444 LogicVRegister Simulator::sqshrun2(VectorFormat vform,
3456 LogicVRegister Simulator::sqrshrun(VectorFormat vform,
3468 LogicVRegister Simulator::sqrshrun2(VectorFormat vform,
3480 LogicVRegister Simulator::uaddl(VectorFormat vform,
3492 LogicVRegister Simulator::uaddl2(VectorFormat vform,
3504 LogicVRegister Simulator::uaddw(VectorFormat vform,
3515 LogicVRegister Simulator::uaddw2(VectorFormat vform,
3526 LogicVRegister Simulator::saddl(VectorFormat vform,
3538 LogicVRegister Simulator::saddl2(VectorFormat vform,
3550 LogicVRegister Simulator::saddw(VectorFormat vform,
3561 LogicVRegister Simulator::saddw2(VectorFormat vform,
3572 LogicVRegister Simulator::usubl(VectorFormat vform,
3584 LogicVRegister Simulator::usubl2(VectorFormat vform,
3596 LogicVRegister Simulator::usubw(VectorFormat vform,
3607 LogicVRegister Simulator::usubw2(VectorFormat vform,
3618 LogicVRegister Simulator::ssubl(VectorFormat vform,
3630 LogicVRegister Simulator::ssubl2(VectorFormat vform,
3642 LogicVRegister Simulator::ssubw(VectorFormat vform,
3653 LogicVRegister Simulator::ssubw2(VectorFormat vform,
3664 LogicVRegister Simulator::uabal(VectorFormat vform,
3676 LogicVRegister Simulator::uabal2(VectorFormat vform,
3688 LogicVRegister Simulator::sabal(VectorFormat vform,
3700 LogicVRegister Simulator::sabal2(VectorFormat vform,
3712 LogicVRegister Simulator::uabdl(VectorFormat vform,
3724 LogicVRegister Simulator::uabdl2(VectorFormat vform,
3736 LogicVRegister Simulator::sabdl(VectorFormat vform,
3748 LogicVRegister Simulator::sabdl2(VectorFormat vform,
3760 LogicVRegister Simulator::umull(VectorFormat vform,
3773 LogicVRegister Simulator::umull2(VectorFormat vform,
3781 LogicVRegister Simulator::smull(VectorFormat vform,
3794 LogicVRegister Simulator::smull2(VectorFormat vform,
3802 LogicVRegister Simulator::umlsl(VectorFormat vform,
3815 LogicVRegister Simulator::umlsl2(VectorFormat vform,
3823 LogicVRegister Simulator::smlsl(VectorFormat vform,
3836 LogicVRegister Simulator::smlsl2(VectorFormat vform,
3844 LogicVRegister Simulator::umlal(VectorFormat vform,
3857 LogicVRegister Simulator::umlal2(VectorFormat vform,
3865 LogicVRegister Simulator::smlal(VectorFormat vform,
3878 LogicVRegister Simulator::smlal2(VectorFormat vform,
3886 LogicVRegister Simulator::sqdmlal(VectorFormat vform,
3897 LogicVRegister Simulator::sqdmlal2(VectorFormat vform,
3905 LogicVRegister Simulator::sqdmlsl(VectorFormat vform,
3916 LogicVRegister Simulator::sqdmlsl2(VectorFormat vform,
3924 LogicVRegister Simulator::sqdmull(VectorFormat vform,
3935 LogicVRegister Simulator::sqdmull2(VectorFormat vform,
3942 LogicVRegister Simulator::sqrdmulh(VectorFormat vform,
3986 LogicVRegister Simulator::dot(VectorFormat vform,
4019 LogicVRegister Simulator::sdot(VectorFormat vform,
4027 LogicVRegister Simulator::udot(VectorFormat vform,
4034 LogicVRegister Simulator::usdot(VectorFormat vform,
4041 LogicVRegister Simulator::cdot(VectorFormat vform,
4069 LogicVRegister Simulator::sqrdcmlah(VectorFormat vform,
4104 LogicVRegister Simulator::sqrdcmlah(VectorFormat vform,
4116 LogicVRegister Simulator::sqrdmlash_d(VectorFormat vform,
4174 LogicVRegister Simulator::sqrdmlash(VectorFormat vform,
4216 LogicVRegister Simulator::sqrdmlah(VectorFormat vform,
4225 LogicVRegister Simulator::sqrdmlsh(VectorFormat vform,
4234 LogicVRegister Simulator::sqdmulh(VectorFormat vform,
4242 LogicVRegister Simulator::addhn(VectorFormat vform,
4253 LogicVRegister Simulator::addhn2(VectorFormat vform,
4264 LogicVRegister Simulator::raddhn(VectorFormat vform,
4275 LogicVRegister Simulator::raddhn2(VectorFormat vform,
4286 LogicVRegister Simulator::subhn(VectorFormat vform,
4297 LogicVRegister Simulator::subhn2(VectorFormat vform,
4308 LogicVRegister Simulator::rsubhn(VectorFormat vform,
4319 LogicVRegister Simulator::rsubhn2(VectorFormat vform,
4330 LogicVRegister Simulator::trn1(VectorFormat vform,
4350 LogicVRegister Simulator::trn2(VectorFormat vform,
4370 LogicVRegister Simulator::zip1(VectorFormat vform,
4390 LogicVRegister Simulator::zip2(VectorFormat vform,
4410 LogicVRegister Simulator::uzp1(VectorFormat vform,
4429 LogicVRegister Simulator::uzp2(VectorFormat vform,
4447 LogicVRegister Simulator::interleave_top_bottom(VectorFormat vform,
4470 T Simulator::FPNeg(T op) {
4475 T Simulator::FPAdd(T op1, T op2) {
4493 T Simulator::FPSub(T op1, T op2) {
4508 T Simulator::FPMulNaNs(T op1, T op2) {
4514 T Simulator::FPMul(T op1, T op2) {
4530 T Simulator::FPMulx(T op1, T op2) {
4541 T Simulator::FPMulAdd(T a, T op1, T op2) {
4586 template float Simulator::FPMulAdd(float a, float op1, float op2);
4588 template double Simulator::FPMulAdd(double a, double op1, double op2);
4591 T Simulator::FPDiv(T op1, T op2) {
4616 T Simulator::FPSqrt(T op) {
4629 T Simulator::FPMax(T a, T b) {
4643 T Simulator::FPMaxNM(T a, T b) {
4656 T Simulator::FPMin(T a, T b) {
4670 T Simulator::FPMinNM(T a, T b) {
4683 T Simulator::FPRecipStepFused(T op1, T op2) {
4711 T Simulator::FPRSqrtStepFused(T op1, T op2) {
4737 int32_t Simulator::FPToFixedJS(double value) {
4805 double Simulator::FPRoundIntCommon(double value, FPRounding round_mode) {
4870 double Simulator::FPRoundInt(double value, FPRounding round_mode) {
4880 double Simulator::FPRoundInt(double value,
4924 int16_t Simulator::FPToInt16(double value, FPRounding rmode) {
4935 int32_t Simulator::FPToInt32(double value, FPRounding rmode) {
4946 int64_t Simulator::FPToInt64(double value, FPRounding rmode) {
4959 uint16_t Simulator::FPToUInt16(double value, FPRounding rmode) {
4970 uint32_t Simulator::FPToUInt32(double value, FPRounding rmode) {
4981 uint64_t Simulator::FPToUInt64(double value, FPRounding rmode) {
4996 LogicVRegister Simulator::FN(VectorFormat vform, \
5018 LogicVRegister Simulator::FN(VectorFormat vform, \
5036 LogicVRegister Simulator::fnmul(VectorFormat vform,
5047 LogicVRegister Simulator::frecps(VectorFormat vform,
5062 LogicVRegister Simulator::frecps(VectorFormat vform,
5079 LogicVRegister Simulator::frsqrts(VectorFormat vform,
5094 LogicVRegister Simulator::frsqrts(VectorFormat vform,
5111 LogicVRegister Simulator::fcmp(VectorFormat vform,
5162 LogicVRegister Simulator::fcmp(VectorFormat vform,
5179 LogicVRegister Simulator::fcmp_zero(VectorFormat vform,
5200 LogicVRegister Simulator::fabscmp(VectorFormat vform,
5225 LogicVRegister Simulator::fmla(VectorFormat vform,
5242 LogicVRegister Simulator::fmla(VectorFormat vform,
5260 LogicVRegister Simulator::fmls(VectorFormat vform,
5277 LogicVRegister Simulator::fmls(VectorFormat vform,
5294 LogicVRegister Simulator::fmlal(VectorFormat vform,
5311 LogicVRegister Simulator::fmlal2(VectorFormat vform,
5329 LogicVRegister Simulator::fmlsl(VectorFormat vform,
5346 LogicVRegister Simulator::fmlsl2(VectorFormat vform,
5364 LogicVRegister Simulator::fmlal(VectorFormat vform,
5382 LogicVRegister Simulator::fmlal2(VectorFormat vform,
5401 LogicVRegister Simulator::fmlsl(VectorFormat vform,
5419 LogicVRegister Simulator::fmlsl2(VectorFormat vform,
5439 LogicVRegister Simulator::fneg(VectorFormat vform,
5452 LogicVRegister Simulator::fneg(VectorFormat vform,
5468 LogicVRegister Simulator::fabs_(VectorFormat vform,
5483 LogicVRegister Simulator::fabs_(VectorFormat vform,
5498 LogicVRegister Simulator::fabd(VectorFormat vform,
5509 LogicVRegister Simulator::fsqrt(VectorFormat vform,
5535 LogicVRegister Simulator::FNP(VectorFormat vform, \
5549 LogicVRegister Simulator::FNP(VectorFormat vform, \
5571 LogicVRegister Simulator::FPPairedAcrossHelper(VectorFormat vform,
5598 LogicVRegister Simulator::FPPairedAcrossHelper(
5625 LogicVRegister Simulator::faddv(VectorFormat vform,
5631 &Simulator::FPAdd<SimFloat16>,
5632 &Simulator::FPAdd<float>,
5633 &Simulator::FPAdd<double>,
5637 LogicVRegister Simulator::fmaxv(VectorFormat vform,
5646 &Simulator::FPMax<SimFloat16>,
5647 &Simulator::FPMax<float>,
5648 &Simulator::FPMax<double>,
5653 LogicVRegister Simulator::fminv(VectorFormat vform,
5662 &Simulator::FPMin<SimFloat16>,
5663 &Simulator::FPMin<float>,
5664 &Simulator::FPMin<double>,
5669 LogicVRegister Simulator::fmaxnmv(VectorFormat vform,
5677 &Simulator::FPMaxNM<SimFloat16>,
5678 &Simulator::FPMaxNM<float>,
5679 &Simulator::FPMaxNM<double>,
5684 LogicVRegister Simulator::fminnmv(VectorFormat vform,
5692 &Simulator::FPMinNM<SimFloat16>,
5693 &Simulator::FPMinNM<float>,
5694 &Simulator::FPMinNM<double>,
5699 LogicVRegister Simulator::fmul(VectorFormat vform,
5721 LogicVRegister Simulator::fmla(VectorFormat vform,
5743 LogicVRegister Simulator::fmls(VectorFormat vform,
5765 LogicVRegister Simulator::fmulx(VectorFormat vform,
5787 LogicVRegister Simulator::frint(VectorFormat vform,
5828 LogicVRegister Simulator::fcvt(VectorFormat dst_vform,
5856 LogicVRegister Simulator::fcvts(VectorFormat vform,
5895 LogicVRegister Simulator::fcvts(VectorFormat vform,
5911 LogicVRegister Simulator::fcvtu(VectorFormat vform,
5950 LogicVRegister Simulator::fcvtu(VectorFormat vform,
5966 LogicVRegister Simulator::fcvtl(VectorFormat vform,
5986 LogicVRegister Simulator::fcvtl2(VectorFormat vform,
6008 LogicVRegister Simulator::fcvtn(VectorFormat vform,
6031 LogicVRegister Simulator::fcvtn2(VectorFormat vform,
6052 LogicVRegister Simulator::fcvtxn(VectorFormat vform,
6073 LogicVRegister Simulator::fcvtxn2(VectorFormat vform,
6087 double Simulator::recip_sqrt_estimate(double a) {
6108 T Simulator::FPRecipSqrtEstimate(T op) {
6182 LogicVRegister Simulator::frsqrte(VectorFormat vform,
6207 T Simulator::FPRecipEstimate(T op, FPRounding rounding) {
6326 LogicVRegister Simulator::frecpe(VectorFormat vform,
6352 LogicVRegister Simulator::ursqrte(VectorFormat vform,
6375 double Simulator::recip_estimate(double a) {
6385 LogicVRegister Simulator::urecpe(VectorFormat vform,
6406 LogicPRegister Simulator::pfalse(LogicPRegister dst) {
6411 LogicPRegister Simulator::pfirst(LogicPRegister dst,
6421 LogicPRegister Simulator::ptrue(VectorFormat vform,
6431 LogicPRegister Simulator::pnext(VectorFormat vform,
6448 LogicVRegister Simulator::frecpx(VectorFormat vform,
6484 LogicVRegister Simulator::frecpx(VectorFormat vform,
6498 LogicVRegister Simulator::flogb(VectorFormat vform,
6544 LogicVRegister Simulator::ftsmul(VectorFormat vform,
6563 LogicVRegister Simulator::ftssel(VectorFormat vform,
6599 LogicVRegister Simulator::FTMaddHelper(VectorFormat vform,
6635 LogicVRegister Simulator::ftmad(VectorFormat vform,
6720 LogicVRegister Simulator::fexpa(VectorFormat vform,
6796 LogicVRegister Simulator::fscale(VectorFormat vform,
6829 LogicVRegister Simulator::fscale(VectorFormat vform,
6844 LogicVRegister Simulator::scvtf(VectorFormat vform,
6888 LogicVRegister Simulator::scvtf(VectorFormat vform,
6903 LogicVRegister Simulator::ucvtf(VectorFormat vform,
6947 LogicVRegister Simulator::ucvtf(VectorFormat vform,
6962 LogicVRegister Simulator::unpk(VectorFormat vform,
6998 LogicPRegister Simulator::SVEIntCompareVectorsHelper(Condition cond,
7078 LogicVRegister Simulator::SVEBitwiseShiftHelper(Shift shift_op,
7110 LogicVRegister Simulator::asrd(VectorFormat vform,
7134 LogicVRegister Simulator::SVEBitwiseLogicalUnpredicatedHelper(
7167 LogicPRegister Simulator::SVEPredicateLogicalHelper(SVEPredicateLogicalOp op,
7212 LogicVRegister Simulator::SVEBitwiseImmHelper(
7239 void Simulator::SVEStructuredStoreHelper(VectorFormat vform,
7301 void Simulator::SVEStructuredLoadHelper(VectorFormat vform,
7359 LogicPRegister Simulator::brka(LogicPRegister pd,
7373 LogicPRegister Simulator::brkb(LogicPRegister pd,
7387 LogicPRegister Simulator::brkn(LogicPRegister pdm,
7396 LogicPRegister Simulator::brkpa(LogicPRegister pd,
7414 LogicPRegister Simulator::brkpb(LogicPRegister pd,
7432 void Simulator::SVEFaultTolerantLoadHelper(VectorFormat vform,
7517 void Simulator::SVEGatherLoadScalarPlusVectorHelper(const Instruction* instr,
7548 int Simulator::GetFirstActive(VectorFormat vform,
7556 int Simulator::GetLastActive(VectorFormat vform,
7564 int Simulator::CountActiveLanes(VectorFormat vform,
7573 int Simulator::CountActiveAndTrueLanes(VectorFormat vform,
7583 int Simulator::GetPredicateConstraintLaneCount(VectorFormat vform,
7625 LogicPRegister Simulator::match(VectorFormat vform,
7699 LogicVRegister Simulator::pack_odd_elements(VectorFormat vform,
7707 LogicVRegister Simulator::pack_even_elements(VectorFormat vform,
7715 LogicVRegister Simulator::adcl(VectorFormat vform,
7760 LogicVRegister Simulator::matmul(VectorFormat vform_dst,
7811 LogicVRegister Simulator::fmatmul(VectorFormat vform,
7841 LogicVRegister Simulator::fmatmul(VectorFormat vform,