Lines Matching defs:value
105 // Calculate the exponent. The highest significant bit will have the value
132 // Calculate the exponent. The highest significant bit will have the value
161 // Calculate the exponent. The highest significant bit will have the value
609 uint64_t value) {
611 VIXL_ASSERT(IsUintN(lane_size, value));
613 // Left-justify `value`.
614 uint64_t ub = value << (64 - lane_size);
624 // `value` is always positive, so we have an overflow if the (signed) result
1001 uint64_t value) {
1003 VIXL_ASSERT(IsUintN(lane_size, value));
1005 // Left-justify `value`.
1006 uint64_t ub = value << (64 - lane_size);
1016 // `value` is always positive, so we have an overflow if the (signed) result
1850 uint64_t value = (src.Uint(vform, i) == 0) ? 1 : 0;
1851 dst.SetUint(vform, i, value);
2358 uint64_t value;
2360 value = src.Uint(vform, i);
2363 reversed_value = (reversed_value << 1) | (value & 1);
2364 value >>= 1;
2496 uint64_t value = src.Uint(vform, i);
2497 dst.SetUint(vform, i, RotateRight(value, rotation, width));
2821 uint64_t value = src1.Uint(vform, i);
2829 result_high |= (value & 1) << high_pos;
2832 result_low |= (value & 1) << low_pos;
2836 value >>= 1;
2853 uint64_t value = src1.Uint(vform, i);
2858 result |= (value & 1) << j;
2859 value >>= 1;
2879 uint64_t value = src1.Uint(vform, i);
2886 (value == src2.Uint(vform, j + segment_offset))) {
2914 uint64_t value = src.Uint(vform, src_index);
2917 dst.SetUint(vform, i, value);
2939 uint64_t value = src.Uint(vform, j + src_index);
2941 dst.SetUint(vform, j + i, value);
2961 uint64_t value = imm & MaxUintFromFormat(vform);
2964 dst.SetUint(vform, i, value);
2984 uint64_t value = imm & MaxUintFromFormat(vform);
2985 dst.SetUint(vform, dst_index, value);
2995 uint64_t value = start;
2997 dst.SetUint(vform, i, value);
2998 value += step;
3188 uint64_t value =
3190 dst.SetInt(vform, i, value);
3971 // Saturation only occurs when src1 = src2 = minimum representable value.
4140 // Shift the whole value left by `esize - 1` bits.
4154 // Arithmetic shift the whole value right by `esize - 1` bits.
4697 bool IsNormal(T value) {
4698 return std::isnormal(value);
4702 bool IsNormal(SimFloat16 value) {
4703 uint16_t rawbits = Float16ToRawbits(value);
4737 int32_t Simulator::FPToFixedJS(double value) {
4739 // to 32-bit integer is exact. If the source value is +/-Infinity, -0.0, NaN,
4745 if ((value == 0.0) || (value == kFP64PositiveInfinity) ||
4746 (value == kFP64NegativeInfinity)) {
4750 if ((value != 0.0) || std::signbit(value)) {
4753 } else if (std::isnan(value)) {
4755 FPProcessNaN(value);
4761 double int_result = std::floor(value);
4762 double error = value - int_result;
4768 // Constrain the value into the range [INT32_MIN, INT32_MAX]. We can almost
4805 double Simulator::FPRoundIntCommon(double value, FPRounding round_mode) {
4806 VIXL_ASSERT((value != kFP64PositiveInfinity) &&
4807 (value != kFP64NegativeInfinity));
4808 VIXL_ASSERT(!IsNaN(value));
4810 double int_result = std::floor(value);
4811 double error = value - int_result;
4816 if ((-0.5 < value) && (value < 0.0)) {
4829 if ((-0.5 <= value) && (value < 0.0)) {
4841 // If value>0 then we take floor(value)
4842 // otherwise, ceil(value).
4843 if (value < 0) {
4844 int_result = ceil(value);
4849 // We always use floor(value).
4855 if ((-1.0 < value) && (value < 0.0)) {
4870 double Simulator::FPRoundInt(double value, FPRounding round_mode) {
4871 if ((value == 0.0) || (value == kFP64PositiveInfinity) ||
4872 (value == kFP64NegativeInfinity)) {
4873 return value;
4874 } else if (IsNaN(value)) {
4875 return FPProcessNaN(value);
4877 return FPRoundIntCommon(value, round_mode);
4880 double Simulator::FPRoundInt(double value,
4884 return FPRoundInt(value, round_mode);
4889 if (value == 0.0) {
4890 return value;
4893 if ((value == kFP64PositiveInfinity) || (value == kFP64NegativeInfinity) ||
4894 IsNaN(value)) {
4902 double result = FPRoundIntCommon(value, round_mode);
4924 int16_t Simulator::FPToInt16(double value, FPRounding rmode) {
4925 value = FPRoundInt(value, rmode);
4926 if (value >= kHMaxInt) {
4928 } else if (value < kHMinInt) {
4931 return IsNaN(value) ? 0 : static_cast<int16_t>(value);
4935 int32_t Simulator::FPToInt32(double value, FPRounding rmode) {
4936 value = FPRoundInt(value, rmode);
4937 if (value >= kWMaxInt) {
4939 } else if (value < kWMinInt) {
4942 return IsNaN(value) ? 0 : static_cast<int32_t>(value);
4946 int64_t Simulator::FPToInt64(double value, FPRounding rmode) {
4947 value = FPRoundInt(value, rmode);
4948 // This is equivalent to "if (value >= kXMaxInt)" but avoids rounding issues
4950 if (value >= 9223372036854775808.) {
4952 } else if (value < kXMinInt) {
4955 return IsNaN(value) ? 0 : static_cast<int64_t>(value);
4959 uint16_t Simulator::FPToUInt16(double value, FPRounding rmode) {
4960 value = FPRoundInt(value, rmode);
4961 if (value >= kHMaxUInt) {
4963 } else if (value < 0.0) {
4966 return IsNaN(value) ? 0 : static_cast<uint16_t>(value);
4970 uint32_t Simulator::FPToUInt32(double value, FPRounding rmode) {
4971 value = FPRoundInt(value, rmode);
4972 if (value >= kWMaxUInt) {
4974 } else if (value < 0.0) {
4977 return IsNaN(value) ? 0 : static_cast<uint32_t>(value);
4981 uint64_t Simulator::FPToUInt64(double value, FPRounding rmode) {
4982 value = FPRoundInt(value, rmode);
4983 // This is equivalent to "if (value >= kXMaxUInt)" but avoids rounding issues
4985 if (value >= 18446744073709551616.) {
4987 } else if (value < 0.0) {
4990 return IsNaN(value) ? 0 : static_cast<uint64_t>(value);
5579 // at the end of the array to the same value that a false predicate would set.
5586 // Pairwise reduce the elements to a single value, using the pair op function
5870 uint64_t value = ExtractUnsignedBitfield64(src_data_size_in_bits - 1,
5873 double result = RawbitsWithSizeToFP<double>(src_data_size_in_bits, value) *
5925 uint64_t value = ExtractUnsignedBitfield64(src_data_size_in_bits - 1,
5928 double result = RawbitsWithSizeToFP<double>(src_data_size_in_bits, value) *
6587 // determines the sign of the value written to dst.
6613 // The specification requires testing the top bit of the raw value, rather
6859 int64_t value = ExtractSignedBitfield64(src_data_size_in_bits - 1,
6865 SimFloat16 result = FixedToFloat16(value, fbits, round);
6870 float result = FixedToFloat(value, fbits, round);
6875 double result = FixedToDouble(value, fbits, round);
6918 uint64_t value = ExtractUnsignedBitfield64(src_data_size_in_bits - 1,
6924 SimFloat16 result = UFixedToFloat16(value, fbits, round);
6929 float result = UFixedToFloat(value, fbits, round);
6934 double result = UFixedToDouble(value, fbits, round);
7091 // which occupies the corresponding lanes of the value to be shifted.
7099 uint64_t value = src1.Uint(vform, lane);
7101 value,
7118 int64_t value = src1.Int(vform, i);
7120 if (value < 0) {
7123 value = value + GetUintMask(shift);
7125 value = ShiftOperand(kDRegSize, value, ASR, shift);
7127 value = 0;
7129 dst.SetInt(vform, i, value);
7287 // Stores don't represent a change to the source register's value, so only
7288 // print the relevant part of the value.
7455 uint64_t value = 0;
7464 value = MemReadUint(msize_in_bytes, element_address);
7476 value = MemReadUint(msize_in_bytes, element_address);
7488 // leave the register value unchanged (like merging predication) because
7496 zt.SetInt(vform, i, ExtractSignedBitfield64(msb, 0, value));
7498 zt.SetUint(vform, i, ExtractUnsignedBitfield64(msb, 0, value));
7835 T value = (i < (T_per_segment * segment_count)) ? result[i] : 0;
7836 srcdst.SetFloat<T>(vform, i, value);