Lines Matching defs:temp2
639 SimVRegister temp1, temp2;
641 uzp2(vform, temp2, src1, src2);
642 add(vform, dst, temp1, temp2);
1517 SimVRegister temp1, temp2;
1519 LogicVRegister extendedreg = sxtl(vform, temp2, src);
1529 SimVRegister temp1, temp2;
1531 LogicVRegister extendedreg = sxtl2(vform, temp2, src);
1557 SimVRegister temp1, temp2;
1559 LogicVRegister extendedreg = uxtl(vform, temp2, src);
1569 SimVRegister temp1, temp2;
1571 LogicVRegister extendedreg = uxtl2(vform, temp2, src);
3484 SimVRegister temp1, temp2;
3486 uxtl(vform, temp2, src2);
3487 add(vform, dst, temp1, temp2);
3496 SimVRegister temp1, temp2;
3498 uxtl2(vform, temp2, src2);
3499 add(vform, dst, temp1, temp2);
3530 SimVRegister temp1, temp2;
3532 sxtl(vform, temp2, src2);
3533 add(vform, dst, temp1, temp2);
3542 SimVRegister temp1, temp2;
3544 sxtl2(vform, temp2, src2);
3545 add(vform, dst, temp1, temp2);
3576 SimVRegister temp1, temp2;
3578 uxtl(vform, temp2, src2);
3579 sub(vform, dst, temp1, temp2);
3588 SimVRegister temp1, temp2;
3590 uxtl2(vform, temp2, src2);
3591 sub(vform, dst, temp1, temp2);
3622 SimVRegister temp1, temp2;
3624 sxtl(vform, temp2, src2);
3625 sub(vform, dst, temp1, temp2);
3634 SimVRegister temp1, temp2;
3636 sxtl2(vform, temp2, src2);
3637 sub(vform, dst, temp1, temp2);
3668 SimVRegister temp1, temp2;
3670 uxtl(vform, temp2, src2);
3671 uaba(vform, dst, temp1, temp2);
3680 SimVRegister temp1, temp2;
3682 uxtl2(vform, temp2, src2);
3683 uaba(vform, dst, temp1, temp2);
3692 SimVRegister temp1, temp2;
3694 sxtl(vform, temp2, src2);
3695 saba(vform, dst, temp1, temp2);
3704 SimVRegister temp1, temp2;
3706 sxtl2(vform, temp2, src2);
3707 saba(vform, dst, temp1, temp2);
3716 SimVRegister temp1, temp2;
3718 uxtl(vform, temp2, src2);
3719 absdiff(vform, dst, temp1, temp2, false);
3728 SimVRegister temp1, temp2;
3730 uxtl2(vform, temp2, src2);
3731 absdiff(vform, dst, temp1, temp2, false);
3740 SimVRegister temp1, temp2;
3742 sxtl(vform, temp2, src2);
3743 absdiff(vform, dst, temp1, temp2, true);
3752 SimVRegister temp1, temp2;
3754 sxtl2(vform, temp2, src2);
3755 absdiff(vform, dst, temp1, temp2, true);
3765 SimVRegister temp1, temp2;
3767 uxtl(vform, temp2, src2, is_2);
3768 mul(vform, dst, temp1, temp2);
3786 SimVRegister temp1, temp2;
3788 sxtl(vform, temp2, src2, is_2);
3789 mul(vform, dst, temp1, temp2);
3807 SimVRegister temp1, temp2;
3809 uxtl(vform, temp2, src2, is_2);
3810 mls(vform, dst, dst, temp1, temp2);
3828 SimVRegister temp1, temp2;
3830 sxtl(vform, temp2, src2, is_2);
3831 mls(vform, dst, dst, temp1, temp2);
3849 SimVRegister temp1, temp2;
3851 uxtl(vform, temp2, src2, is_2);
3852 mla(vform, dst, dst, temp1, temp2);
3870 SimVRegister temp1, temp2;
3872 sxtl(vform, temp2, src2, is_2);
3873 mla(vform, dst, dst, temp1, temp2);
5205 SimVRegister temp1, temp2;
5208 LogicVRegister abs_src2 = fabs_<SimFloat16>(vform, temp2, src2);
5212 LogicVRegister abs_src2 = fabs_<float>(vform, temp2, src2);
5217 LogicVRegister abs_src2 = fabs_<double>(vform, temp2, src2);
5539 SimVRegister temp1, temp2; \
5541 uzp2(vform, temp2, src1, src2); \
5542 FN(vform, dst, temp1, temp2); \