Lines Matching defs:temp1
639 SimVRegister temp1, temp2;
640 uzp1(vform, temp1, src1, src2);
642 add(vform, dst, temp1, temp2);
1517 SimVRegister temp1, temp2;
1518 LogicVRegister shiftreg = dup_immediate(vform, temp1, shift);
1529 SimVRegister temp1, temp2;
1530 LogicVRegister shiftreg = dup_immediate(vform, temp1, shift);
1557 SimVRegister temp1, temp2;
1558 LogicVRegister shiftreg = dup_immediate(vform, temp1, shift);
1569 SimVRegister temp1, temp2;
1570 LogicVRegister shiftreg = dup_immediate(vform, temp1, shift);
3484 SimVRegister temp1, temp2;
3485 uxtl(vform, temp1, src1);
3487 add(vform, dst, temp1, temp2);
3496 SimVRegister temp1, temp2;
3497 uxtl2(vform, temp1, src1);
3499 add(vform, dst, temp1, temp2);
3530 SimVRegister temp1, temp2;
3531 sxtl(vform, temp1, src1);
3533 add(vform, dst, temp1, temp2);
3542 SimVRegister temp1, temp2;
3543 sxtl2(vform, temp1, src1);
3545 add(vform, dst, temp1, temp2);
3576 SimVRegister temp1, temp2;
3577 uxtl(vform, temp1, src1);
3579 sub(vform, dst, temp1, temp2);
3588 SimVRegister temp1, temp2;
3589 uxtl2(vform, temp1, src1);
3591 sub(vform, dst, temp1, temp2);
3622 SimVRegister temp1, temp2;
3623 sxtl(vform, temp1, src1);
3625 sub(vform, dst, temp1, temp2);
3634 SimVRegister temp1, temp2;
3635 sxtl2(vform, temp1, src1);
3637 sub(vform, dst, temp1, temp2);
3668 SimVRegister temp1, temp2;
3669 uxtl(vform, temp1, src1);
3671 uaba(vform, dst, temp1, temp2);
3680 SimVRegister temp1, temp2;
3681 uxtl2(vform, temp1, src1);
3683 uaba(vform, dst, temp1, temp2);
3692 SimVRegister temp1, temp2;
3693 sxtl(vform, temp1, src1);
3695 saba(vform, dst, temp1, temp2);
3704 SimVRegister temp1, temp2;
3705 sxtl2(vform, temp1, src1);
3707 saba(vform, dst, temp1, temp2);
3716 SimVRegister temp1, temp2;
3717 uxtl(vform, temp1, src1);
3719 absdiff(vform, dst, temp1, temp2, false);
3728 SimVRegister temp1, temp2;
3729 uxtl2(vform, temp1, src1);
3731 absdiff(vform, dst, temp1, temp2, false);
3740 SimVRegister temp1, temp2;
3741 sxtl(vform, temp1, src1);
3743 absdiff(vform, dst, temp1, temp2, true);
3752 SimVRegister temp1, temp2;
3753 sxtl2(vform, temp1, src1);
3755 absdiff(vform, dst, temp1, temp2, true);
3765 SimVRegister temp1, temp2;
3766 uxtl(vform, temp1, src1, is_2);
3768 mul(vform, dst, temp1, temp2);
3786 SimVRegister temp1, temp2;
3787 sxtl(vform, temp1, src1, is_2);
3789 mul(vform, dst, temp1, temp2);
3807 SimVRegister temp1, temp2;
3808 uxtl(vform, temp1, src1, is_2);
3810 mls(vform, dst, dst, temp1, temp2);
3828 SimVRegister temp1, temp2;
3829 sxtl(vform, temp1, src1, is_2);
3831 mls(vform, dst, dst, temp1, temp2);
3849 SimVRegister temp1, temp2;
3850 uxtl(vform, temp1, src1, is_2);
3852 mla(vform, dst, dst, temp1, temp2);
3870 SimVRegister temp1, temp2;
3871 sxtl(vform, temp1, src1, is_2);
3873 mla(vform, dst, dst, temp1, temp2);
5205 SimVRegister temp1, temp2;
5207 LogicVRegister abs_src1 = fabs_<SimFloat16>(vform, temp1, src1);
5211 LogicVRegister abs_src1 = fabs_<float>(vform, temp1, src1);
5216 LogicVRegister abs_src1 = fabs_<double>(vform, temp1, src1);
5539 SimVRegister temp1, temp2; \
5540 uzp1(vform, temp1, src1, src2); \
5542 FN(vform, dst, temp1, temp2); \