Lines Matching defs:temp
556 SimVRegister temp;
557 LogicVRegister imm_reg = dup_immediate(vform, temp, imm);
696 SimVRegister temp;
697 mul(vform, temp, src1, src2);
698 add(vform, dst, srca, temp);
708 SimVRegister temp;
709 mul(vform, temp, src1, src2);
710 sub(vform, dst, srca, temp);
733 SimVRegister temp;
735 return mul(vform, dst, src1, dup_element(indexform, temp, src2, index));
806 SimVRegister temp;
808 return mla(vform, dst, dst, src1, dup_element(indexform, temp, src2, index));
817 SimVRegister temp;
819 return mls(vform, dst, dst, src1, dup_element(indexform, temp, src2, index));
827 SimVRegister temp;
830 return sqdmull(vform, dst, src1, dup_element(indexform, temp, src2, index));
838 SimVRegister temp;
841 return sqdmlal(vform, dst, src1, dup_element(indexform, temp, src2, index));
849 SimVRegister temp;
852 return sqdmlsl(vform, dst, src1, dup_element(indexform, temp, src2, index));
860 SimVRegister temp;
862 return sqdmulh(vform, dst, src1, dup_element(indexform, temp, src2, index));
871 SimVRegister temp;
873 return sqrdmulh(vform, dst, src1, dup_element(indexform, temp, src2, index));
882 SimVRegister temp;
884 return sqrdmlah(vform, dst, src1, dup_element(indexform, temp, src2, index));
893 SimVRegister temp;
895 return sqrdmlsh(vform, dst, src1, dup_element(indexform, temp, src2, index));
1506 SimVRegister temp;
1507 LogicVRegister shiftreg = dup_immediate(vform, temp, shift);
1687 SimVRegister temp;
1688 LogicVRegister shiftreg = dup_immediate(vform, temp, shift);
1698 SimVRegister temp;
1699 LogicVRegister shiftreg = dup_immediate(vform, temp, shift);
1709 SimVRegister temp;
1710 LogicVRegister shiftreg = dup_immediate(vform, temp, shift);
1746 SimVRegister temp;
1747 LogicVRegister shiftreg = dup_immediate(vform, temp, -shift);
1757 SimVRegister temp;
1758 LogicVRegister shiftreg = dup_immediate(vform, temp, -shift);
1767 SimVRegister temp;
1768 LogicVRegister shifted_reg = sshr(vform, temp, src, shift);
1777 SimVRegister temp;
1778 LogicVRegister shifted_reg = ushr(vform, temp, src, shift);
1787 SimVRegister temp;
1788 LogicVRegister shifted_reg = sshr(vform, temp, src, shift).Round(vform);
1797 SimVRegister temp;
1798 LogicVRegister shifted_reg = ushr(vform, temp, src, shift).Round(vform);
2004 SimVRegister temp;
2006 neg(vform, temp, src2).SignedSaturate(vform);
2007 sshl(vform, dst, src1, temp, false);
2015 SimVRegister temp;
2017 neg(vform, temp, src2).SignedSaturate(vform);
2018 ushl(vform, dst, src1, temp, false);
2320 SimVRegister temp;
2322 absdiff(vform, temp, src1, src2, true);
2323 add(vform, dst, dst, temp);
2332 SimVRegister temp;
2334 absdiff(vform, temp, src1, src2, false);
2335 add(vform, dst, dst, temp);
2766 SimVRegister zero, temp;
2785 mul(vform, temp, src1_a, src2_a);
2787 sub(vform, srca_r, srca_r, temp);
2789 add(vform, srca_r, srca_r, temp);
2792 mul(vform, temp, src1_a, src2_b);
2794 sub(vform, srca_i, srca_i, temp);
2796 add(vform, srca_i, srca_i, temp);
2810 SimVRegister temp;
2811 dup_elements_to_segments(VectorFormatDoubleWidth(vform), temp, src2, index);
2812 return cmla(vform, dst, srca, src1, temp, rot);
3200 SimVRegister temp;
3203 LogicVRegister shifted_src = ushr(vform_src, temp, src, shift);
3212 SimVRegister temp;
3215 LogicVRegister shifted_src = ushr(vformsrc, temp, src, shift);
3224 SimVRegister temp;
3227 LogicVRegister shifted_src = ushr(vformsrc, temp, src, shift).Round(vformsrc);
3236 SimVRegister temp;
3239 LogicVRegister shifted_src = ushr(vformsrc, temp, src, shift).Round(vformsrc);
3388 SimVRegister temp;
3391 LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift);
3400 SimVRegister temp;
3403 LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift);
3412 SimVRegister temp;
3415 LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift).Round(vformsrc);
3424 SimVRegister temp;
3427 LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift).Round(vformsrc);
3436 SimVRegister temp;
3439 LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift);
3448 SimVRegister temp;
3451 LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift);
3460 SimVRegister temp;
3463 LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift).Round(vformsrc);
3472 SimVRegister temp;
3475 LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift).Round(vformsrc);
3508 SimVRegister temp;
3509 uxtl(vform, temp, src2);
3510 add(vform, dst, src1, temp);
3519 SimVRegister temp;
3520 uxtl2(vform, temp, src2);
3521 add(vform, dst, src1, temp);
3554 SimVRegister temp;
3555 sxtl(vform, temp, src2);
3556 add(vform, dst, src1, temp);
3565 SimVRegister temp;
3566 sxtl2(vform, temp, src2);
3567 add(vform, dst, src1, temp);
3600 SimVRegister temp;
3601 uxtl(vform, temp, src2);
3602 sub(vform, dst, src1, temp);
3611 SimVRegister temp;
3612 uxtl2(vform, temp, src2);
3613 sub(vform, dst, src1, temp);
3646 SimVRegister temp;
3647 sxtl(vform, temp, src2);
3648 sub(vform, dst, src1, temp);
3657 SimVRegister temp;
3658 sxtl2(vform, temp, src2);
3659 sub(vform, dst, src1, temp);
3891 SimVRegister temp;
3892 LogicVRegister product = sqdmull(vform, temp, src1, src2, is_2);
3910 SimVRegister temp;
3911 LogicVRegister product = sqdmull(vform, temp, src1, src2, is_2);
3929 SimVRegister temp;
3930 LogicVRegister product = smull(vform, temp, src1, src2, is_2);
4078 SimVRegister zero, temp;
4111 SimVRegister temp;
4112 dup_elements_to_segments(VectorFormatDoubleWidth(vform), temp, src2, index);
4113 return sqrdcmlah(vform, dst, srca, src1, temp, rot);
4246 SimVRegister temp;
4247 add(VectorFormatDoubleWidth(vform), temp, src1, src2);
4248 shrn(vform, dst, temp, LaneSizeInBitsFromFormat(vform));
4257 SimVRegister temp;
4258 add(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2);
4259 shrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform));
4268 SimVRegister temp;
4269 add(VectorFormatDoubleWidth(vform), temp, src1, src2);
4270 rshrn(vform, dst, temp, LaneSizeInBitsFromFormat(vform));
4279 SimVRegister temp;
4280 add(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2);
4281 rshrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform));
4290 SimVRegister temp;
4291 sub(VectorFormatDoubleWidth(vform), temp, src1, src2);
4292 shrn(vform, dst, temp, LaneSizeInBitsFromFormat(vform));
4301 SimVRegister temp;
4302 sub(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2);
4303 shrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform));
4312 SimVRegister temp;
4313 sub(VectorFormatDoubleWidth(vform), temp, src1, src2);
4314 rshrn(vform, dst, temp, LaneSizeInBitsFromFormat(vform));
4323 SimVRegister temp;
4324 sub(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2);
4325 rshrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform));
5040 SimVRegister temp;
5041 LogicVRegister product = fmul(vform, temp, src1, src2);
5183 SimVRegister temp;
5186 dup_immediate(vform, temp, Float16ToRawbits(SimFloat16(0.0)));
5189 LogicVRegister zero_reg = dup_immediate(vform, temp, FloatToRawbits(0.0));
5193 LogicVRegister zero_reg = dup_immediate(vform, temp, DoubleToRawbits(0.0));
5502 SimVRegister temp;
5503 fsub(vform, temp, src1, src2);
5504 fabs_(vform, dst, temp);
5705 SimVRegister temp;
5707 LogicVRegister index_reg = dup_element(kFormat8H, temp, src2, index);
5710 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index);
5714 LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index);
5727 SimVRegister temp;
5729 LogicVRegister index_reg = dup_element(kFormat8H, temp, src2, index);
5732 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index);
5736 LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index);
5749 SimVRegister temp;
5751 LogicVRegister index_reg = dup_element(kFormat8H, temp, src2, index);
5754 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index);
5758 LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index);
5771 SimVRegister temp;
5773 LogicVRegister index_reg = dup_element(kFormat8H, temp, src2, index);
5776 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index);
5780 LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index);
6627 SimVRegister temp;
6628 fabs_<T>(vform, temp, src2);
6629 fmla<T>(vform, cf, cf, src1, temp);