Lines Matching defs:src2
413 LogicVRegister src2,
419 StoreLane(src2, vform, i, addr2);
428 LogicVRegister src2,
433 StoreLane(src2, vform, index, addr + 1 * esize);
439 LogicVRegister src2,
447 StoreLane(src2, vform, i, addr2);
458 LogicVRegister src2,
464 StoreLane(src2, vform, index, addr + 1 * esize);
471 LogicVRegister src2,
481 StoreLane(src2, vform, i, addr2);
494 LogicVRegister src2,
501 StoreLane(src2, vform, index, addr + 1 * esize);
510 const LogicVRegister& src2,
515 int64_t sb = src2.Int(vform, i);
517 uint64_t ub = src2.Uint(vform, i);
565 const LogicVRegister& src2) {
569 uint64_t ub = src2.Uint(vform, i);
579 const LogicVRegister& src2) {
586 uint64_t ub = src2.UintLeftJustified(vform, i);
638 const LogicVRegister& src2) {
640 uzp1(vform, temp1, src1, src2);
641 uzp2(vform, temp2, src1, src2);
652 const LogicVRegister& src2) {
657 int64_t val2 = src2.Int(vform, i);
674 const LogicVRegister& src2) {
679 uint64_t val2 = src2.Uint(vform, i);
695 const LogicVRegister& src2) {
697 mul(vform, temp, src1, src2);
707 const LogicVRegister& src2) {
709 mul(vform, temp, src1, src2);
718 const LogicVRegister& src2) {
722 dst.SetUint(vform, i, src1.Uint(vform, i) * src2.Uint(vform, i));
731 const LogicVRegister& src2,
735 return mul(vform, dst, src1, dup_element(indexform, temp, src2, index));
742 const LogicVRegister& src2) {
746 int64_t val2 = src2.Int(vform, i);
773 const LogicVRegister& src2) {
777 uint64_t val2 = src2.Uint(vform, i);
804 const LogicVRegister& src2,
808 return mla(vform, dst, dst, src1, dup_element(indexform, temp, src2, index));
815 const LogicVRegister& src2,
819 return mls(vform, dst, dst, src1, dup_element(indexform, temp, src2, index));
825 const LogicVRegister& src2,
830 return sqdmull(vform, dst, src1, dup_element(indexform, temp, src2, index));
836 const LogicVRegister& src2,
841 return sqdmlal(vform, dst, src1, dup_element(indexform, temp, src2, index));
847 const LogicVRegister& src2,
852 return sqdmlsl(vform, dst, src1, dup_element(indexform, temp, src2, index));
858 const LogicVRegister& src2,
862 return sqdmulh(vform, dst, src1, dup_element(indexform, temp, src2, index));
869 const LogicVRegister& src2,
873 return sqrdmulh(vform, dst, src1, dup_element(indexform, temp, src2, index));
880 const LogicVRegister& src2,
884 return sqrdmlah(vform, dst, src1, dup_element(indexform, temp, src2, index));
891 const LogicVRegister& src2,
895 return sqrdmlsh(vform, dst, src1, dup_element(indexform, temp, src2, index));
918 const LogicVRegister& src2) {
924 src2.Uint(vform, i),
934 const LogicVRegister& src2) {
942 src2.Uint(vform_src, i),
953 const LogicVRegister& src2) {
961 src2.Uint(vform_src, lane_count + i),
971 const LogicVRegister& src2) {
977 uint64_t ub = src2.UintLeftJustified(vform, i);
1030 const LogicVRegister& src2) {
1033 dst.SetUint(vform, i, src1.Uint(vform, i) & src2.Uint(vform, i));
1042 const LogicVRegister& src2) {
1045 dst.SetUint(vform, i, src1.Uint(vform, i) | src2.Uint(vform, i));
1054 const LogicVRegister& src2) {
1057 dst.SetUint(vform, i, src1.Uint(vform, i) | ~src2.Uint(vform, i));
1066 const LogicVRegister& src2) {
1069 dst.SetUint(vform, i, src1.Uint(vform, i) ^ src2.Uint(vform, i));
1078 const LogicVRegister& src2) {
1081 dst.SetUint(vform, i, src1.Uint(vform, i) & ~src2.Uint(vform, i));
1107 const LogicVRegister& src2) {
1111 uint64_t operand2 = ~src2.Uint(vform, i);
1123 const LogicVRegister& src2) {
1127 uint64_t operand2 = src2.Uint(vform, i);
1140 const LogicVRegister& src2) {
1143 uint64_t operand1 = src2.Uint(vform, i);
1156 const LogicVRegister& src2,
1161 int64_t src2_val = src2.Int(vform, i);
1177 const LogicVRegister& src2) {
1178 return sminmax(vform, dst, src1, src2, true);
1185 const LogicVRegister& src2) {
1186 return sminmax(vform, dst, src1, src2, false);
1193 const LogicVRegister& src2,
1211 src = &src2;
1224 const LogicVRegister& src2) {
1225 return sminmaxp(vform, dst, src1, src2, true);
1232 const LogicVRegister& src2) {
1233 return sminmaxp(vform, dst, src1, src2, false);
1362 const LogicVRegister& src2,
1367 uint64_t src2_val = src2.Uint(vform, i);
1383 const LogicVRegister& src2) {
1384 return uminmax(vform, dst, src1, src2, true);
1391 const LogicVRegister& src2) {
1392 return uminmax(vform, dst, src1, src2, false);
1399 const LogicVRegister& src2,
1417 src = &src2;
1430 const LogicVRegister& src2) {
1431 return uminmaxp(vform, dst, src1, src2, true);
1438 const LogicVRegister& src2) {
1439 return uminmaxp(vform, dst, src1, src2, false);
1609 const LogicVRegister& src2) {
1626 result[i] = src2.Uint(vform, i - dst_idx);
1638 const LogicVRegister& src2) {
1644 : src2.Uint(vform, lane);
1654 const LogicPRegister& src2) {
1658 (mask & src1.GetChunk(i)) | (~mask & src2.GetChunk(i));
1895 const LogicVRegister& src2,
1900 int64_t shift_val = CalculateSignedShiftDistance(src2.Int(vform, i),
1960 const LogicVRegister& src2,
1965 int64_t shift_val = CalculateSignedShiftDistance(src2.Int(vform, i),
2003 const LogicVRegister& src2) {
2006 neg(vform, temp, src2).SignedSaturate(vform);
2014 const LogicVRegister& src2) {
2017 neg(vform, temp, src2).SignedSaturate(vform);
2041 const LogicVRegister& src2) {
2045 uint64_t ub = src2.UintLeftJustified(vform, i);
2053 dst.SetUint(vform, i, src1.Int(vform, i) + src2.Uint(vform, i));
2063 const LogicVRegister& src2) {
2067 int64_t sb = src2.IntLeftJustified(vform, i);
2075 dst.SetUint(vform, i, src1.Uint(vform, i) + src2.Int(vform, i));
2298 const LogicVRegister& src2,
2302 bool src1_gt_src2 = is_signed ? (src1.Int(vform, i) > src2.Int(vform, i))
2303 : (src1.Uint(vform, i) > src2.Uint(vform, i));
2307 dst.SetUint(vform, i, src1.Uint(vform, i) - src2.Uint(vform, i));
2309 dst.SetUint(vform, i, src2.Uint(vform, i) - src1.Uint(vform, i));
2319 const LogicVRegister& src2) {
2322 absdiff(vform, temp, src1, src2, true);
2331 const LogicVRegister& src2) {
2334 absdiff(vform, temp, src1, src2, false);
2505 const LogicVRegister& src2,
2513 result[lane_count - index + i] = src2.Uint(vform, i);
2575 const LogicVRegister& src2, // m
2589 element1 = FPNeg(src2.Float<T>(e * 2 + 1));
2590 element3 = src2.Float<T>(e * 2);
2593 element1 = src2.Float<T>(e * 2 + 1);
2594 element3 = FPNeg(src2.Float<T>(e * 2));
2611 const LogicVRegister& src2, // m
2614 fcadd<SimFloat16>(vform, dst, src1, src2, rot);
2616 fcadd<float>(vform, dst, src1, src2, rot);
2619 fcadd<double>(vform, dst, src1, src2, rot);
2628 const LogicVRegister& src2,
2648 element1 = src2.Float<T>(f * 2);
2650 element3 = src2.Float<T>(f * 2 + 1);
2654 element1 = FPNeg(src2.Float<T>(f * 2 + 1));
2656 element3 = src2.Float<T>(f * 2);
2660 element1 = FPNeg(src2.Float<T>(f * 2));
2662 element3 = FPNeg(src2.Float<T>(f * 2 + 1));
2666 element1 = src2.Float<T>(f * 2 + 1);
2668 element3 = FPNeg(src2.Float<T>(f * 2));
2689 const LogicVRegister& src2,
2693 fcmla<SimFloat16>(vform, dst, src1, src2, acc, -1, rot);
2695 fcmla<float>(vform, dst, src1, src2, acc, -1, rot);
2697 fcmla<double>(vform, dst, src1, src2, acc, -1, rot);
2706 const LogicVRegister& src2, // m
2712 fcmla<float>(vform, dst, src1, src2, dst, index, rot);
2714 fcmla<double>(vform, dst, src1, src2, dst, index, rot);
2722 const LogicVRegister& src2,
2731 uzp1(vform, src2_r, src2, zero);
2732 uzp2(vform, src2_i, src2, zero);
2761 const LogicVRegister& src2,
2771 uzp1(vform, src2_a, src2, zero);
2772 uzp2(vform, src2_b, src2, zero);
2775 uzp2(vform, src2_a, src2, zero);
2776 uzp1(vform, src2_b, src2, zero);
2807 const LogicVRegister& src2,
2811 dup_elements_to_segments(VectorFormatDoubleWidth(vform), temp, src2, index);
2818 const LogicVRegister& src2,
2822 uint64_t mask = src2.Uint(vform, i);
2851 const LogicVRegister& src2) {
2854 uint64_t mask = src2.Uint(vform, i);
2872 const LogicVRegister& src2,
2886 (value == src2.Uint(vform, j + segment_offset))) {
3483 const LogicVRegister& src2) {
3486 uxtl(vform, temp2, src2);
3495 const LogicVRegister& src2) {
3498 uxtl2(vform, temp2, src2);
3507 const LogicVRegister& src2) {
3509 uxtl(vform, temp, src2);
3518 const LogicVRegister& src2) {
3520 uxtl2(vform, temp, src2);
3529 const LogicVRegister& src2) {
3532 sxtl(vform, temp2, src2);
3541 const LogicVRegister& src2) {
3544 sxtl2(vform, temp2, src2);
3553 const LogicVRegister& src2) {
3555 sxtl(vform, temp, src2);
3564 const LogicVRegister& src2) {
3566 sxtl2(vform, temp, src2);
3575 const LogicVRegister& src2) {
3578 uxtl(vform, temp2, src2);
3587 const LogicVRegister& src2) {
3590 uxtl2(vform, temp2, src2);
3599 const LogicVRegister& src2) {
3601 uxtl(vform, temp, src2);
3610 const LogicVRegister& src2) {
3612 uxtl2(vform, temp, src2);
3621 const LogicVRegister& src2) {
3624 sxtl(vform, temp2, src2);
3633 const LogicVRegister& src2) {
3636 sxtl2(vform, temp2, src2);
3645 const LogicVRegister& src2) {
3647 sxtl(vform, temp, src2);
3656 const LogicVRegister& src2) {
3658 sxtl2(vform, temp, src2);
3667 const LogicVRegister& src2) {
3670 uxtl(vform, temp2, src2);
3679 const LogicVRegister& src2) {
3682 uxtl2(vform, temp2, src2);
3691 const LogicVRegister& src2) {
3694 sxtl(vform, temp2, src2);
3703 const LogicVRegister& src2) {
3706 sxtl2(vform, temp2, src2);
3715 const LogicVRegister& src2) {
3718 uxtl(vform, temp2, src2);
3727 const LogicVRegister& src2) {
3730 uxtl2(vform, temp2, src2);
3739 const LogicVRegister& src2) {
3742 sxtl(vform, temp2, src2);
3751 const LogicVRegister& src2) {
3754 sxtl2(vform, temp2, src2);
3763 const LogicVRegister& src2,
3767 uxtl(vform, temp2, src2, is_2);
3776 const LogicVRegister& src2) {
3777 return umull(vform, dst, src1, src2, /* is_2 = */ true);
3784 const LogicVRegister& src2,
3788 sxtl(vform, temp2, src2, is_2);
3797 const LogicVRegister& src2) {
3798 return smull(vform, dst, src1, src2, /* is_2 = */ true);
3805 const LogicVRegister& src2,
3809 uxtl(vform, temp2, src2, is_2);
3818 const LogicVRegister& src2) {
3819 return umlsl(vform, dst, src1, src2, /* is_2 = */ true);
3826 const LogicVRegister& src2,
3830 sxtl(vform, temp2, src2, is_2);
3839 const LogicVRegister& src2) {
3840 return smlsl(vform, dst, src1, src2, /* is_2 = */ true);
3847 const LogicVRegister& src2,
3851 uxtl(vform, temp2, src2, is_2);
3860 const LogicVRegister& src2) {
3861 return umlal(vform, dst, src1, src2, /* is_2 = */ true);
3868 const LogicVRegister& src2,
3872 sxtl(vform, temp2, src2, is_2);
3881 const LogicVRegister& src2) {
3882 return smlal(vform, dst, src1, src2, /* is_2 = */ true);
3889 const LogicVRegister& src2,
3892 LogicVRegister product = sqdmull(vform, temp, src1, src2, is_2);
3900 const LogicVRegister& src2) {
3901 return sqdmlal(vform, dst, src1, src2, /* is_2 = */ true);
3908 const LogicVRegister& src2,
3911 LogicVRegister product = sqdmull(vform, temp, src1, src2, is_2);
3919 const LogicVRegister& src2) {
3920 return sqdmlsl(vform, dst, src1, src2, /* is_2 = */ true);
3927 const LogicVRegister& src2,
3930 LogicVRegister product = smull(vform, temp, src1, src2, is_2);
3938 const LogicVRegister& src2) {
3939 return sqdmull(vform, dst, src1, src2, /* is_2 = */ true);
3945 const LogicVRegister& src2,
3952 mul(vform, temp_lo, src1, src2);
3953 smulh(vform, temp_hi, src1, src2);
3971 // Saturation only occurs when src1 = src2 = minimum representable value.
3975 (src2.Int(vform, i) == MinIntFromFormat(vform))) {
3989 const LogicVRegister& src2,
4007 element2 = src2.Int(quarter_vform, index);
4009 element2 = src2.Uint(quarter_vform, index);
4022 const LogicVRegister& src2) {
4023 return dot(vform, dst, src1, src2, true, true);
4030 const LogicVRegister& src2) {
4031 return dot(vform, dst, src1, src2, false, false);
4037 const LogicVRegister& src2) {
4038 return dot(vform, dst, src1, src2, false, true);
4045 const LogicVRegister& src2,
4060 int64_t r2 = src2.Int(quarter_vform, (4 * i) + (2 * j) + sel_a);
4061 int64_t i2 = src2.Int(quarter_vform, (4 * i) + (2 * j) + sel_b);
4073 const LogicVRegister& src2,
4083 uzp1(vform, src2_a, src2, zero);
4084 uzp2(vform, src2_b, src2, zero);
4087 uzp2(vform, src2_a, src2, zero);
4088 uzp1(vform, src2_b, src2, zero);
4108 const LogicVRegister& src2,
4112 dup_elements_to_segments(VectorFormatDoubleWidth(vform), temp, src2, index);
4119 const LogicVRegister& src2,
4124 // (dst << (esize - 1) + src1 * src2 + 1 << (esize - 2)) >> (esize - 1)
4126 // (dst << esize + 2 * src1 * src2 + 1 << (esize - 1)) >> esize.
4144 vixl_uint128_t product = Mul64(src1.Int(vform, i), src2.Int(vform, i));
4177 const LogicVRegister& src2,
4182 // (dst << (esize - 1) + src1 * src2 + 1 << (esize - 2)) >> (esize - 1)
4184 // (dst << esize + 2 * src1 * src2 + 1 << (esize - 1)) >> esize.
4187 return sqrdmlash_d(vform, dst, src1, src2, round, sub_op);
4198 accum -= src1.Int(vform, i) * src2.Int(vform, i);
4200 accum += src1.Int(vform, i) * src2.Int(vform, i);
4219 const LogicVRegister& src2,
4221 return sqrdmlash(vform, dst, src1, src2, round, false);
4228 const LogicVRegister& src2,
4230 return sqrdmlash(vform, dst, src1, src2, round, true);
4237 const LogicVRegister& src2) {
4238 return sqrdmulh(vform, dst, src1, src2, false);
4245 const LogicVRegister& src2) {
4247 add(VectorFormatDoubleWidth(vform), temp, src1, src2);
4256 const LogicVRegister& src2) {
4258 add(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2);
4267 const LogicVRegister& src2) {
4269 add(VectorFormatDoubleWidth(vform), temp, src1, src2);
4278 const LogicVRegister& src2) {
4280 add(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2);
4289 const LogicVRegister& src2) {
4291 sub(VectorFormatDoubleWidth(vform), temp, src1, src2);
4300 const LogicVRegister& src2) {
4302 sub(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2);
4311 const LogicVRegister& src2) {
4313 sub(VectorFormatDoubleWidth(vform), temp, src1, src2);
4322 const LogicVRegister& src2) {
4324 sub(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2);
4333 const LogicVRegister& src2) {
4339 result[(2 * i) + 1] = src2.Uint(vform, 2 * i);
4353 const LogicVRegister& src2) {
4359 result[(2 * i) + 1] = src2.Uint(vform, (2 * i) + 1);
4373 const LogicVRegister& src2) {
4379 result[(2 * i) + 1] = src2.Uint(vform, i);
4393 const LogicVRegister& src2) {
4399 result[(2 * i) + 1] = src2.Uint(vform, pairs + i);
4413 const LogicVRegister& src2) {
4418 result[lane_count + i] = src2.Uint(vform, i);
4432 const LogicVRegister& src2) {
4437 result[lane_count + i] = src2.Uint(vform, i);
4999 const LogicVRegister& src2) { \
5003 T op2 = src2.Float<T>(i); \
5021 const LogicVRegister& src2) { \
5023 FN<SimFloat16>(vform, dst, src1, src2); \
5025 FN<float>(vform, dst, src1, src2); \
5028 FN<double>(vform, dst, src1, src2); \
5039 const LogicVRegister& src2) {
5041 LogicVRegister product = fmul(vform, temp, src1, src2);
5050 const LogicVRegister& src2) {
5054 T op2 = src2.Float<T>(i);
5065 const LogicVRegister& src2) {
5067 frecps<SimFloat16>(vform, dst, src1, src2);
5069 frecps<float>(vform, dst, src1, src2);
5072 frecps<double>(vform, dst, src1, src2);
5082 const LogicVRegister& src2) {
5086 T op2 = src2.Float<T>(i);
5097 const LogicVRegister& src2) {
5099 frsqrts<SimFloat16>(vform, dst, src1, src2);
5101 frsqrts<float>(vform, dst, src1, src2);
5104 frsqrts<double>(vform, dst, src1, src2);
5114 const LogicVRegister& src2,
5120 T op2 = src2.Float<T>(i);
5165 const LogicVRegister& src2,
5168 fcmp<SimFloat16>(vform, dst, src1, src2, cond);
5170 fcmp<float>(vform, dst, src1, src2, cond);
5173 fcmp<double>(vform, dst, src1, src2, cond);
5203 const LogicVRegister& src2,
5208 LogicVRegister abs_src2 = fabs_<SimFloat16>(vform, temp2, src2);
5212 LogicVRegister abs_src2 = fabs_<float>(vform, temp2, src2);
5217 LogicVRegister abs_src2 = fabs_<double>(vform, temp2, src2);
5229 const LogicVRegister& src2) {
5233 T op2 = src2.Float<T>(i);
5246 const LogicVRegister& src2) {
5248 fmla<SimFloat16>(vform, dst, srca, src1, src2);
5250 fmla<float>(vform, dst, srca, src1, src2);
5253 fmla<double>(vform, dst, srca, src1, src2);
5264 const LogicVRegister& src2) {
5268 T op2 = src2.Float<T>(i);
5281 const LogicVRegister& src2) {
5283 fmls<SimFloat16>(vform, dst, srca, src1, src2);
5285 fmls<float>(vform, dst, srca, src1, src2);
5288 fmls<double>(vform, dst, srca, src1, src2);
5297 const LogicVRegister& src2) {
5302 float op2 = FPToFloat(src2.Float<SimFloat16>(i), kIgnoreDefaultNaN);
5314 const LogicVRegister& src2) {
5320 float op2 = FPToFloat(src2.Float<SimFloat16>(src), kIgnoreDefaultNaN);
5332 const LogicVRegister& src2) {
5337 float op2 = FPToFloat(src2.Float<SimFloat16>(i), kIgnoreDefaultNaN);
5349 const LogicVRegister& src2) {
5355 float op2 = FPToFloat(src2.Float<SimFloat16>(src), kIgnoreDefaultNaN);
5367 const LogicVRegister& src2,
5371 float op2 = FPToFloat(src2.Float<SimFloat16>(index), kIgnoreDefaultNaN);
5385 const LogicVRegister& src2,
5389 float op2 = FPToFloat(src2.Float<SimFloat16>(index), kIgnoreDefaultNaN);
5404 const LogicVRegister& src2,
5408 float op2 = FPToFloat(src2.Float<SimFloat16>(index), kIgnoreDefaultNaN);
5422 const LogicVRegister& src2,
5426 float op2 = FPToFloat(src2.Float<SimFloat16>(index), kIgnoreDefaultNaN);
5501 const LogicVRegister& src2) {
5503 fsub(vform, temp, src1, src2);
5538 const LogicVRegister& src2) { \
5540 uzp1(vform, temp1, src1, src2); \
5541 uzp2(vform, temp2, src1, src2); \
5702 const LogicVRegister& src2,
5707 LogicVRegister index_reg = dup_element(kFormat8H, temp, src2, index);
5710 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index);
5714 LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index);
5724 const LogicVRegister& src2,
5729 LogicVRegister index_reg = dup_element(kFormat8H, temp, src2, index);
5732 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index);
5736 LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index);
5746 const LogicVRegister& src2,
5751 LogicVRegister index_reg = dup_element(kFormat8H, temp, src2, index);
5754 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index);
5758 LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index);
5768 const LogicVRegister& src2,
5773 LogicVRegister index_reg = dup_element(kFormat8H, temp, src2, index);
5776 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index);
5780 LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index);
6547 const LogicVRegister& src2) {
6550 // The bottom bit of src2 controls the sign of the result. Use it to
6552 shl(vform, maybe_neg_src1, src2, LaneSizeInBitsFromFormat(vform) - 1);
6566 const LogicVRegister& src2) {
6585 // Only the bottom two bits of the src2 register are significant, indicating
6588 uint64_t q = src2.Uint(vform, i);
6602 const LogicVRegister& src2,
6621 src2,
6628 fabs_<T>(vform, temp, src2);
6638 const LogicVRegister& src2,
6698 src2,
6705 src2,
6713 src2,
6799 const LogicVRegister& src2) {
6804 int64_t scale = src2.Int(vform, i);
6819 // zero. Initially, scale is (src2 - 1), so we pre-increment.
6832 const LogicVRegister& src2) {
6834 fscale<SimFloat16>(vform, dst, src1, src2);
6836 fscale<float>(vform, dst, src1, src2);
6839 fscale<double>(vform, dst, src1, src2);
7003 const LogicVRegister& src2,
7020 op2 = is_wide_elements ? src2.Int(kFormatVnD, d_lane)
7021 : src2.Int(vform, lane);
7028 op2 = is_wide_elements ? src2.Uint(kFormatVnD, d_lane)
7029 : src2.Uint(vform, lane);
7082 const LogicVRegister& src2,
7094 uint64_t shift_amount = src2.Uint(shift_vform, shift_src_lane);
7718 const LogicVRegister& src2,
7726 unsigned carry_in = src2.Uint(vform, i + 1) & 1;
7740 // Multiply the 2x8 8-bit matrix in src1 by the 8x2 8-bit matrix in src2, add
7745 // src1 = ( a b c d e f g h ) src2 = ( A B )
7758 // src2 = [ P | N | L | J | H | F | D | B | O | M | K | I | G | E | C | A ]
7763 const LogicVRegister& src2,
7784 int64_t e2 = src2_signed ? src2.Int(vform_src, idx2)
7785 : src2.Uint(vform_src, idx2);
7796 // Multiply the 2x2 FP matrix in src1 by the 2x2 FP matrix in src2, add the 2x2
7801 // src1 = ( a b ) src2 = ( A B )
7808 // src2 = [ D | B | C | A ]
7814 const LogicVRegister& src2) {
7823 src2.Float<T>(2 * j + 0 + segoff));
7825 src2.Float<T>(2 * j + 1 + segoff));
7844 const LogicVRegister& src2) {
7846 fmatmul<float>(vform, dst, src1, src2);
7849 fmatmul<double>(vform, dst, src1, src2);