Lines Matching defs:bit
100 // subnormal: The exponent is encoded as 0 and there is no implicit 1 bit.
105 // Calculate the exponent. The highest significant bit will have the value
127 // subnormal: The exponent is encoded as 0 and there is no implicit 1 bit.
132 // Calculate the exponent. The highest significant bit will have the value
156 // subnormal: The exponent is encoded as 0 and there is no implicit 1 bit.
161 // Calculate the exponent. The highest significant bit will have the value
1120 LogicVRegister Simulator::bit(VectorFormat vform,
1935 // Set rounding state by testing most-significant bit shifted out.
2902 // 64-bit parts, and duplicate the parts across the destination.
2927 // In SVE, a segment is a 128-bit portion of a vector, like a Q register,
3955 // Double by shifting high half, and adding in most-significant bit of low
3961 // Add the second (due to doubling) most-significant bit of the low half
4739 // to 32-bit integer is exact. If the source value is +/-Infinity, -0.0, NaN,
4740 // outside the bounds of a 32-bit integer, or isn't an exact integer then the
4785 // Take the bottom 32 bits of the result as a 32-bit integer.
6550 // The bottom bit of src2 controls the sign of the result. Use it to
6613 // The specification requires testing the top bit of the raw value, rather
7740 // Multiply the 2x8 8-bit matrix in src1 by the 8x2 8-bit matrix in src2, add
7741 // the 2x2 32-bit result to the matrix in srcdst, and write back to srcdst.