Lines Matching defs:add
576 LogicVRegister Simulator::add(VectorFormat vform,
642 add(vform, dst, temp1, temp2);
698 add(vform, dst, srca, temp);
1769 return add(vform, dst, dst, shifted_reg);
1779 return add(vform, dst, dst, shifted_reg);
1789 return add(vform, dst, dst, shifted_reg);
1799 return add(vform, dst, dst, shifted_reg);
2323 add(vform, dst, dst, temp);
2335 add(vform, dst, dst, temp);
2737 add(vform, src1_i, src1_i, src2_r).SignedSaturate(vform);
2740 add(vform, src1_i, src1_i, src2_r);
2745 add(vform, src1_r, src1_r, src2_i).SignedSaturate(vform);
2748 add(vform, src1_r, src1_r, src2_i);
2789 add(vform, srca_r, srca_r, temp);
2796 add(vform, srca_i, srca_i, temp);
3487 add(vform, dst, temp1, temp2);
3499 add(vform, dst, temp1, temp2);
3510 add(vform, dst, src1, temp);
3521 add(vform, dst, src1, temp);
3533 add(vform, dst, temp1, temp2);
3545 add(vform, dst, temp1, temp2);
3556 add(vform, dst, src1, temp);
3567 add(vform, dst, src1, temp);
3893 return add(vform, dst, dst, product).SignedSaturate(vform);
3931 return add(vform, dst, product, product).SignedSaturate(vform);
4247 add(VectorFormatDoubleWidth(vform), temp, src1, src2);
4258 add(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2);
4269 add(VectorFormatDoubleWidth(vform), temp, src1, src2);
4280 add(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2);
4722 // The multiply-add-halve operation must be fully fused, so avoid interim
4724 // before doing the multiply-add.
7740 // Multiply the 2x8 8-bit matrix in src1 by the 8x2 8-bit matrix in src2, add
7796 // Multiply the 2x2 FP matrix in src1 by the 2x2 FP matrix in src2, add the 2x2