Lines Matching refs:instr
788 void Disassembler::VisitAddSubImmediate(const Instruction *instr) {
789 bool rd_is_zr = RdIsZROrSP(instr);
791 (rd_is_zr || RnIsZROrSP(instr)) && (instr->GetImmAddSub() == 0) ? true
821 Format(instr, mnemonic, form);
825 void Disassembler::VisitAddSubShifted(const Instruction *instr) {
826 bool rd_is_zr = RdIsZROrSP(instr);
827 bool rn_is_zr = RnIsZROrSP(instr);
833 if (instr->GetShiftDP() == ROR) {
835 VisitUnallocated(instr);
864 Format(instr, mnemonic, form);
868 void Disassembler::VisitAddSubExtended(const Instruction *instr) {
869 bool rd_is_zr = RdIsZROrSP(instr);
871 Extend mode = static_cast<Extend>(instr->GetExtendMode());
877 switch (instr->Mask(AddSubExtendedMask)) {
907 Format(instr, mnemonic, form);
911 void Disassembler::VisitAddSubWithCarry(const Instruction *instr) {
912 bool rn_is_zr = RnIsZROrSP(instr);
917 switch (instr->Mask(AddSubWithCarryMask)) {
947 Format(instr, mnemonic, form);
951 void Disassembler::VisitRotateRightIntoFlags(const Instruction *instr) {
952 FormatWithDecodedMnemonic(instr, "'Xn, 'IRr, 'INzcv");
956 void Disassembler::VisitEvaluateIntoFlags(const Instruction *instr) {
957 FormatWithDecodedMnemonic(instr, "'Wn");
961 void Disassembler::VisitLogicalImmediate(const Instruction *instr) {
962 bool rd_is_zr = RdIsZROrSP(instr);
963 bool rn_is_zr = RnIsZROrSP(instr);
967 if (instr->GetImmLogical() == 0) {
969 Format(instr, "unallocated", "(LogicalImmediate)");
973 switch (instr->Mask(LogicalImmediateMask)) {
982 (instr->GetSixtyFourBits() == 1) ? kXRegSize : kWRegSize;
983 if (rn_is_zr && !IsMovzMovnImm(reg_size, instr->GetImmLogical())) {
1005 Format(instr, mnemonic, form);
1037 void Disassembler::VisitLogicalShifted(const Instruction *instr) {
1038 bool rd_is_zr = RdIsZROrSP(instr);
1039 bool rn_is_zr = RnIsZROrSP(instr);
1053 if (rn_is_zr && (instr->GetImmDPShift() == 0) &&
1054 (instr->GetShiftDP() == LSL)) {
1068 Format(instr, mnemonic, form);
1072 void Disassembler::VisitConditionalCompareRegister(const Instruction *instr) {
1073 FormatWithDecodedMnemonic(instr, "'Rn, 'Rm, 'INzcv, 'Cond");
1077 void Disassembler::VisitConditionalCompareImmediate(const Instruction *instr) {
1078 FormatWithDecodedMnemonic(instr, "'Rn, 'IP, 'INzcv, 'Cond");
1082 void Disassembler::VisitConditionalSelect(const Instruction *instr) {
1083 bool rnm_is_zr = (RnIsZROrSP(instr) && RmIsZROrSP(instr));
1084 bool rn_is_rm = (instr->GetRn() == instr->GetRm());
1090 Condition cond = static_cast<Condition>(instr->GetCondition());
1093 switch (instr->Mask(ConditionalSelectMask)) {
1134 Format(instr, mnemonic, form);
1138 void Disassembler::VisitBitfield(const Instruction *instr) {
1139 unsigned s = instr->GetImmS();
1140 unsigned r = instr->GetImmR();
1142 ((instr->GetSixtyFourBits() == 1) ? kXRegSize : kWRegSize) - 1;
1152 if (instr->GetSixtyFourBits() != instr->GetBitN()) {
1153 VisitUnallocated(instr);
1157 if ((instr->GetSixtyFourBits() == 0) && ((s > 31) || (r > 31))) {
1158 VisitUnallocated(instr);
1162 switch (instr->Mask(BitfieldMask)) {
1173 } else if ((s == 31) && (instr->GetSixtyFourBits() == 1)) {
1218 if (instr->GetRn() == kZeroRegCode) {
1228 Format(instr, mnemonic, form);
1232 void Disassembler::VisitExtract(const Instruction *instr) {
1236 switch (instr->Mask(ExtractMask)) {
1239 if (instr->GetRn() == instr->GetRm()) {
1250 Format(instr, mnemonic, form);
1254 void Disassembler::VisitPCRelAddressing(const Instruction *instr) {
1255 switch (instr->Mask(PCRelAddressingMask)) {
1257 Format(instr, "adr", "'Xd, 'AddrPCRelByte");
1260 Format(instr, "adrp", "'Xd, 'AddrPCRelPage");
1263 Format(instr, "unimplemented", "(PCRelAddressing)");
1268 void Disassembler::VisitConditionalBranch(const Instruction *instr) {
1273 Format(instr, "b.'CBrn", "'TImmCond");
1278 const Instruction *instr) {
1283 if (instr->GetRn() == kLinkRegCode) {
1299 FormatWithDecodedMnemonic(instr, form);
1303 void Disassembler::VisitUnconditionalBranch(const Instruction *instr) {
1304 FormatWithDecodedMnemonic(instr, "'TImmUncn");
1308 void Disassembler::VisitDataProcessing1Source(const Instruction *instr) {
1335 FormatWithDecodedMnemonic(instr, form);
1339 void Disassembler::VisitDataProcessing2Source(const Instruction *instr) {
1364 Format(instr, mnemonic.c_str(), form);
1368 void Disassembler::VisitDataProcessing3Source(const Instruction *instr) {
1369 bool ra_is_zr = RaIsZROrSP(instr);
1377 switch (instr->Mask(DataProcessing3SourceMask)) {
1443 Format(instr, mnemonic, form);
1446 void Disassembler::DisassembleMinMaxImm(const Instruction *instr) {
1447 const char *suffix = (instr->ExtractBit(18) == 0) ? "'s1710" : "'u1710";
1448 FormatWithDecodedMnemonic(instr, "'Rd, 'Rn, #", suffix);
1451 void Disassembler::VisitCompareBranch(const Instruction *instr) {
1452 FormatWithDecodedMnemonic(instr, "'Rt, 'TImmCmpa");
1456 void Disassembler::VisitTestBranch(const Instruction *instr) {
1461 FormatWithDecodedMnemonic(instr, "'Rt, 'It, 'TImmTest");
1465 void Disassembler::VisitMoveWideImmediate(const Instruction *instr) {
1472 switch (instr->Mask(MoveWideImmediateMask)) {
1475 if ((instr->GetImmMoveWide()) || (instr->GetShiftMoveWide() == 0)) {
1476 if ((instr->GetSixtyFourBits() == 0) &&
1477 (instr->GetImmMoveWide() == 0xffff)) {
1489 if ((instr->GetImmMoveWide()) || (instr->GetShiftMoveWide() == 0))
1502 Format(instr, mnemonic, form);
1531 void Disassembler::VisitLoadStorePreIndex(const Instruction *instr) {
1535 switch (instr->Mask(LoadStorePreIndexMask)) {
1543 FormatWithDecodedMnemonic(instr, form, suffix);
1547 void Disassembler::VisitLoadStorePostIndex(const Instruction *instr) {
1551 switch (instr->Mask(LoadStorePostIndexMask)) {
1559 FormatWithDecodedMnemonic(instr, form, suffix);
1563 void Disassembler::VisitLoadStoreUnsignedOffset(const Instruction *instr) {
1567 switch (instr->Mask(LoadStoreUnsignedOffsetMask)) {
1577 FormatWithDecodedMnemonic(instr, form, suffix);
1581 void Disassembler::VisitLoadStoreRCpcUnscaledOffset(const Instruction *instr) {
1596 Format(instr, mnemonic, form);
1600 void Disassembler::VisitLoadStoreRegisterOffset(const Instruction *instr) {
1604 switch (instr->Mask(LoadStoreRegisterOffsetMask)) {
1614 FormatWithDecodedMnemonic(instr, form, suffix);
1618 void Disassembler::VisitLoadStoreUnscaledOffset(const Instruction *instr) {
1654 FormatWithDecodedMnemonic(instr, form, suffix);
1658 void Disassembler::VisitLoadLiteral(const Instruction *instr) {
1680 FormatWithDecodedMnemonic(instr, form, suffix);
1697 void Disassembler::VisitLoadStorePairPostIndex(const Instruction *instr) {
1700 switch (instr->Mask(LoadStorePairPostIndexMask)) {
1708 FormatWithDecodedMnemonic(instr, form);
1712 void Disassembler::VisitLoadStorePairPreIndex(const Instruction *instr) {
1715 switch (instr->Mask(LoadStorePairPreIndexMask)) {
1723 FormatWithDecodedMnemonic(instr, form);
1727 void Disassembler::VisitLoadStorePairOffset(const Instruction *instr) {
1730 switch (instr->Mask(LoadStorePairOffsetMask)) {
1738 FormatWithDecodedMnemonic(instr, form);
1742 void Disassembler::VisitLoadStorePairNonTemporal(const Instruction *instr) {
1763 FormatWithDecodedMnemonic(instr, form);
1817 void Disassembler::VisitLoadStoreExclusive(const Instruction *instr) {
1821 switch (instr->Mask(LoadStoreExclusiveMask)) {
1830 switch (instr->Mask(LoadStoreExclusiveMask)) {
1839 if ((instr->GetRs() % 2 == 1) || (instr->GetRt() % 2 == 1)) {
1840 VisitUnallocated(instr);
1846 FormatWithDecodedMnemonic(instr, form, suffix);
1849 void Disassembler::VisitLoadStorePAC(const Instruction *instr) {
1858 FormatWithDecodedMnemonic(instr, form, suffix);
1861 void Disassembler::VisitAtomicMemory(const Instruction *instr) {
1862 bool is_x = (instr->ExtractBits(31, 30) == 3);
1879 if (instr->GetRt() == kZeroRegCode) {
1884 Format(instr, mnemonic.c_str(), form, suffix);
1888 void Disassembler::VisitFPCompare(const Instruction *instr) {
1899 FormatWithDecodedMnemonic(instr, form);
1903 void Disassembler::VisitFPConditionalCompare(const Instruction *instr) {
1904 FormatWithDecodedMnemonic(instr, "'Fn, 'Fm, 'INzcv, 'Cond");
1908 void Disassembler::VisitFPConditionalSelect(const Instruction *instr) {
1909 FormatWithDecodedMnemonic(instr, "'Fd, 'Fn, 'Fm, 'Cond");
1913 void Disassembler::VisitFPDataProcessing1Source(const Instruction *instr) {
1935 FormatWithDecodedMnemonic(instr, form);
1939 void Disassembler::VisitFPDataProcessing2Source(const Instruction *instr) {
1940 FormatWithDecodedMnemonic(instr, "'Fd, 'Fn, 'Fm");
1944 void Disassembler::VisitFPDataProcessing3Source(const Instruction *instr) {
1945 FormatWithDecodedMnemonic(instr, "'Fd, 'Fn, 'Fm, 'Fa");
1949 void Disassembler::VisitFPImmediate(const Instruction *instr) {
1960 FormatWithDecodedMnemonic(instr, form, suffix);
1964 void Disassembler::VisitFPIntegerConvert(const Instruction *instr) {
1992 FormatWithDecodedMnemonic(instr, form);
1996 void Disassembler::VisitFPFixedPointConvert(const Instruction *instr) {
2016 FormatWithDecodedMnemonic(instr, form, suffix);
2019 void Disassembler::DisassembleNoArgs(const Instruction *instr) {
2020 Format(instr, mnemonic_.c_str(), "");
2023 void Disassembler::VisitSystem(const Instruction *instr) {
2030 form = (instr->GetCRm() == 0xf) ? "" : "'IX";
2039 switch (instr->ExtractBits(7, 6)) {
2061 int crm = instr->GetCRm();
2095 uint32_t sysop = instr->GetSysOp();
2104 if (instr->GetRt() == 31) {
2111 Format(instr, mnemonic, form, suffix);
2115 void Disassembler::VisitException(const Instruction *instr) {
2119 switch (instr->Mask(ExceptionMask)) {
2150 Format(instr, mnemonic, form);
2154 void Disassembler::VisitCrypto2RegSHA(const Instruction *instr) {
2155 VisitUnimplemented(instr);
2159 void Disassembler::VisitCrypto3RegSHA(const Instruction *instr) {
2160 VisitUnimplemented(instr);
2164 void Disassembler::VisitCryptoAES(const Instruction *instr) {
2165 VisitUnimplemented(instr);
2168 void Disassembler::DisassembleNEON2RegAddlp(const Instruction *instr) {
2174 NEONFormatDecoder nfd(instr);
2176 Format(instr, mnemonic, nfd.Substitute(form));
2179 void Disassembler::DisassembleNEON2RegCompare(const Instruction *instr) {
2182 NEONFormatDecoder nfd(instr);
2183 Format(instr, mnemonic, nfd.Substitute(form));
2186 void Disassembler::DisassembleNEON2RegFPCompare(const Instruction *instr) {
2189 NEONFormatDecoder nfd(instr, NEONFormatDecoder::FPFormatMap());
2190 Format(instr, mnemonic, nfd.Substitute(form));
2193 void Disassembler::DisassembleNEON2RegFPConvert(const Instruction *instr) {
2200 NEONFormatDecoder nfd(instr, &map_cvt_tb, &map_cvt_ta);
2213 Format(instr, nfd.Mnemonic(mnemonic), nfd.Substitute(form));
2216 void Disassembler::DisassembleNEON2RegFP(const Instruction *instr) {
2219 NEONFormatDecoder nfd(instr, NEONFormatDecoder::FPFormatMap());
2220 Format(instr, mnemonic, nfd.Substitute(form));
2223 void Disassembler::DisassembleNEON2RegLogical(const Instruction *instr) {
2226 NEONFormatDecoder nfd(instr, NEONFormatDecoder::LogicalFormatMap());
2230 Format(instr, mnemonic, nfd.Substitute(form));
2233 void Disassembler::DisassembleNEON2RegExtract(const Instruction *instr) {
2237 NEONFormatDecoder nfd(instr,
2243 switch (instr->GetNEONSize()) {
2255 Format(instr, nfd.Mnemonic(mnemonic), nfd.Substitute(form), suffix);
2258 void Disassembler::VisitNEON2RegMisc(const Instruction *instr) {
2261 NEONFormatDecoder nfd(instr);
2295 Format(instr, mnemonic, nfd.Substitute(form));
2298 void Disassembler::VisitNEON2RegMiscFP16(const Instruction *instr) {
2311 Format(instr, mnemonic, form, suffix);
2314 void Disassembler::DisassembleNEON3SameLogical(const Instruction *instr) {
2317 NEONFormatDecoder nfd(instr, NEONFormatDecoder::LogicalFormatMap());
2321 if (instr->GetRm() == instr->GetRn()) {
2327 if (instr->GetNEONSize() != 0) {
2331 Format(instr, mnemonic, nfd.Substitute(form));
2334 void Disassembler::DisassembleNEON3SameFHM(const Instruction *instr) {
2335 FormatWithDecodedMnemonic(instr, "'Vd.'?30:42s, 'Vn.'?30:42h, 'Vm.'?30:42h");
2338 void Disassembler::DisassembleNEON3SameNoD(const Instruction *instr) {
2344 NEONFormatDecoder nfd(instr, &map);
2345 Format(instr, mnemonic, nfd.Substitute(form));
2348 void Disassembler::VisitNEON3Same(const Instruction *instr) {
2351 NEONFormatDecoder nfd(instr);
2353 if (instr->Mask(NEON3SameFPFMask) == NEON3SameFPFixed) {
2369 Format(instr, mnemonic, nfd.Substitute(form));
2372 void Disassembler::VisitNEON3SameFP16(const Instruction *instr) {
2375 NEONFormatDecoder nfd(instr);
2377 Format(instr, mnemonic, nfd.Substitute(form));
2380 void Disassembler::VisitNEON3SameExtra(const Instruction *instr) {
2387 NEONFormatDecoder nfd(instr);
2408 Format(instr, mnemonic, nfd.Substitute(form), suffix);
2412 void Disassembler::VisitNEON3Different(const Instruction *instr) {
2416 NEONFormatDecoder nfd(instr);
2446 Format(instr, nfd.Mnemonic(mnemonic), nfd.Substitute(form));
2449 void Disassembler::DisassembleNEONFPAcrossLanes(const Instruction *instr) {
2452 if ((instr->GetNEONQ() == 0) || (instr->ExtractBit(22) == 1)) {
2455 Format(instr, mnemonic, form);
2458 void Disassembler::DisassembleNEONFP16AcrossLanes(const Instruction *instr) {
2459 FormatWithDecodedMnemonic(instr, "'Hd, 'Vn.'?30:84h");
2462 void Disassembler::VisitNEONAcrossLanes(const Instruction *instr) {
2466 NEONFormatDecoder nfd(instr,
2481 Format(instr,
2488 void Disassembler::VisitNEONByIndexedElement(const Instruction *instr) {
2495 NEONFormatDecoder nfd(instr, &map_v, &map_v, &map_s);
2496 Format(instr, mnemonic_.c_str(), nfd.Substitute(form));
2499 void Disassembler::DisassembleNEONMulByElementLong(const Instruction *instr) {
2503 NEONFormatDecoder nfd(instr,
2507 Format(instr, nfd.Mnemonic(mnemonic_.c_str()), nfd.Substitute(form));
2510 void Disassembler::DisassembleNEONDotProdByElement(const Instruction *instr) {
2511 const char *form = instr->ExtractBit(30) ? "'Vd.4s, 'Vn.16" : "'Vd.2s, 'Vn.8";
2513 Format(instr, mnemonic_.c_str(), form, suffix);
2516 void Disassembler::DisassembleNEONFPMulByElement(const Instruction *instr) {
2518 NEONFormatDecoder nfd(instr,
2522 Format(instr, mnemonic_.c_str(), nfd.Substitute(form));
2525 void Disassembler::DisassembleNEONHalfFPMulByElement(const Instruction *instr) {
2526 FormatWithDecodedMnemonic(instr,
2531 void Disassembler::DisassembleNEONFPMulByElementLong(const Instruction *instr) {
2532 FormatWithDecodedMnemonic(instr,
2538 const Instruction *instr) {
2544 NEONFormatDecoder nfd(instr,
2548 Format(instr, mnemonic_.c_str(), nfd.Substitute(form));
2551 void Disassembler::VisitNEONCopy(const Instruction *instr) {
2555 NEONFormatDecoder nfd(instr,
2576 if (instr->Mask(NEON_Q) || ((instr->GetImmNEON5() & 7) == 4)) {
2591 ((vform == kFormatS) && (instr->ExtractBit(30) == 0))) {
2607 Format(instr, mnemonic, nfd.Substitute(form));
2611 void Disassembler::VisitNEONExtract(const Instruction *instr) {
2614 NEONFormatDecoder nfd(instr, NEONFormatDecoder::LogicalFormatMap());
2615 if ((instr->GetImmNEONExt() > 7) && (instr->GetNEONQ() == 0)) {
2618 Format(instr, mnemonic, nfd.Substitute(form));
2622 void Disassembler::VisitNEONLoadStoreMultiStruct(const Instruction *instr) {
2629 NEONFormatDecoder nfd(instr, NEONFormatDecoder::LoadStoreFormatMap());
2631 switch (instr->Mask(NEONLoadStoreMultiStructMask)) {
2694 switch (instr->Mask(NEONLoadStoreMultiStructMask)) {
2702 allocated = (instr->GetNEONQ() != 0) || (instr->GetNEONLSSize() != 3);
2715 Format(instr, mnemonic, nfd.Substitute(form));
2720 const Instruction *instr) {
2728 NEONFormatDecoder nfd(instr, NEONFormatDecoder::LoadStoreFormatMap());
2730 switch (instr->Mask(NEONLoadStoreMultiStructPostIndexMask)) {
2793 switch (instr->Mask(NEONLoadStoreMultiStructPostIndexMask)) {
2801 allocated = (instr->GetNEONQ() != 0) || (instr->GetNEONLSSize() != 3);
2814 Format(instr, mnemonic, nfd.Substitute(form));
2818 void Disassembler::VisitNEONLoadStoreSingleStruct(const Instruction *instr) {
2826 NEONFormatDecoder nfd(instr, NEONFormatDecoder::LoadStoreFormatMap());
2828 switch (instr->Mask(NEONLoadStoreSingleStructMask)) {
2840 form = ((instr->GetNEONLSSize() & 1) == 0) ? form_1s : form_1d;
2853 form = ((instr->GetNEONLSSize() & 1) == 0) ? form_1s : form_1d;
2861 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld2" : "st2";
2866 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld2" : "st2";
2873 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld2" : "st2";
2874 if ((instr->GetNEONLSSize() & 1) == 0) {
2886 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld3" : "st3";
2891 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld3" : "st3";
2896 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld3" : "st3";
2897 if ((instr->GetNEONLSSize() & 1) == 0) {
2909 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld4" : "st4";
2914 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld4" : "st4";
2921 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld4" : "st4";
2922 if ((instr->GetNEONLSSize() & 1) == 0) {
2938 switch (instr->Mask(NEONLoadStoreSingleStructMask)) {
2948 allocated = ((instr->GetNEONLSSize() & 1) == 0);
2959 allocated = (instr->GetNEONLSSize() <= 1) &&
2960 ((instr->GetNEONLSSize() == 0) || (instr->GetNEONS() == 0));
2967 allocated = (instr->GetNEONS() == 0);
2980 Format(instr, mnemonic, nfd.Substitute(form));
2985 const Instruction *instr) {
2993 NEONFormatDecoder nfd(instr, NEONFormatDecoder::LoadStoreFormatMap());
2995 switch (instr->Mask(NEONLoadStoreSingleStructPostIndexMask)) {
3007 form = ((instr->GetNEONLSSize() & 1) == 0) ? form_1s : form_1d;
3020 form = ((instr->GetNEONLSSize() & 1) == 0) ? form_1s : form_1d;
3028 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld2" : "st2";
3033 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld2" : "st2";
3038 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld2" : "st2";
3039 if ((instr->GetNEONLSSize() & 1) == 0)
3050 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld3" : "st3";
3055 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld3" : "st3";
3060 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld3" : "st3";
3061 if ((instr->GetNEONLSSize() & 1) == 0)
3072 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld4" : "st4";
3077 mnemonic = (instr->GetLdStXLoad()) == 1 ? "ld4" : "st4";
3082 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld4" : "st4";
3083 if ((instr->GetNEONLSSize() & 1) == 0)
3098 switch (instr->Mask(NEONLoadStoreSingleStructPostIndexMask)) {
3108 allocated = ((instr->GetNEONLSSize() & 1) == 0);
3119 allocated = (instr->GetNEONLSSize() <= 1) &&
3120 ((instr->GetNEONLSSize() == 0) || (instr->GetNEONS() == 0));
3127 allocated = (instr->GetNEONS() == 0);
3140 Format(instr, mnemonic, nfd.Substitute(form));
3144 void Disassembler::VisitNEONModifiedImmediate(const Instruction *instr) {
3150 NEONFormatDecoder nfd(instr, NEONFormatDecoder::LogicalFormatMap());
3191 Format(instr, mnemonic, nfd.Substitute(form));
3195 const Instruction *instr) {
3199 if (instr->GetNEONSize() != 3) {
3207 Format(instr, mnemonic, form, suffix);
3210 void Disassembler::DisassembleNEONFPScalar2RegMisc(const Instruction *instr) {
3214 NEONFormatDecoder nfd(instr, NEONFormatDecoder::FPScalarFormatMap());
3229 Format(instr, mnemonic, nfd.SubstitutePlaceholders(form), suffix);
3232 void Disassembler::VisitNEONScalar2RegMisc(const Instruction *instr) {
3235 NEONFormatDecoder nfd(instr, NEONFormatDecoder::ScalarFormatMap());
3242 Format(instr, mnemonic, nfd.SubstitutePlaceholders(form));
3245 void Disassembler::VisitNEONScalar2RegMiscFP16(const Instruction *instr) {
3258 Format(instr, mnemonic, form, suffix);
3262 void Disassembler::VisitNEONScalar3Diff(const Instruction *instr) {
3265 NEONFormatDecoder nfd(instr,
3271 Format(instr, mnemonic, nfd.SubstitutePlaceholders(form));
3274 void Disassembler::DisassembleNEONFPScalar3Same(const Instruction *instr) {
3277 NEONFormatDecoder nfd(instr, NEONFormatDecoder::FPScalarFormatMap());
3278 Format(instr, mnemonic, nfd.SubstitutePlaceholders(form));
3281 void Disassembler::DisassembleNEONScalar3SameOnlyD(const Instruction *instr) {
3284 if (instr->GetNEONSize() != 3) {
3287 Format(instr, mnemonic, form);
3290 void Disassembler::VisitNEONScalar3Same(const Instruction *instr) {
3293 NEONFormatDecoder nfd(instr, NEONFormatDecoder::ScalarFormatMap());
3310 Format(instr, mnemonic, nfd.SubstitutePlaceholders(form));
3313 void Disassembler::VisitNEONScalar3SameFP16(const Instruction *instr) {
3314 FormatWithDecodedMnemonic(instr, "'Hd, 'Hn, 'Hm");
3317 void Disassembler::VisitNEONScalar3SameExtra(const Instruction *instr) {
3318 USE(instr);
3324 const Instruction *instr) {
3327 NEONFormatDecoder nfd(instr,
3333 Format(instr,
3338 void Disassembler::DisassembleNEONFPScalarMulIndex(const Instruction *instr) {
3342 NEONFormatDecoder nfd(instr, &map);
3343 Format(instr,
3348 void Disassembler::VisitNEONScalarByIndexedElement(const Instruction *instr) {
3351 NEONFormatDecoder nfd(instr, NEONFormatDecoder::ScalarFormatMap());
3356 Format(instr,
3362 void Disassembler::VisitNEONScalarCopy(const Instruction *instr) {
3366 NEONFormatDecoder nfd(instr, NEONFormatDecoder::TriangularScalarFormatMap());
3368 if (instr->Mask(NEONScalarCopyMask) == NEON_DUP_ELEMENT_scalar) {
3373 Format(instr, mnemonic, nfd.Substitute(form, nfd.kPlaceholder, nfd.kFormat));
3377 void Disassembler::VisitNEONScalarPairwise(const Instruction *instr) {
3382 if (instr->GetNEONSize() != 3) {
3385 Format(instr, mnemonic, "'Dd, 'Vn.2d");
3388 NEONFormatDecoder nfd(instr,
3391 Format(instr,
3400 const Instruction *instr) {
3405 if (instr->ExtractBit(22) == 0) {
3416 Format(instr, mnemonic, form, suffix);
3420 const Instruction *instr) {
3427 NEONFormatDecoder nfd(instr, &map_dst, &map_src);
3428 Format(instr, mnemonic, nfd.SubstitutePlaceholders(form));
3431 void Disassembler::VisitNEONScalarShiftImmediate(const Instruction *instr) {
3443 NEONFormatDecoder nfd(instr, &map);
3455 Format(instr, mnemonic, nfd.SubstitutePlaceholders(form), suffix);
3458 void Disassembler::DisassembleNEONShiftLeftLongImm(const Instruction *instr) {
3463 NEONFormatDecoder nfd(instr,
3467 if (instr->GetImmNEONImmb() == 0 &&
3468 CountSetBits(instr->GetImmNEONImmh(), 32) == 1) { // xtl variant.
3474 Format(instr, nfd.Mnemonic(mnemonic), nfd.Substitute(form), suffix);
3477 void Disassembler::DisassembleNEONShiftRightImm(const Instruction *instr) {
3480 NEONFormatDecoder nfd(instr, NEONFormatDecoder::ShiftImmFormatMap());
3496 Format(instr, mnemonic, nfd.Substitute(form));
3500 const Instruction *instr) {
3504 NEONFormatDecoder nfd(instr,
3507 Format(instr, nfd.Mnemonic(mnemonic), nfd.Substitute(form));
3510 void Disassembler::VisitNEONShiftImmediate(const Instruction *instr) {
3513 NEONFormatDecoder nfd(instr, NEONFormatDecoder::ShiftImmFormatMap());
3514 Format(instr, mnemonic, nfd.Substitute(form));
3518 void Disassembler::VisitNEONTable(const Instruction *instr) {
3527 NEONFormatDecoder nfd(instr, NEONFormatDecoder::LogicalFormatMap());
3546 int reg_num = instr->GetRn();
3554 Format(instr, mnemonic, nfd.Substitute(re_form));
3558 void Disassembler::VisitNEONPerm(const Instruction *instr) {
3559 NEONFormatDecoder nfd(instr);
3560 FormatWithDecodedMnemonic(instr, nfd.Substitute("'Vd.%s, 'Vn.%s, 'Vm.%s"));
3563 void Disassembler::Disassemble_Vd4S_Vn16B_Vm16B(const Instruction *instr) {
3564 FormatWithDecodedMnemonic(instr, "'Vd.4s, 'Vn.16b, 'Vm.16b");
3569 const Instruction *instr) {
3570 FormatWithDecodedMnemonic(instr,
3575 const Instruction *instr) {
3576 FormatWithDecodedMnemonic(instr,
3581 const Instruction *instr) {
3582 FormatWithDecodedMnemonic(instr,
3587 const Instruction *instr) {
3606 if (instr->ExtractBits(20, 16) != 0) form = form_imm;
3608 Format(instr, mnemonic, form);
3612 const Instruction *instr) {
3618 instr->Mask(SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsMask)) {
3639 Format(instr, mnemonic, form, suffix);
3643 const Instruction *instr) {
3644 const char *form = (instr->ExtractBits(20, 16) != 0)
3647 FormatWithDecodedMnemonic(instr, form);
3651 const Instruction *instr) {
3652 FormatWithDecodedMnemonic(instr,
3657 const Instruction *instr) {
3658 FormatWithDecodedMnemonic(instr, "{'Zt.s}, 'Pgl, ['Xns, 'Zm.s, '?14:suxtw]");
3662 const Instruction *instr) {
3667 bool is_zero = instr->ExtractBits(20, 16) == 0;
3669 switch (instr->Mask(SVE32BitScatterStore_VectorPlusImmMask)) {
3686 Format(instr, mnemonic, form, suffix);
3690 const Instruction *instr) {
3691 FormatWithDecodedMnemonic(instr,
3697 const Instruction *instr) {
3698 FormatWithDecodedMnemonic(instr,
3703 const Instruction *instr) {
3704 FormatWithDecodedMnemonic(instr, "{'Zt.d}, 'Pgl/z, ['Xns, 'Zm.d]");
3709 const Instruction *instr) {
3710 FormatWithDecodedMnemonic(instr,
3715 const Instruction *instr) {
3722 if (instr->ExtractBits(20, 16) != 0) {
3723 unsigned msz = instr->ExtractBits(24, 23);
3724 bool sign_extend = instr->ExtractBit(14) == 0;
3733 FormatWithDecodedMnemonic(instr, form);
3737 const Instruction *instr) {
3752 FormatWithDecodedMnemonic(instr, form, suffix);
3757 const Instruction *instr) {
3772 FormatWithDecodedMnemonic(instr, form, suffix);
3776 const Instruction *instr) {
3777 const char *form = (instr->ExtractBits(20, 16) != 0)
3781 FormatWithDecodedMnemonic(instr, form);
3785 const Instruction *instr) {
3786 FormatWithDecodedMnemonic(instr, "{'Zt.d}, 'Pgl, ['Xns, 'Zm.d, lsl #'u2423]");
3790 const Instruction *instr) {
3791 FormatWithDecodedMnemonic(instr, "{'Zt.d}, 'Pgl, ['Xns, 'Zm.d]");
3796 const Instruction *instr) {
3797 FormatWithDecodedMnemonic(instr,
3803 const Instruction *instr) {
3804 FormatWithDecodedMnemonic(instr, "{'Zt.d}, 'Pgl, ['Xns, 'Zm.d, '?14:suxtw]");
3808 const Instruction *instr) {
3812 if (instr->ExtractBits(20, 16) != 0) {
3828 FormatWithDecodedMnemonic(instr, form, suffix);
3832 const Instruction *instr) {
3833 if (instr->GetSVEImmLogical() == 0) {
3835 Format(instr, "unallocated", "(SVEBitwiseImm)");
3837 FormatWithDecodedMnemonic(instr, "'Zd.'tl, 'Zd.'tl, 'ITriSvel");
3841 void Disassembler::VisitSVEBitwiseLogical_Predicated(const Instruction *instr) {
3842 FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.'t");
3846 const Instruction *instr) {
3850 unsigned tsize = (instr->ExtractBits(23, 22) << 2) | instr->ExtractBits(9, 8);
3876 Format(instr, mnemonic, form, suffix);
3880 const Instruction *instr) {
3881 FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.'t");
3885 const Instruction *instr) {
3886 if (instr->GetSVESize() == kDRegSizeInBytesLog2) {
3887 Format(instr, "unallocated", "(SVEBitwiseShiftByWideElements_Predicated)");
3889 FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.d");
3974 void Disassembler::VisitSVEBroadcastBitmaskImm(const Instruction *instr) {
3978 switch (instr->Mask(SVEBroadcastBitmaskImmMask)) {
3980 uint64_t imm = instr->GetSVEImmLogical();
3982 int lane_size = instr->GetSVEBitwiseImmLaneSizeInBytesLog2();
3991 Format(instr, mnemonic, form);
3995 const Instruction *instr) {
3999 if (instr->GetSVEVectorFormat() != kFormatVnB) {
4000 switch (instr->Mask(SVEBroadcastFPImm_UnpredicatedMask)) {
4010 Format(instr, mnemonic, form);
4013 void Disassembler::VisitSVEBroadcastGeneralRegister(const Instruction *instr) {
4017 switch (instr->Mask(SVEBroadcastGeneralRegisterMask)) {
4021 if (instr->GetSVESize() == kDRegSizeInBytesLog2) {
4030 Format(instr, mnemonic, form);
4033 void Disassembler::VisitSVEBroadcastIndexElement(const Instruction *instr) {
4037 switch (instr->Mask(SVEBroadcastIndexElementMask)) {
4040 int tsz = instr->ExtractBits(20, 16);
4044 int imm2 = instr->ExtractBits(23, 22);
4058 Format(instr, mnemonic, form);
4062 const Instruction *instr) {
4066 switch (instr->Mask(SVEBroadcastIntImm_UnpredicatedMask)) {
4069 if ((instr->GetSVEVectorFormat() == kFormatVnB) &&
4070 (instr->ExtractBit(13) == 1))
4075 form = (instr->ExtractBit(13) == 0) ? "'Zd.'t, #'s1205"
4081 Format(instr, mnemonic, form);
4084 void Disassembler::VisitSVECompressActiveElements(const Instruction *instr) {
4087 if (instr->ExtractBit(23) == 1) {
4088 FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Pgl, 'Zn.'t");
4090 VisitUnallocated(instr);
4095 const Instruction *instr) {
4096 FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Pgl, 'Zd.'t, 'Zn.'t");
4100 const Instruction *instr) {
4103 if (instr->GetSVESize() == kDRegSizeInBytesLog2) {
4106 FormatWithDecodedMnemonic(instr, form);
4110 const Instruction *instr) {
4111 FormatWithDecodedMnemonic(instr, "'t'u0400, 'Pgl, 't'u0400, 'Zn.'t");
4115 const Instruction *instr) {
4116 const char *form = (instr->ExtractBit(22) == 0) ? "'Wn, 'Wm" : "'Xn, 'Xm";
4117 FormatWithDecodedMnemonic(instr, form);
4121 const Instruction *instr) {
4122 FormatWithDecodedMnemonic(instr, "'Zd, 'Zn");
4126 const Instruction *instr) {
4130 if (instr->GetRm() != kZeroRegCode) {
4159 FormatWithDecodedMnemonic(instr, form, suffix);
4163 const Instruction *instr) {
4166 (instr->ExtractBits(19, 16) == 0) ? "]" : ", #'s1916, mul vl]";
4167 FormatWithDecodedMnemonic(instr, form, suffix);
4171 const Instruction *instr) {
4174 (instr->ExtractBits(19, 16) == 0) ? "]" : ", #'s1916, mul vl]";
4186 FormatWithDecodedMnemonic(instr, form, suffix);
4190 const Instruction *instr) {
4203 FormatWithDecodedMnemonic(instr, form);
4207 const Instruction *instr) {
4210 (instr->ExtractBits(19, 16) == 0) ? "]" : ", #'s1916, mul vl]";
4223 FormatWithDecodedMnemonic(instr, form, suffix);
4227 const Instruction *instr) {
4231 switch (instr->Mask(SVEContiguousNonTemporalStore_ScalarPlusScalarMask)) {
4251 Format(instr, mnemonic, form);
4255 const Instruction *instr) {
4256 const char *form = (instr->ExtractBits(21, 16) != 0)
4259 FormatWithDecodedMnemonic(instr, form);
4263 const Instruction *instr) {
4267 if (instr->GetRm() != kZeroRegCode) {
4268 switch (instr->Mask(SVEContiguousPrefetch_ScalarPlusScalarMask)) {
4289 Format(instr, mnemonic, form);
4293 const Instruction *instr) {
4296 if (instr->ExtractBits(19, 16) == 0) {
4299 FormatWithDecodedMnemonic(instr, form);
4303 const Instruction *instr) {
4305 FormatWithDecodedMnemonic(instr, "{'Zt.'tls}, 'Pgl, ['Xns, 'Xm'NSveS]");
4308 void Disassembler::VisitSVECopyFPImm_Predicated(const Instruction *instr) {
4312 if (instr->GetSVEVectorFormat() != kFormatVnB) {
4313 switch (instr->Mask(SVECopyFPImm_PredicatedMask)) {
4323 Format(instr, mnemonic, form);
4327 const Instruction *instr) {
4331 switch (instr->Mask(SVECopyGeneralRegisterToVector_PredicatedMask)) {
4336 if (instr->GetSVESize() == kXRegSizeInBytesLog2) {
4343 Format(instr, mnemonic, form);
4346 void Disassembler::VisitSVECopyIntImm_Predicated(const Instruction *instr) {
4351 switch (instr->Mask(SVECopyIntImm_PredicatedMask)) {
4356 if (instr->ExtractBit(13) != 0) suffix = ", lsl #8";
4362 Format(instr, mnemonic, form, suffix);
4366 const Instruction *instr) {
4370 switch (instr->Mask(SVECopySIMDFPScalarRegisterToVector_PredicatedMask)) {
4379 Format(instr, mnemonic, form);
4383 const Instruction *instr) {
4385 if (instr->GetSVESize() == kDRegSizeInBytesLog2) {
4388 FormatWithDecodedMnemonic(instr, form);
4392 const Instruction *instr) {
4393 FormatWithDecodedMnemonic(instr, "'t'u0400, 'Pgl, 'Zn.'t");
4396 void Disassembler::VisitSVEFFRInitialise(const Instruction *instr) {
4397 DisassembleNoArgs(instr);
4400 void Disassembler::VisitSVEFFRWriteFromPredicate(const Instruction *instr) {
4401 FormatWithDecodedMnemonic(instr, "'Pn.b");
4405 const Instruction *instr) {
4411 int i1 = instr->ExtractBit(5);
4414 if (instr->GetSVEVectorFormat() == kFormatVnB) {
4415 VisitUnallocated(instr);
4429 FormatWithDecodedMnemonic(instr, form, suffix);
4432 void Disassembler::VisitSVEFPArithmetic_Predicated(const Instruction *instr) {
4433 if (instr->GetSVEVectorFormat() == kFormatVnB) {
4434 VisitUnallocated(instr);
4436 FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.'t");
4440 void Disassembler::VisitSVEFPConvertPrecision(const Instruction *instr) {
4463 FormatWithDecodedMnemonic(instr, form);
4466 void Disassembler::VisitSVEFPConvertToInt(const Instruction *instr) {
4499 FormatWithDecodedMnemonic(instr, form);
4502 void Disassembler::VisitSVEFPExponentialAccelerator(const Instruction *instr) {
4503 unsigned size = instr->GetSVESize();
4506 FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Zn.'t");
4508 VisitUnallocated(instr);
4512 void Disassembler::VisitSVEFPRoundToIntegralValue(const Instruction *instr) {
4513 if (instr->GetSVEVectorFormat() == kFormatVnB) {
4514 VisitUnallocated(instr);
4516 FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Pgl/m, 'Zn.'t");
4520 void Disassembler::VisitSVEFPTrigMulAddCoefficient(const Instruction *instr) {
4521 unsigned size = instr->GetSVESize();
4524 FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Zd.'t, 'Zn.'t, #'u1816");
4526 VisitUnallocated(instr);
4530 void Disassembler::VisitSVEFPTrigSelectCoefficient(const Instruction *instr) {
4531 unsigned size = instr->GetSVESize();
4534 FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Zn.'t, 'Zm.'t");
4536 VisitUnallocated(instr);
4540 void Disassembler::VisitSVEFPUnaryOp(const Instruction *instr) {
4541 if (instr->GetSVESize() == kBRegSizeInBytesLog2) {
4542 VisitUnallocated(instr);
4544 FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Pgl/m, 'Zn.'t");
4548 static const char *IncDecFormHelper(const Instruction *instr,
4552 if (instr->ExtractBits(19, 16) == 0) {
4553 if (instr->ExtractBits(9, 5) == SVE_ALL) {
4565 const Instruction *instr) {
4567 IncDecFormHelper(instr, "'Xd, 'Ipc, mul #'u1916+1", "'Xd, 'Ipc", "'Xd");
4568 FormatWithDecodedMnemonic(instr, form);
4572 const Instruction *instr) {
4573 const char *form = IncDecFormHelper(instr,
4577 FormatWithDecodedMnemonic(instr, form);
4580 void Disassembler::VisitSVEInsertGeneralRegister(const Instruction *instr) {
4582 if (instr->GetSVESize() == kDRegSizeInBytesLog2) {
4585 FormatWithDecodedMnemonic(instr, form);
4589 const Instruction *instr) {
4590 FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Vnv");
4594 const Instruction *instr) {
4595 const char *form = (instr->ExtractBit(13) == 0)
4598 FormatWithDecodedMnemonic(instr, form);
4602 const Instruction *instr) {
4603 FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.'t");
4607 const Instruction *instr) {
4609 (instr->ExtractBit(12) == 0) ? "'Pd.'t, 'Wn, 'Wm" : "'Pd.'t, 'Xn, 'Xm";
4610 FormatWithDecodedMnemonic(instr, form);
4613 void Disassembler::VisitSVEIntConvertToFP(const Instruction *instr) {
4645 FormatWithDecodedMnemonic(instr, form);
4649 const Instruction *instr) {
4650 unsigned size = instr->GetSVESize();
4652 FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.'t");
4654 VisitUnallocated(instr);
4659 const Instruction *instr) {
4660 FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.'t");
4663 void Disassembler::VisitSVEIntMinMaxImm_Unpredicated(const Instruction *instr) {
4673 FormatWithDecodedMnemonic(instr, form, suffix);
4676 void Disassembler::VisitSVEIntMulImm_Unpredicated(const Instruction *instr) {
4677 FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Zd.'t, #'s1205");
4680 void Disassembler::VisitSVEIntMulVectors_Predicated(const Instruction *instr) {
4681 FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.'t");
4684 void Disassembler::VisitSVELoadAndBroadcastElement(const Instruction *instr) {
4742 if (instr->ExtractBits(21, 16) == 0) {
4746 FormatWithDecodedMnemonic(instr, form, suffix);
4750 const Instruction *instr) {
4762 if (instr->ExtractBits(19, 16) == 0) suffix = "]";
4764 FormatWithDecodedMnemonic(instr, form, suffix);
4768 const Instruction *instr) {
4778 FormatWithDecodedMnemonic(instr, form, suffix);
4782 const Instruction *instr) {
4802 FormatWithDecodedMnemonic(instr, form, suffix);
4806 const Instruction *instr) {
4826 FormatWithDecodedMnemonic(instr, form, suffix);
4829 void Disassembler::VisitSVELoadPredicateRegister(const Instruction *instr) {
4831 if (instr->Mask(0x003f1c00) == 0) {
4834 FormatWithDecodedMnemonic(instr, form);
4837 void Disassembler::VisitSVELoadVectorRegister(const Instruction *instr) {
4839 if (instr->Mask(0x003f1c00) == 0) {
4842 FormatWithDecodedMnemonic(instr, form);
4845 void Disassembler::VisitSVEPartitionBreakCondition(const Instruction *instr) {
4846 FormatWithDecodedMnemonic(instr, "'Pd.b, p'u1310/'?04:mz, 'Pn.b");
4849 void Disassembler::VisitSVEPermutePredicateElements(const Instruction *instr) {
4850 FormatWithDecodedMnemonic(instr, "'Pd.'t, 'Pn.'t, 'Pm.'t");
4853 void Disassembler::VisitSVEPredicateFirstActive(const Instruction *instr) {
4854 FormatWithDecodedMnemonic(instr, "'Pd.b, 'Pn, 'Pd.b");
4858 const Instruction *instr) {
4859 FormatWithDecodedMnemonic(instr, "'Pd.b");
4862 void Disassembler::VisitSVEPredicateTest(const Instruction *instr) {
4863 FormatWithDecodedMnemonic(instr, "p'u1310, 'Pn.b");
4866 void Disassembler::VisitSVEPredicateZero(const Instruction *instr) {
4867 FormatWithDecodedMnemonic(instr, "'Pd.b");
4871 const Instruction *instr) {
4872 FormatWithDecodedMnemonic(instr, "'Pd.b, p'u1310/z, 'Pn.b, 'Pd.b");
4875 void Disassembler::VisitSVEReversePredicateElements(const Instruction *instr) {
4876 FormatWithDecodedMnemonic(instr, "'Pd.'t, 'Pn.'t");
4879 void Disassembler::VisitSVEReverseVectorElements(const Instruction *instr) {
4880 FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Zn.'t");
4883 void Disassembler::VisitSVEReverseWithinElements(const Instruction *instr) {
4887 unsigned size = instr->GetSVESize();
4888 switch (instr->Mask(SVEReverseWithinElementsMask)) {
4917 Format(instr, mnemonic, form);
4921 const Instruction *instr) {
4922 const char *form = IncDecFormHelper(instr,
4926 const char *form_sx = IncDecFormHelper(instr,
4943 FormatWithDecodedMnemonic(instr, form);
4947 const Instruction *instr) {
4948 const char *form = IncDecFormHelper(instr,
4952 FormatWithDecodedMnemonic(instr, form);
4956 const Instruction *instr) {
4976 FormatWithDecodedMnemonic(instr, form, suffix);
4980 const Instruction *instr) {
5000 FormatWithDecodedMnemonic(instr, form, suffix);
5003 void Disassembler::VisitSVEStorePredicateRegister(const Instruction *instr) {
5005 if (instr->Mask(0x003f1c00) == 0) {
5008 FormatWithDecodedMnemonic(instr, form);
5011 void Disassembler::VisitSVEStoreVectorRegister(const Instruction *instr) {
5013 if (instr->Mask(0x003f1c00) == 0) {
5016 FormatWithDecodedMnemonic(instr, form);
5019 void Disassembler::VisitSVETableLookup(const Instruction *instr) {
5020 FormatWithDecodedMnemonic(instr, "'Zd.'t, {'Zn.'t}, 'Zm.'t");
5023 void Disassembler::VisitSVEUnpackPredicateElements(const Instruction *instr) {
5024 FormatWithDecodedMnemonic(instr, "'Pd.h, 'Pn.b");
5027 void Disassembler::VisitSVEUnpackVectorElements(const Instruction *instr) {
5028 if (instr->GetSVESize() == 0) {
5030 VisitUnallocated(instr);
5032 FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Zn.'th");
5036 void Disassembler::VisitSVEVectorSplice(const Instruction *instr) {
5037 FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Pgl, 'Zd.'t, 'Zn.'t");
5040 void Disassembler::VisitSVEAddressGeneration(const Instruction *instr) {
5045 bool msz_is_zero = (instr->ExtractBits(11, 10) == 0);
5047 switch (instr->Mask(SVEAddressGenerationMask)) {
5064 Format(instr, mnemonic, form, suffix);
5068 const Instruction *instr) {
5072 switch (instr->Mask(SVEBitwiseLogicalUnpredicatedMask)) {
5084 if (instr->GetRn() == instr->GetRm()) {
5092 Format(instr, mnemonic, form);
5095 void Disassembler::VisitSVEBitwiseShiftUnpredicated(const Instruction *instr) {
5099 (instr->ExtractBits(23, 22) << 2) | instr->ExtractBits(20, 19);
5100 unsigned lane_size = instr->GetSVESize();
5141 Format(instr, mnemonic, form, suffix);
5144 void Disassembler::VisitSVEElementCount(const Instruction *instr) {
5146 IncDecFormHelper(instr, "'Xd, 'Ipc, mul #'u1916+1", "'Xd, 'Ipc", "'Xd");
5147 FormatWithDecodedMnemonic(instr, form);
5150 void Disassembler::VisitSVEFPAccumulatingReduction(const Instruction *instr) {
5151 if (instr->GetSVEVectorFormat() == kFormatVnB) {
5152 VisitUnallocated(instr);
5154 FormatWithDecodedMnemonic(instr, "'t'u0400, 'Pgl, 't'u0400, 'Zn.'t");
5158 void Disassembler::VisitSVEFPArithmeticUnpredicated(const Instruction *instr) {
5159 if (instr->GetSVEVectorFormat() == kFormatVnB) {
5160 VisitUnallocated(instr);
5162 FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Zn.'t, 'Zm.'t");
5166 void Disassembler::VisitSVEFPCompareVectors(const Instruction *instr) {
5167 if (instr->GetSVEVectorFormat() == kFormatVnB) {
5168 VisitUnallocated(instr);
5170 FormatWithDecodedMnemonic(instr, "'Pd.'t, 'Pgl/z, 'Zn.'t, 'Zm.'t");
5174 void Disassembler::VisitSVEFPCompareWithZero(const Instruction *instr) {
5175 if (instr->GetSVEVectorFormat() == kFormatVnB) {
5176 VisitUnallocated(instr);
5178 FormatWithDecodedMnemonic(instr, "'Pd.'t, 'Pgl/z, 'Zn.'t, #0.0");
5182 void Disassembler::VisitSVEFPComplexAddition(const Instruction *instr) {
5185 if (instr->GetSVEVectorFormat() == kFormatVnB) {
5186 VisitUnallocated(instr);
5188 FormatWithDecodedMnemonic(instr, form);
5192 void Disassembler::VisitSVEFPComplexMulAdd(const Instruction *instr) {
5194 if (instr->GetSVEVectorFormat() == kFormatVnB) {
5195 VisitUnallocated(instr);
5197 FormatWithDecodedMnemonic(instr, form);
5201 void Disassembler::VisitSVEFPComplexMulAddIndex(const Instruction *instr) {
5209 FormatWithDecodedMnemonic(instr, form, suffix);
5212 void Disassembler::VisitSVEFPFastReduction(const Instruction *instr) {
5213 if (instr->GetSVEVectorFormat() == kFormatVnB) {
5214 VisitUnallocated(instr);
5216 FormatWithDecodedMnemonic(instr, "'t'u0400, 'Pgl, 'Zn.'t");
5220 void Disassembler::VisitSVEFPMulIndex(const Instruction *instr) {
5230 FormatWithDecodedMnemonic(instr, form);
5233 void Disassembler::VisitSVEFPMulAdd(const Instruction *instr) {
5234 if (instr->GetSVEVectorFormat() == kFormatVnB) {
5235 VisitUnallocated(instr);
5237 FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Pgl/m, 'Zn.'t, 'Zm.'t");
5241 void Disassembler::VisitSVEFPMulAddIndex(const Instruction *instr) {
5253 FormatWithDecodedMnemonic(instr, form);
5256 void Disassembler::VisitSVEFPUnaryOpUnpredicated(const Instruction *instr) {
5257 if (instr->GetSVEVectorFormat() == kFormatVnB) {
5258 VisitUnallocated(instr);
5260 FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Zn.'t");
5264 void Disassembler::VisitSVEIncDecByPredicateCount(const Instruction *instr) {
5290 FormatWithDecodedMnemonic(instr, form);
5293 void Disassembler::VisitSVEIndexGeneration(const Instruction *instr) {
5296 static_cast<unsigned>(instr->GetSVESize()) <= kWRegSizeInBytesLog2;
5309 FormatWithDecodedMnemonic(instr, form);
5312 void Disassembler::VisitSVEIntArithmeticUnpredicated(const Instruction *instr) {
5313 FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Zn.'t, 'Zm.'t");
5316 void Disassembler::VisitSVEIntCompareSignedImm(const Instruction *instr) {
5317 FormatWithDecodedMnemonic(instr, "'Pd.'t, 'Pgl/z, 'Zn.'t, #'s2016");
5320 void Disassembler::VisitSVEIntCompareUnsignedImm(const Instruction *instr) {
5321 FormatWithDecodedMnemonic(instr, "'Pd.'t, 'Pgl/z, 'Zn.'t, #'u2014");
5324 void Disassembler::VisitSVEIntCompareVectors(const Instruction *instr) {
5337 FormatWithDecodedMnemonic(instr, form, suffix);
5340 void Disassembler::VisitSVEIntMulAddPredicated(const Instruction *instr) {
5349 FormatWithDecodedMnemonic(instr, form, suffix);
5352 void Disassembler::VisitSVEIntMulAddUnpredicated(const Instruction *instr) {
5353 if (static_cast<unsigned>(instr->GetSVESize()) >= kSRegSizeInBytesLog2) {
5354 FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Zn.'tq, 'Zm.'tq");
5356 VisitUnallocated(instr);
5360 void Disassembler::VisitSVEMovprfx(const Instruction *instr) {
5361 FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Pgl/'?16:mz, 'Zn.'t");
5364 void Disassembler::VisitSVEIntReduction(const Instruction *instr) {
5372 FormatWithDecodedMnemonic(instr, form);
5376 const Instruction *instr) {
5377 VectorFormat vform = instr->GetSVEVectorFormat();
5383 VisitUnallocated(instr);
5390 VisitUnallocated(instr);
5399 VisitUnallocated(instr);
5405 FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Pgl/m, 'Zn.'t");
5408 void Disassembler::VisitSVEMulIndex(const Instruction *instr) {
5418 FormatWithDecodedMnemonic(instr, form);
5421 void Disassembler::VisitSVEPermuteVectorExtract(const Instruction *instr) {
5422 FormatWithDecodedMnemonic(instr, "'Zd.b, 'Zd.b, 'Zn.b, #'u2016:1210");
5425 void Disassembler::VisitSVEPermuteVectorInterleaving(const Instruction *instr) {
5426 FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Zn.'t, 'Zm.'t");
5429 void Disassembler::VisitSVEPredicateCount(const Instruction *instr) {
5430 FormatWithDecodedMnemonic(instr, "'Xd, p'u1310, 'Pn.'t");
5433 void Disassembler::VisitSVEPredicateLogical(const Instruction *instr) {
5437 int pd = instr->GetPd();
5438 int pn = instr->GetPn();
5439 int pm = instr->GetPm();
5440 int pg = instr->ExtractBits(13, 10);
5488 Format(instr, mnemonic, form);
5491 void Disassembler::VisitSVEPredicateInitialize(const Instruction *instr) {
5494 if (instr->ExtractBits(9, 5) == SVE_ALL) form = "'Pd.'t";
5495 FormatWithDecodedMnemonic(instr, form);
5498 void Disassembler::VisitSVEPredicateNextActive(const Instruction *instr) {
5499 FormatWithDecodedMnemonic(instr, "'Pd.'t, 'Pn, 'Pd.'t");
5503 const Instruction *instr) {
5504 FormatWithDecodedMnemonic(instr, "'Pd.b, 'Pn/z");
5507 void Disassembler::VisitSVEPropagateBreak(const Instruction *instr) {
5508 FormatWithDecodedMnemonic(instr, "'Pd.b, p'u1310/z, 'Pn.b, 'Pm.b");
5511 void Disassembler::VisitSVEStackFrameAdjustment(const Instruction *instr) {
5512 FormatWithDecodedMnemonic(instr, "'Xds, 'Xms, #'s1005");
5515 void Disassembler::VisitSVEStackFrameSize(const Instruction *instr) {
5516 FormatWithDecodedMnemonic(instr, "'Xd, #'s1005");
5519 void Disassembler::VisitSVEVectorSelect(const Instruction *instr) {
5523 if (instr->GetRd() == instr->GetRm()) {
5528 Format(instr, mnemonic, form);
5532 const Instruction *instr) {
5535 (instr->ExtractBits(19, 16) == 0) ? "]" : ", #'s1916, mul vl]";
5536 FormatWithDecodedMnemonic(instr, form, suffix);
5540 const Instruction *instr) {
5562 FormatWithDecodedMnemonic(instr, form, suffix);
5565 void Disassembler::VisitReserved(const Instruction *instr) {
5567 VIXL_ASSERT(instr->Mask(ReservedMask) == UDF);
5568 Format(instr, "udf", "'IUdf");
5571 void Disassembler::VisitUnimplemented(const Instruction *instr) {
5572 Format(instr, "unimplemented", "(Unimplemented)");
5576 void Disassembler::VisitUnallocated(const Instruction *instr) {
5577 Format(instr, "unallocated", "(Unallocated)");
5580 void Disassembler::Visit(Metadata *metadata, const Instruction *instr) {
5587 VisitUnimplemented(instr);
5590 (it->second)(this, instr);
5594 void Disassembler::Disassemble_PdT_PgZ_ZnT_ZmT(const Instruction *instr) {
5596 VectorFormat vform = instr->GetSVEVectorFormat();
5599 Format(instr, "unimplemented", "(PdT_PgZ_ZnT_ZmT)");
5601 Format(instr, mnemonic_.c_str(), form);
5605 void Disassembler::Disassemble_ZdB_Zn1B_Zn2B_imm(const Instruction *instr) {
5607 Format(instr, mnemonic_.c_str(), form);
5610 void Disassembler::Disassemble_ZdB_ZnB_ZmB(const Instruction *instr) {
5612 if (instr->GetSVEVectorFormat() == kFormatVnB) {
5613 Format(instr, mnemonic_.c_str(), form);
5615 Format(instr, "unimplemented", "(ZdB_ZnB_ZmB)");
5619 void Disassembler::Disassemble_ZdD_PgM_ZnS(const Instruction *instr) {
5621 Format(instr, mnemonic_.c_str(), form);
5624 void Disassembler::Disassemble_ZdD_ZnD_ZmD(const Instruction *instr) {
5626 Format(instr, mnemonic_.c_str(), form);
5629 void Disassembler::Disassemble_ZdD_ZnD_ZmD_imm(const Instruction *instr) {
5631 Format(instr, mnemonic_.c_str(), form);
5634 void Disassembler::Disassemble_ZdD_ZnS_ZmS_imm(const Instruction *instr) {
5636 Format(instr, mnemonic_.c_str(), form);
5639 void Disassembler::Disassemble_ZdH_PgM_ZnS(const Instruction *instr) {
5641 Format(instr, mnemonic_.c_str(), form);
5644 void Disassembler::Disassemble_ZdH_ZnH_ZmH_imm(const Instruction *instr) {
5646 Format(instr, mnemonic_.c_str(), form);
5649 void Disassembler::Disassemble_ZdS_PgM_ZnD(const Instruction *instr) {
5651 Format(instr, mnemonic_.c_str(), form);
5654 void Disassembler::Disassemble_ZdS_PgM_ZnH(const Instruction *instr) {
5656 Format(instr, mnemonic_.c_str(), form);
5659 void Disassembler::Disassemble_ZdS_PgM_ZnS(const Instruction *instr) {
5661 if (instr->GetSVEVectorFormat() == kFormatVnS) {
5662 Format(instr, mnemonic_.c_str(), form);
5664 Format(instr, "unimplemented", "(ZdS_PgM_ZnS)");
5668 void Disassembler::Disassemble_ZdS_ZnH_ZmH_imm(const Instruction *instr) {
5670 Format(instr, mnemonic_.c_str(), form);
5673 void Disassembler::Disassemble_ZdS_ZnS_ZmS(const Instruction *instr) {
5675 Format(instr, mnemonic_.c_str(), form);
5678 void Disassembler::Disassemble_ZdS_ZnS_ZmS_imm(const Instruction *instr) {
5680 Format(instr, mnemonic_.c_str(), form);
5683 void Disassembler::DisassembleSVEFlogb(const Instruction *instr) {
5685 if (instr->GetSVEVectorFormat(17) == kFormatVnB) {
5686 Format(instr, "unimplemented", "(SVEFlogb)");
5688 Format(instr, mnemonic_.c_str(), form);
5692 void Disassembler::Disassemble_ZdT_PgM_ZnT(const Instruction *instr) {
5694 Format(instr, mnemonic_.c_str(), form);
5697 void Disassembler::Disassemble_ZdT_PgZ_ZnT_ZmT(const Instruction *instr) {
5699 VectorFormat vform = instr->GetSVEVectorFormat();
5701 Format(instr, mnemonic_.c_str(), form);
5703 Format(instr, "unimplemented", "(ZdT_PgZ_ZnT_ZmT)");
5707 void Disassembler::Disassemble_ZdT_Pg_Zn1T_Zn2T(const Instruction *instr) {
5709 Format(instr, mnemonic_.c_str(), form);
5712 void Disassembler::Disassemble_ZdT_Zn1T_Zn2T_ZmT(const Instruction *instr) {
5714 Format(instr, mnemonic_.c_str(), form);
5717 void Disassembler::Disassemble_ZdT_ZnT_ZmT(const Instruction *instr) {
5719 Format(instr, mnemonic_.c_str(), form);
5722 void Disassembler::Disassemble_ZdT_ZnT_ZmTb(const Instruction *instr) {
5724 if (instr->GetSVEVectorFormat() == kFormatVnB) {
5725 Format(instr, "unimplemented", "(ZdT_ZnT_ZmTb)");
5727 Format(instr, mnemonic_.c_str(), form);
5731 void Disassembler::Disassemble_ZdT_ZnTb(const Instruction *instr) {
5734 instr->GetSVEImmShiftAndLaneSizeLog2(/* is_predicated = */ false);
5743 Format(instr, mnemonic_.c_str(), form);
5745 Format(instr, "unimplemented", "(ZdT_ZnTb)");
5749 void Disassembler::Disassemble_ZdT_ZnTb_ZmTb(const Instruction *instr) {
5751 if (instr->GetSVEVectorFormat() == kFormatVnB) {
5755 Format(instr, "unimplemented", "(ZdT_ZnTb_ZmTb)");
5757 Format(instr, mnemonic_.c_str(), form);
5761 void Disassembler::DisassembleSVEAddSubHigh(const Instruction *instr) {
5763 if (instr->GetSVEVectorFormat() == kFormatVnB) {
5764 Format(instr, "unimplemented", "(SVEAddSubHigh)");
5766 Format(instr, mnemonic_.c_str(), form);
5770 void Disassembler::DisassembleSVEShiftLeftImm(const Instruction *instr) {
5773 instr->GetSVEImmShiftAndLaneSizeLog2(/* is_predicated = */ false);
5777 Format(instr, mnemonic_.c_str(), form);
5779 Format(instr, "unimplemented", "(SVEShiftLeftImm)");
5783 void Disassembler::DisassembleSVEShiftRightImm(const Instruction *instr) {
5786 instr->GetSVEImmShiftAndLaneSizeLog2(/* is_predicated = */ false);
5790 Format(instr, mnemonic_.c_str(), form);
5792 Format(instr, "unimplemented", "(SVEShiftRightImm)");
5796 void Disassembler::Disassemble_ZdaD_ZnD_ZmD_imm(const Instruction *instr) {
5798 Format(instr, mnemonic_.c_str(), form);
5802 const Instruction *instr) {
5804 Format(instr, mnemonic_.c_str(), form);
5807 void Disassembler::Disassemble_ZdaD_ZnS_ZmS_imm(const Instruction *instr) {
5809 Format(instr, mnemonic_.c_str(), form);
5812 void Disassembler::Disassemble_ZdaH_ZnH_ZmH_imm(const Instruction *instr) {
5814 Format(instr, mnemonic_.c_str(), form);
5818 const Instruction *instr) {
5820 Format(instr, mnemonic_.c_str(), form);
5823 void Disassembler::Disassemble_ZdaS_ZnB_ZmB(const Instruction *instr) {
5825 Format(instr, mnemonic_.c_str(), form);
5829 const Instruction *instr) {
5831 Format(instr, mnemonic_.c_str(), form);
5834 void Disassembler::Disassemble_ZdaS_ZnH_ZmH(const Instruction *instr) {
5836 Format(instr, mnemonic_.c_str(), form);
5839 void Disassembler::Disassemble_ZdaS_ZnH_ZmH_imm(const Instruction *instr) {
5841 Format(instr, mnemonic_.c_str(), form);
5844 void Disassembler::Disassemble_ZdaS_ZnS_ZmS_imm(const Instruction *instr) {
5846 Format(instr, mnemonic_.c_str(), form);
5850 const Instruction *instr) {
5852 Format(instr, mnemonic_.c_str(), form);
5855 void Disassembler::Disassemble_ZdaT_PgM_ZnTb(const Instruction *instr) {
5858 if (instr->GetSVESize() == 0) {
5860 Format(instr, "unimplemented", "(Disassemble_ZdaT_PgM_ZnTb)");
5864 Format(instr, mnemonic_.c_str(), form);
5867 void Disassembler::DisassembleSVEAddSubCarry(const Instruction *instr) {
5869 Format(instr, mnemonic_.c_str(), form);
5872 void Disassembler::Disassemble_ZdaT_ZnT_ZmT(const Instruction *instr) {
5874 Format(instr, mnemonic_.c_str(), form);
5877 void Disassembler::Disassemble_ZdaT_ZnT_ZmT_const(const Instruction *instr) {
5879 Format(instr, mnemonic_.c_str(), form);
5882 void Disassembler::Disassemble_ZdaT_ZnTb_ZmTb(const Instruction *instr) {
5884 if (instr->GetSVEVectorFormat() == kFormatVnB) {
5885 Format(instr, "unimplemented", "(ZdaT_ZnTb_ZmTb)");
5887 Format(instr, mnemonic_.c_str(), form);
5891 void Disassembler::Disassemble_ZdaT_ZnTb_ZmTb_const(const Instruction *instr) {
5893 VectorFormat vform = instr->GetSVEVectorFormat();
5896 Format(instr, "unimplemented", "(ZdaT_ZnTb_ZmTb_const)");
5898 Format(instr, mnemonic_.c_str(), form);
5902 void Disassembler::Disassemble_ZdnB_ZdnB(const Instruction *instr) {
5904 Format(instr, mnemonic_.c_str(), form);
5907 void Disassembler::Disassemble_ZdnB_ZdnB_ZmB(const Instruction *instr) {
5909 Format(instr, mnemonic_.c_str(), form);
5912 void Disassembler::DisassembleSVEBitwiseTernary(const Instruction *instr) {
5914 Format(instr, mnemonic_.c_str(), form);
5917 void Disassembler::Disassemble_ZdnS_ZdnS_ZmS(const Instruction *instr) {
5919 Format(instr, mnemonic_.c_str(), form);
5922 void Disassembler::DisassembleSVEFPPair(const Instruction *instr) {
5924 if (instr->GetSVEVectorFormat() == kFormatVnB) {
5925 Format(instr, "unimplemented", "(SVEFPPair)");
5927 Format(instr, mnemonic_.c_str(), form);
5931 void Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT(const Instruction *instr) {
5933 Format(instr, mnemonic_.c_str(), form);
5936 void Disassembler::DisassembleSVEComplexIntAddition(const Instruction *instr) {
5938 const char *suffix = (instr->ExtractBit(10) == 0) ? "90" : "270";
5939 Format(instr, mnemonic_.c_str(), form, suffix);
5942 void Disassembler::Disassemble_ZdnT_ZdnT_ZmT_const(const Instruction *instr) {
5945 (instr->ExtractBits(23, 22) << 2) | instr->ExtractBits(20, 19);
5948 Format(instr, "unimplemented", "(ZdnT_ZdnT_ZmT_const)");
5950 Format(instr, mnemonic_.c_str(), form);
5954 void Disassembler::Disassemble_ZtD_PgZ_ZnD_Xm(const Instruction *instr) {
5956 const char *suffix = instr->GetRm() == 31 ? "]" : ", 'Xm]";
5957 Format(instr, mnemonic_.c_str(), form, suffix);
5960 void Disassembler::Disassemble_ZtD_Pg_ZnD_Xm(const Instruction *instr) {
5962 const char *suffix = instr->GetRm() == 31 ? "]" : ", 'Xm]";
5963 Format(instr, mnemonic_.c_str(), form, suffix);
5966 void Disassembler::Disassemble_ZtS_PgZ_ZnS_Xm(const Instruction *instr) {
5968 const char *suffix = instr->GetRm() == 31 ? "]" : ", 'Xm]";
5969 Format(instr, mnemonic_.c_str(), form, suffix);
5972 void Disassembler::Disassemble_ZtS_Pg_ZnS_Xm(const Instruction *instr) {
5974 const char *suffix = instr->GetRm() == 31 ? "]" : ", 'Xm]";
5975 Format(instr, mnemonic_.c_str(), form, suffix);
5978 void Disassembler::Disassemble_XdSP_XnSP_Xm(const Instruction *instr) {
5980 const char *suffix = instr->GetRm() == 31 ? "" : ", 'Xm";
5981 Format(instr, mnemonic_.c_str(), form, suffix);
5984 void Disassembler::Disassemble_XdSP_XnSP_uimm6_uimm4(const Instruction *instr) {
5987 Format(instr, mnemonic_.c_str(), form);
5990 void Disassembler::Disassemble_Xd_XnSP_Xm(const Instruction *instr) {
5992 Format(instr, mnemonic_.c_str(), form);
5995 void Disassembler::Disassemble_Xd_XnSP_XmSP(const Instruction *instr) {
5996 if ((form_hash_ == Hash("subps_64s_dp_2src")) && (instr->GetRd() == 31)) {
5997 Format(instr, "cmpp", "'Xns, 'Xms");
6000 Format(instr, mnemonic_.c_str(), form);
6004 void Disassembler::DisassembleMTEStoreTagPair(const Instruction *instr) {
6022 if (instr->GetImmLSPair() == 0) {
6026 Format(instr, mnemonic_.c_str(), form, suffix);
6029 void Disassembler::DisassembleMTEStoreTag(const Instruction *instr) {
6056 if (instr->GetImmLS() == 0) {
6060 Format(instr, mnemonic_.c_str(), form, suffix);
6063 void Disassembler::DisassembleMTELoadTag(const Instruction *instr) {
6065 (instr->GetImmLS() == 0) ? "'Xt, ['Xns]" : "'Xt, ['Xns, #'s2012*16]";
6066 Format(instr, mnemonic_.c_str(), form);
6069 void Disassembler::DisassembleCpy(const Instruction *instr) {
6072 int d = instr->GetRd();
6073 int n = instr->GetRn();
6074 int s = instr->GetRs();
6082 if (instr->ExtractBits(31, 30)) {
6086 Format(instr, mnemonic_.c_str(), form);
6089 void Disassembler::DisassembleSet(const Instruction *instr) {
6092 int d = instr->GetRd();
6093 int n = instr->GetRn();
6094 int s = instr->GetRs();
6102 if (instr->ExtractBits(31, 30)) {
6106 Format(instr, mnemonic_.c_str(), form);
6109 void Disassembler::ProcessOutput(const Instruction * /*instr*/) {
6114 void Disassembler::AppendRegisterNameToOutput(const Instruction *instr,
6116 USE(instr);
6156 void Disassembler::AppendPCRelativeOffsetToOutput(const Instruction *instr,
6158 USE(instr);
6169 void Disassembler::AppendAddressToOutput(const Instruction *instr,
6171 USE(instr);
6176 void Disassembler::AppendCodeAddressToOutput(const Instruction *instr,
6178 AppendAddressToOutput(instr, addr);
6182 void Disassembler::AppendDataAddressToOutput(const Instruction *instr,
6184 AppendAddressToOutput(instr, addr);
6188 void Disassembler::AppendCodeRelativeAddressToOutput(const Instruction *instr,
6190 USE(instr);
6201 const Instruction *instr, const void *addr) {
6202 AppendCodeRelativeAddressToOutput(instr, addr);
6207 const Instruction *instr, const void *addr) {
6208 AppendCodeRelativeAddressToOutput(instr, addr);
6222 void Disassembler::Format(const Instruction *instr,
6227 VisitUnallocated(instr);
6230 Substitute(instr, mnemonic);
6234 Substitute(instr, format0);
6237 Substitute(instr, format1);
6242 ProcessOutput(instr);
6246 void Disassembler::FormatWithDecodedMnemonic(const Instruction *instr,
6249 Format(instr, mnemonic_.c_str(), format0, format1);
6252 void Disassembler::Substitute(const Instruction *instr, const char *string) {
6256 string += SubstituteField(instr, string);
6266 int Disassembler::SubstituteField(const Instruction *instr,
6281 return SubstituteRegisterField(instr, format);
6283 return SubstitutePredicateRegisterField(instr, format);
6285 return SubstituteImmediateField(instr, format);
6287 return SubstituteLiteralField(instr, format);
6289 return SubstituteShiftField(instr, format);
6291 return SubstituteConditionField(instr, format);
6293 return SubstituteExtendField(instr, format);
6295 return SubstitutePCRelAddressField(instr, format);
6297 return SubstituteBranchTargetField(instr, format);
6299 return SubstituteLSRegOffsetField(instr, format);
6301 return SubstituteBarrierField(instr, format);
6303 return SubstituteCrField(instr, format);
6305 return SubstituteSysOpField(instr, format);
6307 return SubstitutePrefetchField(instr, format);
6310 return SubstituteIntField(instr, format);
6312 return SubstituteSVESize(instr, format);
6314 return SubstituteTernary(instr, format);
6323 const Instruction *instr, char reg_prefix, const char *field) {
6329 reg_num = instr->GetRd();
6332 reg_num = instr->GetRn();
6335 reg_num = instr->GetRm();
6340 reg_num = instr->GetRmLow16();
6346 (instr->GetNEONSize() < 2) ? instr->GetRmLow16() : instr->GetRm();
6349 reg_num = instr->GetRa();
6352 reg_num = instr->GetRs();
6355 reg_num = instr->GetRt();
6371 reg_num = instr->GetRt2();
6392 int Disassembler::SubstituteRegisterField(const Instruction *instr,
6405 bool is_x = instr->GetSixtyFourBits() == 1;
6412 is_x = (instr->ExtractBit(bitpos) == 1);
6420 GetRegNumForField(instr, reg_prefix, reg_field);
6440 imm *= (1 << instr->GetNEONLSSize());
6443 imm *= (instr->GetNEONQ() == 0) ? kDRegSizeInBytes
6461 switch (instr->GetFPType()) {
6505 reg_size = 1 << (instr->GetSVESize() + 3);
6518 AppendRegisterNameToOutput(instr, CPURegister(reg_num, reg_size, reg_type));
6523 int Disassembler::SubstitutePredicateRegisterField(const Instruction *instr,
6531 AppendToOutput("p%u", instr->GetPt());
6534 AppendToOutput("p%u", instr->GetPn());
6537 AppendToOutput("p%u", instr->GetPm());
6541 AppendToOutput("p%u", instr->GetPgLow8());
6549 int Disassembler::SubstituteImmediateField(const Instruction *instr,
6556 AppendToOutput("#0x%" PRIx32, instr->GetImmMoveWide());
6557 if (instr->GetShiftMoveWide() > 0) {
6558 AppendToOutput(", lsl #%" PRId32, 16 * instr->GetShiftMoveWide());
6562 uint64_t imm = static_cast<uint64_t>(instr->GetImmMoveWide())
6563 << (16 * instr->GetShiftMoveWide());
6565 if (!instr->GetSixtyFourBits()) imm &= UINT64_C(0xffffffff);
6574 instr->GetImmLLiteral() *
6582 if (is_index || (instr->GetImmLS() != 0)) {
6583 AppendToOutput(", #%" PRId32, instr->GetImmLS());
6592 if (is_index || (instr->GetImmLSPair() != 0)) {
6595 AppendToOutput(", #%" PRId32, instr->GetImmLSPair() * scale);
6600 if (instr->GetImmLSUnsigned() != 0) {
6601 int shift = instr->GetSizeLS();
6602 AppendToOutput(", #%" PRId32, instr->GetImmLSUnsigned() << shift);
6607 if (instr->GetImmLSPAC() != 0) {
6608 AppendToOutput(", #%" PRId32, instr->GetImmLSPAC());
6619 int64_t offset = instr->GetImmCondBranch() << 2;
6620 AppendPCRelativeOffsetToOutput(instr, offset);
6624 int64_t imm = instr->GetImmAddSub() << (12 * instr->GetImmAddSubShift());
6638 AppendToOutput("#%" PRId32, 64 - instr->GetFPScale());
6642 imm8 = instr->GetImmNEONabcdefgh();
6647 imm8 = instr->ExtractBits(12, 5);
6652 imm8 = instr->GetImmFP();
6665 AppendToOutput("#%" PRId32, instr->GetImmHint());
6674 AppendToOutput("#0x%" PRIx64, instr->GetSVEImmLogical());
6679 instr->GetSVEImmShiftAndLaneSizeLog2(
6688 instr->GetSVEImmShiftAndLaneSizeLog2(
6696 instr->GetSVEImmShiftAndLaneSizeLog2(
6705 instr->GetSVEImmShiftAndLaneSizeLog2(
6715 AppendToOutput("#0x%" PRIx64, instr->GetImmLogical());
6720 int nzcv = (instr->GetNzcv() << Flags_offset);
6729 AppendToOutput("#%" PRId32, instr->GetImmCondCmp());
6733 return SubstituteBitfieldImmediateField(instr, format);
6736 AppendToOutput("#%" PRId32, instr->GetImmS());
6741 (instr->GetImmTestBranchBit5() << 5) |
6742 instr->GetImmTestBranchBit40());
6747 int imm = instr->ExtractSignedBits(19, 16);
6749 int reg_count = instr->ExtractBits(22, 21) + 1;
6757 int shift = 16 << HighestSetBitPosition(instr->GetImmNEONImmh());
6758 shift -= instr->GetImmNEONImmhImmb();
6763 int shift = instr->GetImmNEONImmhImmb();
6764 shift -= 8 << HighestSetBitPosition(instr->GetImmNEONImmh());
6775 AppendToOutput("#0x%" PRIx32, instr->GetImmException());
6779 AppendToOutput("#0x%" PRIx32, instr->GetImmUdf());
6785 AppendToOutput("#%" PRId32, instr->GetImmNEONExt());
6790 uint32_t vm_index = instr->GetNEONH() << 2;
6791 vm_index |= instr->GetNEONL() << 1;
6792 vm_index |= instr->GetNEONM();
6798 VIXL_ASSERT((instr->GetNEONSize() == 1) ||
6799 (instr->GetNEONSize() == 2));
6800 vm_index >>= instr->GetNEONSize();
6806 if (instr->GetNEONSize() == 2) {
6809 } else if (instr->GetNEONSize() == 3) {
6820 unsigned imm5 = instr->GetImmNEON5();
6821 unsigned imm4 = instr->GetImmNEON4();
6841 instr->GetSVEPermuteIndexAndLaneSizeLog2();
6848 AppendToOutput("%d", instr->GetNEONLSIndex(format[8] - '0'));
6853 uint64_t imm8 = instr->GetImmNEONabcdefgh();
6857 uint64_t imm8 = instr->GetImmNEONabcdefgh();
6869 int cmode = instr->GetNEONCmode();
6876 int cmode = instr->GetNEONCmode();
6892 AppendToOutput("#0x%" PRIx32, instr->GetCRm());
6896 switch (instr->GetImmSystemRegister()) {
6911 instr->GetSysOp0(),
6912 instr->GetSysOp1(),
6913 instr->GetCRn(),
6914 instr->GetCRm(),
6915 instr->GetSysOp2());
6923 AppendToOutput("#%d", instr->GetImmRMIFRotation());
6934 unsigned pattern = instr->GetImmSVEPredicateConstraint();
6982 int Disassembler::SubstituteBitfieldImmediateField(const Instruction *instr,
6985 unsigned r = instr->GetImmR();
6986 unsigned s = instr->GetImmS();
7006 (instr->GetSixtyFourBits() == 1) ? kXRegSize : kWRegSize;
7018 int Disassembler::SubstituteLiteralField(const Instruction *instr,
7023 const void *address = instr->GetLiteralAddress<const void *>();
7024 switch (instr->Mask(LoadLiteralMask)) {
7031 AppendCodeRelativeDataAddressToOutput(instr, address);
7035 switch (instr->GetPrefetchHint()) {
7038 AppendCodeRelativeDataAddressToOutput(instr, address);
7041 AppendCodeRelativeCodeAddressToOutput(instr, address);
7044 AppendCodeRelativeAddressToOutput(instr, address);
7057 int Disassembler::SubstituteShiftField(const Instruction *instr,
7060 VIXL_ASSERT(instr->GetShiftDP() <= 0x3);
7064 VIXL_ASSERT(instr->GetShiftDP() != ROR);
7068 if (instr->GetImmDPShift() != 0) {
7071 shift_type[instr->GetShiftDP()],
7072 instr->GetImmDPShift());
7078 int msz = instr->ExtractBits(24, 23);
7091 int Disassembler::SubstituteConditionField(const Instruction *instr,
7113 cond = instr->GetConditionBranch();
7116 cond = InvertCondition(static_cast<Condition>(instr->GetCondition()));
7120 cond = instr->GetCondition();
7127 int Disassembler::SubstitutePCRelAddressField(const Instruction *instr,
7132 int64_t offset = instr->GetImmPCRel();
7136 const Instruction *base = instr + code_address_offset();
7146 AppendPCRelativeOffsetToOutput(instr, offset);
7148 AppendCodeRelativeAddressToOutput(instr, target);
7153 int Disassembler::SubstituteBranchTargetField(const Instruction *instr,
7161 offset = instr->GetImmUncondBranch();
7165 offset = instr->GetImmCondBranch();
7169 offset = instr->GetImmCmpBranch();
7173 offset = instr->GetImmTestBranch();
7179 const void *target_address = reinterpret_cast<const void *>(instr + offset);
7180 VIXL_STATIC_ASSERT(sizeof(*instr) == 1);
7182 AppendPCRelativeOffsetToOutput(instr, offset);
7184 AppendCodeRelativeCodeAddressToOutput(instr, target_address);
7190 int Disassembler::SubstituteExtendField(const Instruction *instr,
7193 VIXL_ASSERT(instr->GetExtendMode() <= 7);
7201 if (((instr->GetRd() == kZeroRegCode) || (instr->GetRn() == kZeroRegCode)) &&
7202 (((instr->GetExtendMode() == UXTW) && (instr->GetSixtyFourBits() == 0)) ||
7203 (instr->GetExtendMode() == UXTX))) {
7204 if (instr->GetImmExtendShift() > 0) {
7205 AppendToOutput(", lsl #%" PRId32, instr->GetImmExtendShift());
7208 AppendToOutput(", %s", extend_mode[instr->GetExtendMode()]);
7209 if (instr->GetImmExtendShift() > 0) {
7210 AppendToOutput(" #%" PRId32, instr->GetImmExtendShift());
7217 int Disassembler::SubstituteLSRegOffsetField(const Instruction *instr,
7230 unsigned shift = instr->GetImmShiftLS();
7231 Extend ext = static_cast<Extend>(instr->GetExtendMode());
7234 unsigned rm = instr->GetRm();
7245 AppendToOutput(" #%d", instr->GetSizeLS());
7252 int Disassembler::SubstitutePrefetchField(const Instruction *instr,
7270 is_sve ? instr->GetSVEPrefetchHint() : instr->GetPrefetchHint();
7271 unsigned target = instr->GetPrefetchTarget() + 1;
7272 unsigned stream = instr->GetPrefetchStream();
7277 std::bitset<4> prefetch_mode(instr->GetSVEImmPrefetchOperation());
7280 std::bitset<5> prefetch_mode(instr->GetImmPrefetchOperation());
7293 int Disassembler::SubstituteBarrierField(const Instruction *instr,
7302 int domain = instr->GetImmBarrierDomain();
7303 int type = instr->GetImmBarrierType();
7309 int Disassembler::SubstituteSysOpField(const Instruction *instr,
7315 op = instr->GetSysOp1();
7318 op = instr->GetSysOp2();
7327 int Disassembler::SubstituteCrField(const Instruction *instr,
7333 cr = instr->GetCRn();
7336 cr = instr->GetCRm();
7345 int Disassembler::SubstituteIntField(const Instruction *instr,
7369 bits = (bits << chunk_width) | (instr->ExtractBits(msb, lsb));
7403 int Disassembler::SubstituteSVESize(const Instruction *instr,
7409 unsigned size_in_bytes_log2 = instr->GetSVESize();
7414 size_in_bytes_log2 = instr->ExtractBits(18, 17);
7420 size_in_bytes_log2 = instr->ExtractBits(22, 21);
7424 unsigned msize = instr->ExtractBits(24, 23);
7430 size_in_bytes_log2 = instr->GetSVEBitwiseImmLaneSizeInBytesLog2();
7436 size_in_bytes_log2 = instr->ExtractBits(24, 23);
7440 instr->GetSVEPermuteIndexAndLaneSizeLog2();
7451 instr->GetSVEImmShiftAndLaneSizeLog2(is_predicated);
7479 int Disassembler::SubstituteTernary(const Instruction *instr,
7493 AppendToOutput("%c", c[1 - instr->ExtractBit(static_cast<int>(value))]);
7514 void PrintDisassembler::Disassemble(const Instruction *instr) {
7524 decoder.Decode(instr);
7548 void PrintDisassembler::ProcessOutput(const Instruction *instr) {
7549 int64_t address = CodeRelativeAddress(instr);
7571 instr->GetInstructionBits(),