Lines Matching refs:zd
50 void Assembler::adr(const ZRegister& zd, const SVEMemOperand& addr) {
54 AreSameLaneSize(zd, addr.GetVectorBase(), addr.GetVectorOffset()));
56 int lane_size = zd.GetLaneSizeInBits();
82 Emit(op | msz | Rd(zd) | Rn(addr.GetVectorBase()) |
100 void Assembler::and_(const ZRegister& zd, const ZRegister& zn, uint64_t imm) {
103 VIXL_ASSERT(zd.Is(zn));
104 SVELogicalImmediate(zd, imm, AND_z_zi);
107 void Assembler::dupm(const ZRegister& zd, uint64_t imm) {
112 SVELogicalImmediate(zd, imm, DUPM_z_i);
115 void Assembler::eor(const ZRegister& zd, const ZRegister& zn, uint64_t imm) {
118 VIXL_ASSERT(zd.Is(zn));
119 SVELogicalImmediate(zd, imm, EOR_z_zi);
122 void Assembler::orr(const ZRegister& zd, const ZRegister& zn, uint64_t imm) {
125 VIXL_ASSERT(zd.Is(zn));
126 SVELogicalImmediate(zd, imm, ORR_z_zi);
130 void Assembler::and_(const ZRegister& zd,
134 VIXL_ASSERT(zd.IsLaneSizeD());
135 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
136 Emit(AND_z_zz | Rd(zd) | Rn(zn) | Rm(zm));
139 void Assembler::bic(const ZRegister& zd,
143 VIXL_ASSERT(zd.IsLaneSizeD());
144 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
145 Emit(BIC_z_zz | Rd(zd) | Rn(zn) | Rm(zm));
148 void Assembler::eor(const ZRegister& zd,
152 VIXL_ASSERT(zd.IsLaneSizeD());
153 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
154 Emit(EOR_z_zz | Rd(zd) | Rn(zn) | Rm(zm));
157 void Assembler::orr(const ZRegister& zd,
161 VIXL_ASSERT(zd.IsLaneSizeD());
162 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
163 Emit(ORR_z_zz | Rd(zd) | Rn(zn) | Rm(zm));
178 void Assembler::asr(const ZRegister& zd,
189 VIXL_ASSERT(zd.Is(zn));
191 EncodeSVEShiftRightImmediate(shift, zd.GetLaneSizeInBits());
192 SVEBitwiseShiftImmediatePred(zd, pg, encoded_imm, ASR_z_p_zi);
195 void Assembler::asr(const ZRegister& zd,
206 VIXL_ASSERT(zd.Is(zn));
207 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm) ||
209 (zd.GetLaneSizeInBytes() != kDRegSizeInBytes)));
211 if (AreSameLaneSize(zd, zn, zm)) {
214 Emit(op | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
217 void Assembler::asrd(const ZRegister& zd,
228 VIXL_ASSERT(zd.Is(zn));
231 EncodeSVEShiftRightImmediate(shift, zd.GetLaneSizeInBits());
232 SVEBitwiseShiftImmediatePred(zd, pg, encoded_imm, ASRD_z_p_zi);
235 void Assembler::asrr(const ZRegister& zd,
246 VIXL_ASSERT(zd.Is(zn));
247 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
249 Emit(ASRR_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
252 void Assembler::lsl(const ZRegister& zd,
263 VIXL_ASSERT(zd.Is(zn));
266 EncodeSVEShiftLeftImmediate(shift, zd.GetLaneSizeInBits());
267 SVEBitwiseShiftImmediatePred(zd, pg, encoded_imm, LSL_z_p_zi);
270 void Assembler::lsl(const ZRegister& zd,
281 VIXL_ASSERT(zd.Is(zn));
282 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm) ||
284 (zd.GetLaneSizeInBytes() != kDRegSizeInBytes)));
286 if (AreSameLaneSize(zd, zn, zm)) {
289 Emit(op | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
292 void Assembler::lslr(const ZRegister& zd,
303 VIXL_ASSERT(zd.Is(zn));
304 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
306 Emit(LSLR_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
309 void Assembler::lsr(const ZRegister& zd,
320 VIXL_ASSERT(zd.Is(zn));
323 EncodeSVEShiftRightImmediate(shift, zd.GetLaneSizeInBits());
324 SVEBitwiseShiftImmediatePred(zd, pg, encoded_imm, LSR_z_p_zi);
327 void Assembler::lsr(const ZRegister& zd,
338 VIXL_ASSERT(zd.Is(zn));
339 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm) ||
341 (zd.GetLaneSizeInBytes() != kDRegSizeInBytes)));
343 if (AreSameLaneSize(zd, zn, zm)) {
346 Emit(op | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
349 void Assembler::lsrr(const ZRegister& zd,
360 VIXL_ASSERT(zd.Is(zn));
361 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
363 Emit(LSRR_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
379 void Assembler::SVEBitwiseShiftImmediate(const ZRegister& zd,
386 Emit(op | tszh | tszl_and_imm | Rd(zd) | Rn(zn));
389 void Assembler::asr(const ZRegister& zd, const ZRegister& zn, int shift) {
391 VIXL_ASSERT(AreSameLaneSize(zd, zn));
393 EncodeSVEShiftRightImmediate(shift, zd.GetLaneSizeInBits());
394 SVEBitwiseShiftImmediate(zd, zn, encoded_imm, ASR_z_zi);
397 void Assembler::asr(const ZRegister& zd,
401 VIXL_ASSERT(AreSameLaneSize(zd, zn));
402 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kDRegSizeInBytes);
404 Emit(ASR_z_zw | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
407 void Assembler::lsl(const ZRegister& zd, const ZRegister& zn, int shift) {
410 EncodeSVEShiftLeftImmediate(shift, zd.GetLaneSizeInBits());
411 SVEBitwiseShiftImmediate(zd, zn, encoded_imm, LSL_z_zi);
414 void Assembler::lsl(const ZRegister& zd,
418 VIXL_ASSERT(AreSameLaneSize(zd, zn));
419 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kDRegSizeInBytes);
421 Emit(LSL_z_zw | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
424 void Assembler::lsr(const ZRegister& zd, const ZRegister& zn, int shift) {
427 EncodeSVEShiftRightImmediate(shift, zd.GetLaneSizeInBits());
428 SVEBitwiseShiftImmediate(zd, zn, encoded_imm, LSR_z_zi);
431 void Assembler::lsr(const ZRegister& zd,
435 VIXL_ASSERT(AreSameLaneSize(zd, zn));
436 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kDRegSizeInBytes);
438 Emit(LSR_z_zw | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
570 void Assembler::fabd(const ZRegister& zd,
580 VIXL_ASSERT(zd.Is(zn));
581 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
582 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
584 Emit(FABD_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
587 void Assembler::fadd(const ZRegister& zd,
597 VIXL_ASSERT(zd.Is(zn));
598 VIXL_ASSERT(AreSameLaneSize(zd, zn));
599 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
603 Emit(FADD_z_p_zs | SVESize(zd) | Rd(zd) | PgLow8(pg) | i1);
606 void Assembler::fadd(const ZRegister& zd,
616 VIXL_ASSERT(zd.Is(zn));
617 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
618 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
620 Emit(FADD_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
623 void Assembler::fdiv(const ZRegister& zd,
633 VIXL_ASSERT(zd.Is(zn));
634 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
635 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
637 Emit(FDIV_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
640 void Assembler::fdivr(const ZRegister& zd,
650 VIXL_ASSERT(zd.Is(zn));
651 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
652 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
654 Emit(FDIVR_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
657 void Assembler::fmax(const ZRegister& zd,
667 VIXL_ASSERT(zd.Is(zn));
668 VIXL_ASSERT(AreSameLaneSize(zd, zn));
669 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
673 Emit(FMAX_z_p_zs | SVESize(zd) | Rd(zd) | PgLow8(pg) | i1);
676 void Assembler::fmax(const ZRegister& zd,
686 VIXL_ASSERT(zd.Is(zn));
687 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
688 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
690 Emit(FMAX_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
693 void Assembler::fmaxnm(const ZRegister& zd,
703 VIXL_ASSERT(zd.Is(zn));
704 VIXL_ASSERT(AreSameLaneSize(zd, zn));
705 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
709 Emit(FMAXNM_z_p_zs | SVESize(zd) | Rd(zd) | PgLow8(pg) | i1);
712 void Assembler::fmaxnm(const ZRegister& zd,
722 VIXL_ASSERT(zd.Is(zn));
723 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
724 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
726 Emit(FMAXNM_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
729 void Assembler::fmin(const ZRegister& zd,
739 VIXL_ASSERT(zd.Is(zn));
740 VIXL_ASSERT(AreSameLaneSize(zd, zn));
741 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
745 Emit(FMIN_z_p_zs | SVESize(zd) | Rd(zd) | PgLow8(pg) | i1);
748 void Assembler::fmin(const ZRegister& zd,
758 VIXL_ASSERT(zd.Is(zn));
759 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
760 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
762 Emit(FMIN_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
765 void Assembler::fminnm(const ZRegister& zd,
775 VIXL_ASSERT(zd.Is(zn));
776 VIXL_ASSERT(AreSameLaneSize(zd, zn));
777 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
781 Emit(FMINNM_z_p_zs | SVESize(zd) | Rd(zd) | PgLow8(pg) | i1);
784 void Assembler::fminnm(const ZRegister& zd,
794 VIXL_ASSERT(zd.Is(zn));
795 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
796 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
798 Emit(FMINNM_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
801 void Assembler::fmul(const ZRegister& zd,
811 VIXL_ASSERT(zd.Is(zn));
812 VIXL_ASSERT(AreSameLaneSize(zd, zn));
813 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
817 Emit(FMUL_z_p_zs | SVESize(zd) | Rd(zd) | PgLow8(pg) | i1);
820 void Assembler::fmul(const ZRegister& zd,
830 VIXL_ASSERT(zd.Is(zn));
831 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
832 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
834 Emit(FMUL_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
837 void Assembler::fmulx(const ZRegister& zd,
847 VIXL_ASSERT(zd.Is(zn));
848 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
849 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
851 Emit(FMULX_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
854 void Assembler::fscale(const ZRegister& zd,
864 VIXL_ASSERT(zd.Is(zn));
865 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
866 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
868 Emit(FSCALE_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
871 void Assembler::fsub(const ZRegister& zd,
881 VIXL_ASSERT(zd.Is(zn));
882 VIXL_ASSERT(AreSameLaneSize(zd, zn));
883 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
887 Emit(FSUB_z_p_zs | SVESize(zd) | Rd(zd) | PgLow8(pg) | i1);
890 void Assembler::fsub(const ZRegister& zd,
900 VIXL_ASSERT(zd.Is(zn));
901 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
902 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
904 Emit(FSUB_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
907 void Assembler::fsubr(const ZRegister& zd,
917 VIXL_ASSERT(zd.Is(zn));
918 VIXL_ASSERT(AreSameLaneSize(zd, zn));
919 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
923 Emit(FSUBR_z_p_zs | SVESize(zd) | Rd(zd) | PgLow8(pg) | i1);
926 void Assembler::fsubr(const ZRegister& zd,
936 VIXL_ASSERT(zd.Is(zn));
937 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
938 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
940 Emit(FSUBR_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
943 void Assembler::ftmad(const ZRegister& zd,
953 VIXL_ASSERT(zd.Is(zn));
954 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
955 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
957 Emit(FTMAD_z_zzi | SVESize(zd) | Rd(zd) | Rn(zm) |
963 void Assembler::fadd(const ZRegister& zd,
971 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
972 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
974 Emit(FADD_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
977 void Assembler::fmul(const ZRegister& zd,
985 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
986 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
988 Emit(FMUL_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
991 void Assembler::frecps(const ZRegister& zd,
999 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
1000 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
1002 Emit(FRECPS_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
1005 void Assembler::frsqrts(const ZRegister& zd,
1013 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
1014 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
1016 Emit(FRSQRTS_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
1019 void Assembler::fsub(const ZRegister& zd,
1027 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
1028 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
1030 Emit(FSUB_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
1033 void Assembler::ftsmul(const ZRegister& zd,
1041 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
1042 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
1044 Emit(FTSMUL_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
1267 void Assembler::fcadd(const ZRegister& zd,
1278 VIXL_ASSERT(zd.Is(zn));
1279 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
1280 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
1284 Emit(FCADD_z_p_zz | rotate_bit | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
1648 void Assembler::fmul(const ZRegister& zd,
1657 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
1661 Instr synthesized_op = SVEMulIndexHelper(zd.GetLaneSizeInBytesLog2(),
1668 Emit(synthesized_op | Rd(zd) | Rn(zn));
1673 void Assembler::fcvt(const ZRegister& zd,
1681 switch (zd.GetLaneSizeInBytes()) {
1691 switch (zd.GetLaneSizeInBytes()) {
1701 switch (zd.GetLaneSizeInBytes()) {
1713 Emit(op | Rd(zd) | PgLow8(pg) | Rn(zn));
1716 void Assembler::fcvtzs(const ZRegister& zd,
1723 switch (zd.GetLaneSizeInBytes()) {
1736 switch (zd.GetLaneSizeInBytes()) {
1746 switch (zd.GetLaneSizeInBytes()) {
1758 Emit(op | Rd(zd) | PgLow8(pg) | Rn(zn));
1761 void Assembler::fcvtzu(const ZRegister& zd,
1768 switch (zd.GetLaneSizeInBytes()) {
1781 switch (zd.GetLaneSizeInBytes()) {
1791 switch (zd.GetLaneSizeInBytes()) {
1803 Emit(op | Rd(zd) | PgLow8(pg) | Rn(zn));
1806 void Assembler::frecpx(const ZRegister& zd,
1814 VIXL_ASSERT(AreSameLaneSize(zd, zn));
1815 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
1817 Emit(FRECPX_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
1820 void Assembler::frinta(const ZRegister& zd,
1824 VIXL_ASSERT(AreSameLaneSize(zd, zn));
1825 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
1827 Emit(FRINTA_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
1830 void Assembler::frinti(const ZRegister& zd,
1834 VIXL_ASSERT(AreSameLaneSize(zd, zn));
1835 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
1837 Emit(FRINTI_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
1840 void Assembler::frintm(const ZRegister& zd,
1844 VIXL_ASSERT(AreSameLaneSize(zd, zn));
1845 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
1847 Emit(FRINTM_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
1850 void Assembler::frintn(const ZRegister& zd,
1854 VIXL_ASSERT(AreSameLaneSize(zd, zn));
1855 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
1857 Emit(FRINTN_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
1860 void Assembler::frintp(const ZRegister& zd,
1864 VIXL_ASSERT(AreSameLaneSize(zd, zn));
1865 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
1867 Emit(FRINTP_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
1870 void Assembler::frintx(const ZRegister& zd,
1874 VIXL_ASSERT(AreSameLaneSize(zd, zn));
1875 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
1877 Emit(FRINTX_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
1880 void Assembler::frintz(const ZRegister& zd,
1884 VIXL_ASSERT(AreSameLaneSize(zd, zn));
1885 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
1887 Emit(FRINTZ_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
1890 void Assembler::fsqrt(const ZRegister& zd,
1898 VIXL_ASSERT(AreSameLaneSize(zd, zn));
1899 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
1901 Emit(FSQRT_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
1904 void Assembler::scvtf(const ZRegister& zd,
1911 switch (zd.GetLaneSizeInBytes()) {
1918 switch (zd.GetLaneSizeInBytes()) {
1931 switch (zd.GetLaneSizeInBytes()) {
1946 Emit(op | Rd(zd) | PgLow8(pg) | Rn(zn));
1949 void Assembler::ucvtf(const ZRegister& zd,
1956 switch (zd.GetLaneSizeInBytes()) {
1963 switch (zd.GetLaneSizeInBytes()) {
1976 switch (zd.GetLaneSizeInBytes()) {
1991 Emit(op | Rd(zd) | PgLow8(pg) | Rn(zn));
1996 void Assembler::frecpe(const ZRegister& zd, const ZRegister& zn) {
2002 VIXL_ASSERT(AreSameLaneSize(zd, zn));
2003 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
2005 Emit(FRECPE_z_z | SVESize(zd) | Rd(zd) | Rn(zn));
2008 void Assembler::frsqrte(const ZRegister& zd, const ZRegister& zn) {
2014 VIXL_ASSERT(AreSameLaneSize(zd, zn));
2015 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
2017 Emit(FRSQRTE_z_z | SVESize(zd) | Rd(zd) | Rn(zn));
2201 void Assembler::index(const ZRegister& zd, int start, int step) {
2208 Emit(INDEX_z_ii | SVESize(zd) | ImmField<20, 16>(step) |
2209 ImmField<9, 5>(start) | Rd(zd));
2212 void Assembler::index(const ZRegister& zd,
2221 zd.GetLaneSizeInBits());
2223 zd.GetLaneSizeInBits());
2225 Emit(INDEX_z_rr | SVESize(zd) | Rd(zd) | Rn(rn) | Rm(rm));
2228 void Assembler::index(const ZRegister& zd, const Register& rn, int imm5) {
2235 zd.GetLaneSizeInBits());
2237 Emit(INDEX_z_ri | SVESize(zd) | Rd(zd) | Rn(rn) | ImmField<20, 16>(imm5));
2240 void Assembler::index(const ZRegister& zd, int imm5, const Register& rm) {
2247 zd.GetLaneSizeInBits());
2249 Emit(INDEX_z_ir | SVESize(zd) | Rd(zd) | ImmField<9, 5>(imm5) | Rm(rm));
2254 void Assembler::add(const ZRegister& zd,
2262 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
2264 Emit(ADD_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
2267 void Assembler::sqadd(const ZRegister& zd,
2275 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
2277 Emit(SQADD_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
2280 void Assembler::sqsub(const ZRegister& zd,
2288 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
2290 Emit(SQSUB_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
2293 void Assembler::sub(const ZRegister& zd,
2301 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
2303 Emit(SUB_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
2306 void Assembler::uqadd(const ZRegister& zd,
2314 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
2316 Emit(UQADD_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
2319 void Assembler::uqsub(const ZRegister& zd,
2327 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
2329 Emit(UQSUB_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
2334 void Assembler::add(const ZRegister& zd,
2344 VIXL_ASSERT(zd.Is(zn));
2345 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2347 Emit(ADD_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
2350 void Assembler::and_(const ZRegister& zd,
2360 VIXL_ASSERT(zd.Is(zn));
2361 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2363 Emit(AND_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
2366 void Assembler::bic(const ZRegister& zd,
2376 VIXL_ASSERT(zd.Is(zn));
2377 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2379 Emit(BIC_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
2382 void Assembler::eor(const ZRegister& zd,
2392 VIXL_ASSERT(zd.Is(zn));
2393 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2395 Emit(EOR_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
2398 void Assembler::mul(const ZRegister& zd,
2408 VIXL_ASSERT(zd.Is(zn));
2409 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2411 Emit(MUL_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
2414 void Assembler::orr(const ZRegister& zd,
2424 VIXL_ASSERT(zd.Is(zn));
2425 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2427 Emit(ORR_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
2430 void Assembler::sabd(const ZRegister& zd,
2440 VIXL_ASSERT(zd.Is(zn));
2441 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2443 Emit(SABD_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
2446 void Assembler::sdiv(const ZRegister& zd,
2456 VIXL_ASSERT(zd.Is(zn));
2457 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2458 VIXL_ASSERT(zd.IsLaneSizeS() || zd.IsLaneSizeD());
2460 Emit(SDIV_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
2463 void Assembler::sdivr(const ZRegister& zd,
2473 VIXL_ASSERT(zd.Is(zn));
2474 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2475 VIXL_ASSERT(zd.IsLaneSizeS() || zd.IsLaneSizeD());
2477 Emit(SDIVR_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
2480 void Assembler::smax(const ZRegister& zd,
2490 VIXL_ASSERT(zd.Is(zn));
2491 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2493 Emit(SMAX_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
2496 void Assembler::smin(const ZRegister& zd,
2506 VIXL_ASSERT(zd.Is(zn));
2507 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2509 Emit(SMIN_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
2512 void Assembler::smulh(const ZRegister& zd,
2522 VIXL_ASSERT(zd.Is(zn));
2523 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2525 Emit(SMULH_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
2528 void Assembler::sub(const ZRegister& zd,
2538 VIXL_ASSERT(zd.Is(zn));
2539 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2541 Emit(SUB_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
2544 void Assembler::subr(const ZRegister& zd,
2554 VIXL_ASSERT(zd.Is(zn));
2555 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2557 Emit(SUBR_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
2560 void Assembler::uabd(const ZRegister& zd,
2570 VIXL_ASSERT(zd.Is(zn));
2571 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2573 Emit(UABD_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
2576 void Assembler::udiv(const ZRegister& zd,
2586 VIXL_ASSERT(zd.Is(zn));
2587 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2588 VIXL_ASSERT(zd.IsLaneSizeS() || zd.IsLaneSizeD());
2590 Emit(UDIV_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
2593 void Assembler::udivr(const ZRegister& zd,
2603 VIXL_ASSERT(zd.Is(zn));
2604 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2605 VIXL_ASSERT(zd.IsLaneSizeS() || zd.IsLaneSizeD());
2607 Emit(UDIVR_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
2610 void Assembler::umax(const ZRegister& zd,
2620 VIXL_ASSERT(zd.Is(zn));
2621 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2623 Emit(UMAX_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
2626 void Assembler::umin(const ZRegister& zd,
2636 VIXL_ASSERT(zd.Is(zn));
2637 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2639 Emit(UMIN_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
2642 void Assembler::umulh(const ZRegister& zd,
2652 VIXL_ASSERT(zd.Is(zn));
2653 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2655 Emit(UMULH_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
3134 void Assembler::fexpa(const ZRegister& zd, const ZRegister& zn) {
3140 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3141 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
3143 Emit(FEXPA_z_z | SVESize(zd) | Rd(zd) | Rn(zn));
3146 void Assembler::ftssel(const ZRegister& zd,
3154 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
3155 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
3157 Emit(FTSSEL_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
3160 void Assembler::movprfx(const ZRegister& zd, const ZRegister& zn) {
3166 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3168 Emit(MOVPRFX_z_z | Rd(zd) | Rn(zn));
3273 void Assembler::movprfx(const ZRegister& zd,
3281 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3286 Emit(MOVPRFX_z_p_z | SVESize(zd) | m | Rd(zd) | PgLow8(pg) | Rn(zn));
3353 void Assembler::abs(const ZRegister& zd,
3361 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3363 Emit(ABS_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
3366 void Assembler::cls(const ZRegister& zd,
3374 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3376 Emit(CLS_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
3379 void Assembler::clz(const ZRegister& zd,
3387 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3389 Emit(CLZ_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
3392 void Assembler::cnot(const ZRegister& zd,
3400 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3402 Emit(CNOT_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
3405 void Assembler::cnt(const ZRegister& zd,
3413 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3415 Emit(CNT_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
3418 void Assembler::fabs(const ZRegister& zd,
3426 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3427 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
3429 Emit(FABS_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
3432 void Assembler::fneg(const ZRegister& zd,
3440 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3441 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
3443 Emit(FNEG_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
3446 void Assembler::neg(const ZRegister& zd,
3454 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3456 Emit(NEG_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
3459 void Assembler::not_(const ZRegister& zd,
3467 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3469 Emit(NOT_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
3472 void Assembler::sxtb(const ZRegister& zd,
3480 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3481 VIXL_ASSERT(zd.GetLaneSizeInBytes() > kBRegSizeInBytes);
3483 Emit(SXTB_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
3486 void Assembler::sxth(const ZRegister& zd,
3494 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3495 VIXL_ASSERT(zd.GetLaneSizeInBytes() > kHRegSizeInBytes);
3497 Emit(SXTH_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
3500 void Assembler::sxtw(const ZRegister& zd,
3508 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3509 VIXL_ASSERT(zd.GetLaneSizeInBytes() > kSRegSizeInBytes);
3511 Emit(SXTW_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
3514 void Assembler::uxtb(const ZRegister& zd,
3522 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3523 VIXL_ASSERT(zd.GetLaneSizeInBytes() > kBRegSizeInBytes);
3525 Emit(UXTB_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
3528 void Assembler::uxth(const ZRegister& zd,
3536 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3537 VIXL_ASSERT(zd.GetLaneSizeInBytes() > kHRegSizeInBytes);
3539 Emit(UXTH_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
3542 void Assembler::uxtw(const ZRegister& zd,
3550 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3551 VIXL_ASSERT(zd.GetLaneSizeInBytes() > kSRegSizeInBytes);
3553 Emit(UXTW_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
3558 void Assembler::cpy(const ZRegister& zd,
3573 Emit(CPY_z_p_i | m | sh | SVESize(zd) | Rd(zd) | Pg<19, 16>(pg) |
3577 void Assembler::fcpy(const ZRegister& zd, const PRegisterM& pg, double imm) {
3583 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
3586 Emit(FCPY_z_p_i | SVESize(zd) | Rd(zd) | Pg<19, 16>(pg) | imm_field);
3593 const ZRegister& zd,
3611 Emit(op | SVESize(zd) | Rd(zd) | shift_bit | ImmUnsignedField<12, 5>(imm8));
3614 void Assembler::add(const ZRegister& zd,
3624 VIXL_ASSERT(zd.Is(zn));
3625 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3627 SVEIntAddSubtractImmUnpredicatedHelper(ADD_z_zi, zd, imm8, shift);
3630 void Assembler::dup(const ZRegister& zd, int imm8, int shift) {
3638 VIXL_ASSERT((shift < 8) || !zd.IsLaneSizeB());
3641 Emit(DUP_z_i | SVESize(zd) | Rd(zd) | shift_bit | ImmField<12, 5>(imm8));
3644 void Assembler::fdup(const ZRegister& zd, double imm) {
3650 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
3653 Emit(FDUP_z_i | SVESize(zd) | encoded_imm | Rd(zd));
3656 void Assembler::mul(const ZRegister& zd, const ZRegister& zn, int imm8) {
3663 VIXL_ASSERT(zd.Is(zn));
3664 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3666 Emit(MUL_z_zi | SVESize(zd) | Rd(zd) | ImmField<12, 5>(imm8));
3669 void Assembler::smax(const ZRegister& zd, const ZRegister& zn, int imm8) {
3676 VIXL_ASSERT(zd.Is(zn));
3677 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3679 Emit(SMAX_z_zi | SVESize(zd) | Rd(zd) | ImmField<12, 5>(imm8));
3682 void Assembler::smin(const ZRegister& zd, const ZRegister& zn, int imm8) {
3689 VIXL_ASSERT(zd.Is(zn));
3690 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3692 Emit(SMIN_z_zi | SVESize(zd) | Rd(zd) | ImmField<12, 5>(imm8));
3695 void Assembler::sqadd(const ZRegister& zd,
3705 VIXL_ASSERT(zd.Is(zn));
3706 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3708 SVEIntAddSubtractImmUnpredicatedHelper(SQADD_z_zi, zd, imm8, shift);
3711 void Assembler::sqsub(const ZRegister& zd,
3721 VIXL_ASSERT(zd.Is(zn));
3722 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3724 SVEIntAddSubtractImmUnpredicatedHelper(SQSUB_z_zi, zd, imm8, shift);
3727 void Assembler::sub(const ZRegister& zd,
3737 VIXL_ASSERT(zd.Is(zn));
3738 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3740 SVEIntAddSubtractImmUnpredicatedHelper(SUB_z_zi, zd, imm8, shift);
3743 void Assembler::subr(const ZRegister& zd,
3753 VIXL_ASSERT(zd.Is(zn));
3754 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3756 SVEIntAddSubtractImmUnpredicatedHelper(SUBR_z_zi, zd, imm8, shift);
3759 void Assembler::umax(const ZRegister& zd, const ZRegister& zn, int imm8) {
3766 VIXL_ASSERT(zd.Is(zn));
3767 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3769 Emit(UMAX_z_zi | SVESize(zd) | Rd(zd) | ImmUnsignedField<12, 5>(imm8));
3772 void Assembler::umin(const ZRegister& zd, const ZRegister& zn, int imm8) {
3779 VIXL_ASSERT(zd.Is(zn));
3780 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3782 Emit(UMIN_z_zi | SVESize(zd) | Rd(zd) | ImmUnsignedField<12, 5>(imm8));
3785 void Assembler::uqadd(const ZRegister& zd,
3795 VIXL_ASSERT(zd.Is(zn));
3796 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3798 SVEIntAddSubtractImmUnpredicatedHelper(UQADD_z_zi, zd, imm8, shift);
3801 void Assembler::uqsub(const ZRegister& zd,
3811 VIXL_ASSERT(zd.Is(zn));
3812 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3814 SVEIntAddSubtractImmUnpredicatedHelper(UQSUB_z_zi, zd, imm8, shift);
5563 void Assembler::ext(const ZRegister& zd,
5582 if (zd.Is(zn)) {
5591 Emit(op | Rd(zd) | ImmUnsignedField<20, 16>(imm8h) |
5597 void Assembler::trn1(const ZRegister& zd,
5605 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
5607 Emit(TRN1_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
5610 void Assembler::trn2(const ZRegister& zd,
5618 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
5620 Emit(TRN2_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
5623 void Assembler::uzp1(const ZRegister& zd,
5631 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
5633 Emit(UZP1_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
5636 void Assembler::uzp2(const ZRegister& zd,
5644 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
5646 Emit(UZP2_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
5649 void Assembler::zip1(const ZRegister& zd,
5657 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
5659 Emit(ZIP1_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
5662 void Assembler::zip2(const ZRegister& zd,
5670 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
5672 Emit(ZIP2_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
5709 void Assembler::clasta(const ZRegister& zd,
5719 VIXL_ASSERT(zd.Is(zn));
5720 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
5722 Emit(CLASTA_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
5757 void Assembler::clastb(const ZRegister& zd,
5767 VIXL_ASSERT(zd.Is(zn));
5768 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
5770 Emit(CLASTB_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
5773 void Assembler::compact(const ZRegister& zd,
5781 VIXL_ASSERT(AreSameLaneSize(zd, zn));
5782 VIXL_ASSERT((zd.GetLaneSizeInBits() == kSRegSize) ||
5783 (zd.GetLaneSizeInBits() == kDRegSize));
5785 Instr sz = (zd.GetLaneSizeInBits() == kDRegSize) ? (1 << 22) : 0;
5786 Emit(COMPACT_z_p_z | sz | Rd(zd) | PgLow8(pg) | Rn(zn));
5789 void Assembler::cpy(const ZRegister& zd,
5798 zd.GetLaneSizeInBits());
5800 Emit(CPY_z_p_r | SVESize(zd) | Rd(zd) | PgLow8(pg) | RnSP(rn));
5803 void Assembler::cpy(const ZRegister& zd,
5813 zd.GetLaneSizeInBits());
5815 Emit(CPY_z_p_v | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(vn));
5868 void Assembler::rbit(const ZRegister& zd,
5876 VIXL_ASSERT(AreSameLaneSize(zd, zn));
5878 Emit(RBIT_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
5881 void Assembler::revb(const ZRegister& zd,
5889 VIXL_ASSERT(AreSameLaneSize(zd, zn));
5890 VIXL_ASSERT(zd.IsLaneSizeH() || zd.IsLaneSizeS() || zd.IsLaneSizeD());
5892 Emit(REVB_z_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
5895 void Assembler::revh(const ZRegister& zd,
5903 VIXL_ASSERT(AreSameLaneSize(zd, zn));
5904 VIXL_ASSERT(zd.IsLaneSizeS() || zd.IsLaneSizeD());
5906 Emit(REVH_z_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
5909 void Assembler::revw(const ZRegister& zd,
5917 VIXL_ASSERT(AreSameLaneSize(zd, zn));
5918 VIXL_ASSERT(zd.IsLaneSizeD());
5920 Emit(REVW_z_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
5923 void Assembler::splice(const ZRegister& zd,
5927 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
5929 if (zd.Aliases(zn)) {
5936 VIXL_ASSERT(zd.Is(zn));
5938 Emit(SPLICE_z_p_zz_des | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
5940 splice_con(zd, pg, zn, zm);
5944 void Assembler::splice_con(const ZRegister& zd,
5955 VIXL_ASSERT(AreSameLaneSize(zd, zn1, zn2));
5957 Emit(0x052d8000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn1));
5962 void Assembler::dup(const ZRegister& zd, const Register& xn) {
5969 Emit(DUP_z_r | SVESize(zd) | Rd(zd) | RnSP(xn));
5972 void Assembler::dup(const ZRegister& zd, const ZRegister& zn, unsigned index) {
5978 VIXL_ASSERT(AreSameFormat(zd, zn));
5979 VIXL_ASSERT((index * zd.GetLaneSizeInBits()) < 512);
5980 int n = zd.GetLaneSizeInBytesLog2();
5987 ImmUnsignedField<20, 16>(tsz_5) | Rd(zd) | Rn(zn));
6011 void Assembler::rev(const ZRegister& zd, const ZRegister& zn) {
6017 VIXL_ASSERT(AreSameFormat(zd, zn));
6019 Emit(REV_z_z | SVESize(zd) | Rd(zd) | Rn(zn));
6022 void Assembler::sunpkhi(const ZRegister& zd, const ZRegister& zn) {
6028 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
6029 VIXL_ASSERT(!zd.IsLaneSizeB());
6031 Emit(SUNPKHI_z_z | SVESize(zd) | Rd(zd) | Rn(zn));
6034 void Assembler::sunpklo(const ZRegister& zd, const ZRegister& zn) {
6040 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
6041 VIXL_ASSERT(!zd.IsLaneSizeB());
6043 Emit(SUNPKLO_z_z | SVESize(zd) | Rd(zd) | Rn(zn));
6046 void Assembler::tbl(const ZRegister& zd,
6054 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
6056 Emit(TBL_z_zz_1 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
6059 void Assembler::uunpkhi(const ZRegister& zd, const ZRegister& zn) {
6065 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
6066 VIXL_ASSERT(!zd.IsLaneSizeB());
6068 Emit(UUNPKHI_z_z | SVESize(zd) | Rd(zd) | Rn(zn));
6071 void Assembler::uunpklo(const ZRegister& zd, const ZRegister& zn) {
6077 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
6078 VIXL_ASSERT(!zd.IsLaneSizeB());
6080 Emit(UUNPKLO_z_z | SVESize(zd) | Rd(zd) | Rn(zn));
6451 void Assembler::sel(const ZRegister& zd,
6456 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
6458 Emit(SEL_z_p_zz | SVESize(zd) | Rd(zd) | Pg<13, 10>(pg) | Rn(zn) | Rm(zm));
6485 void Assembler::bic(const ZRegister& zd, const ZRegister& zn, uint64_t imm) {
6486 and_(zd, zn, ~imm);
6489 void Assembler::eon(const ZRegister& zd, const ZRegister& zn, uint64_t imm) {
6490 eor(zd, zn, ~imm);
6493 void Assembler::orn(const ZRegister& zd, const ZRegister& zn, uint64_t imm) {
6494 orr(zd, zn, ~imm);
6498 void Assembler::fmov(const ZRegister& zd, const PRegisterM& pg, double imm) {
6500 cpy(zd, pg, 0);
6502 fcpy(zd, pg, imm);
6506 void Assembler::fmov(const ZRegister& zd, double imm) {
6508 dup(zd, 0);
6510 fdup(zd, imm);
6535 void Assembler::mov(const ZRegister& zd,
6540 cpy(zd, pg, imm8, shift);
6543 void Assembler::mov(const ZRegister& zd, const Register& xn) { dup(zd, xn); }
6545 void Assembler::mov(const ZRegister& zd, const VRegister& vn) {
6547 VIXL_ASSERT(AreSameLaneSize(zd, vn));
6548 dup(zd, vn.Z().WithSameLaneSizeAs(vn), 0);
6551 void Assembler::mov(const ZRegister& zd, const ZRegister& zn) {
6552 VIXL_ASSERT(AreSameLaneSize(zd, zn));
6553 orr(zd.VnD(), zn.VnD(), zn.VnD());
6556 void Assembler::mov(const ZRegister& zd, const ZRegister& zn, unsigned index) {
6557 VIXL_ASSERT(AreSameLaneSize(zd, zn));
6558 dup(zd, zn, index);
6561 void Assembler::mov(const ZRegister& zd,
6564 cpy(zd, pg, rn);
6567 void Assembler::mov(const ZRegister& zd,
6571 VIXL_ASSERT(AreSameLaneSize(zd, vn));
6572 cpy(zd, pg, vn);
6575 void Assembler::mov(const ZRegister& zd,
6578 VIXL_ASSERT(AreSameLaneSize(zd, zn));
6579 sel(zd, pg, zn, zd);
6582 void Assembler::mov(const ZRegister& zd, uint64_t imm) {
6586 dupm(zd, imm);
6589 void Assembler::mov(const ZRegister& zd, int imm8, int shift) {
6590 dup(zd, imm8, shift);
6651 void Assembler::addhnb(const ZRegister& zd,
6660 VIXL_ASSERT(zn.GetLaneSizeInBytes() == (zd.GetLaneSizeInBytes() * 2));
6663 Emit(0x45206000 | SVESize(zn) | Rd(zd) | Rn(zn) | Rm(zm));
6666 void Assembler::addhnt(const ZRegister& zd,
6675 VIXL_ASSERT(zn.GetLaneSizeInBytes() == (zd.GetLaneSizeInBytes() * 2));
6678 Emit(0x45206400 | SVESize(zn) | Rd(zd) | Rn(zn) | Rm(zm));
6681 void Assembler::addp(const ZRegister& zd,
6691 VIXL_ASSERT(zd.Is(zn));
6692 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
6694 Emit(0x4411a000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
6697 void Assembler::bcax(const ZRegister& zd,
6707 VIXL_ASSERT(zd.Is(zn));
6708 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm, zk));
6709 VIXL_ASSERT(zd.IsLaneSizeD());
6711 Emit(0x04603800 | Rd(zd) | Rm(zm) | Rn(zk));
6714 void Assembler::bdep(const ZRegister& zd,
6723 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
6725 Emit(0x4500b400 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
6728 void Assembler::bext(const ZRegister& zd,
6737 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
6739 Emit(0x4500b000 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
6742 void Assembler::bgrp(const ZRegister& zd,
6751 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
6753 Emit(0x4500b800 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
6756 void Assembler::bsl(const ZRegister& zd,
6766 VIXL_ASSERT(zd.Is(zn));
6767 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm, zk));
6768 VIXL_ASSERT(zd.IsLaneSizeD());
6770 Emit(0x04203c00 | Rd(zd) | Rm(zm) | Rn(zk));
6773 void Assembler::bsl1n(const ZRegister& zd,
6783 VIXL_ASSERT(zd.Is(zn));
6784 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm, zk));
6785 VIXL_ASSERT(zd.IsLaneSizeD());
6787 Emit(0x04603c00 | Rd(zd) | Rm(zm) | Rn(zk));
6790 void Assembler::bsl2n(const ZRegister& zd,
6800 VIXL_ASSERT(zd.Is(zn));
6801 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm, zk));
6802 VIXL_ASSERT(zd.IsLaneSizeD());
6804 Emit(0x04a03c00 | Rd(zd) | Rm(zm) | Rn(zk));
6807 void Assembler::cadd(const ZRegister& zd,
6817 VIXL_ASSERT(zd.Is(zn));
6818 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
6822 Emit(0x4500d800 | rotate_bit | SVESize(zd) | Rd(zd) | Rn(zm));
6909 void Assembler::eor3(const ZRegister& zd,
6919 VIXL_ASSERT(zd.Is(zn));
6920 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm, zk));
6921 VIXL_ASSERT(zd.IsLaneSizeD());
6923 Emit(0x04203800 | Rd(zd) | Rm(zm) | Rn(zk));
6926 void Assembler::eorbt(const ZRegister& zd,
6934 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
6936 Emit(0x45009000 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
6939 void Assembler::eortb(const ZRegister& zd,
6947 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
6949 Emit(0x45009400 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
6952 void Assembler::faddp(const ZRegister& zd,
6962 VIXL_ASSERT(zd.Is(zn));
6963 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
6964 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
6966 Emit(0x64108000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
6969 void Assembler::fcvtlt(const ZRegister& zd,
6979 if (zd.IsLaneSizeD() && zn.IsLaneSizeS()) {
6982 VIXL_ASSERT(zd.IsLaneSizeS() && zn.IsLaneSizeH());
6986 Emit(op | Rd(zd) | PgLow8(pg) | Rn(zn));
6989 void Assembler::fcvtnt(const ZRegister& zd,
6999 if (zd.IsLaneSizeS() && zn.IsLaneSizeD()) {
7002 VIXL_ASSERT(zd.IsLaneSizeH() && zn.IsLaneSizeS());
7005 Emit(op | Rd(zd) | PgLow8(pg) | Rn(zn));
7008 void Assembler::fcvtx(const ZRegister& zd,
7016 VIXL_ASSERT(zd.IsLaneSizeS() && zn.IsLaneSizeD());
7018 Emit(0x650aa000 | Rd(zd) | PgLow8(pg) | Rn(zn));
7021 void Assembler::fcvtxnt(const ZRegister& zd,
7030 Emit(0x640aa000 | Rd(zd) | PgLow8(pg) | Rn(zn));
7033 void Assembler::flogb(const ZRegister& zd,
7041 VIXL_ASSERT(AreSameLaneSize(zd, zn));
7042 VIXL_ASSERT(!zd.IsLaneSizeB());
7045 Instr size = SVESize(zd) >> 5;
7046 Emit(0x6518a000 | size | Rd(zd) | PgLow8(pg) | Rn(zn));
7049 void Assembler::fmaxnmp(const ZRegister& zd,
7059 VIXL_ASSERT(zd.Is(zn));
7060 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
7061 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
7063 Emit(0x64148000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
7066 void Assembler::fmaxp(const ZRegister& zd,
7076 VIXL_ASSERT(zd.Is(zn));
7077 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
7078 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
7080 Emit(0x64168000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
7083 void Assembler::fminnmp(const ZRegister& zd,
7093 VIXL_ASSERT(zd.Is(zn));
7094 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
7095 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
7097 Emit(0x64158000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
7100 void Assembler::fminp(const ZRegister& zd,
7110 VIXL_ASSERT(zd.Is(zn));
7111 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
7112 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
7114 Emit(0x64178000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
7241 void Assembler::histcnt(const ZRegister& zd,
7250 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
7251 VIXL_ASSERT(zd.IsLaneSizeS() || zd.IsLaneSizeD());
7253 Emit(0x4520c000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn) | Rm(zm));
7256 void Assembler::histseg(const ZRegister& zd,
7264 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
7265 VIXL_ASSERT(zd.IsLaneSizeB());
7267 Emit(0x4520a000 | Rd(zd) | Rn(zn) | Rm(zm));
7327 void Assembler::mul(const ZRegister& zd,
7336 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
7338 Instr synthesised_op = SVEMulIndexHelper(zd.GetLaneSizeInBytesLog2(),
7345 Emit(synthesised_op | Rd(zd) | Rn(zn));
7348 void Assembler::mul(const ZRegister& zd,
7356 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
7358 Emit(0x04206000 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
7361 void Assembler::nbsl(const ZRegister& zd,
7371 VIXL_ASSERT(zd.Is(zn));
7372 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm, zk));
7373 VIXL_ASSERT(zd.IsLaneSizeD());
7375 Emit(0x04e03c00 | Rd(zd) | Rm(zm) | Rn(zk));
7393 void Assembler::pmul(const ZRegister& zd,
7402 Emit(0x04206400 | Rd(zd) | Rn(zn) | Rm(zm));
7405 void Assembler::pmullb(const ZRegister& zd,
7414 VIXL_ASSERT(!zd.IsLaneSizeB() && !zd.IsLaneSizeS());
7415 VIXL_ASSERT(zd.GetLaneSizeInBytes() == zn.GetLaneSizeInBytes() * 2);
7417 VIXL_ASSERT(!zd.IsLaneSizeQ());
7419 Emit(0x45006800 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
7422 void Assembler::pmullt(const ZRegister& zd,
7431 VIXL_ASSERT(!zd.IsLaneSizeB() && !zd.IsLaneSizeS());
7432 VIXL_ASSERT(zd.GetLaneSizeInBytes() == zn.GetLaneSizeInBytes() * 2);
7434 VIXL_ASSERT(!zd.IsLaneSizeQ());
7436 Emit(0x45006c00 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
7439 void Assembler::raddhnb(const ZRegister& zd,
7448 VIXL_ASSERT(zn.GetLaneSizeInBytes() == (zd.GetLaneSizeInBytes() * 2));
7451 Emit(0x45206800 | SVESize(zn) | Rd(zd) | Rn(zn) | Rm(zm));
7454 void Assembler::raddhnt(const ZRegister& zd,
7463 VIXL_ASSERT(zn.GetLaneSizeInBytes() == (zd.GetLaneSizeInBytes() * 2));
7466 Emit(0x45206c00 | SVESize(zn) | Rd(zd) | Rn(zn) | Rm(zm));
7488 void Assembler::MNE(const ZRegister& zd, const ZRegister& zn, int shift) { \
7490 VIXL_ASSERT(!zd.IsLaneSizeD() && !zd.IsLaneSizeQ()); \
7491 VIXL_ASSERT(zn.GetLaneSizeInBytes() == (zd.GetLaneSizeInBytes() * 2)); \
7493 EncodeSVEShiftRightImmediate(shift, zd.GetLaneSizeInBits()); \
7494 SVEBitwiseShiftImmediate(zd, zn, encoded_imm, X); \
7499 void Assembler::rsubhnb(const ZRegister& zd,
7508 VIXL_ASSERT(zn.GetLaneSizeInBytes() == (zd.GetLaneSizeInBytes() * 2));
7511 Emit(0x45207800 | SVESize(zn) | Rd(zd) | Rn(zn) | Rm(zm));
7514 void Assembler::rsubhnt(const ZRegister& zd,
7523 VIXL_ASSERT(zn.GetLaneSizeInBytes() == (zd.GetLaneSizeInBytes() * 2));
7526 Emit(0x45207c00 | SVESize(zn) | Rd(zd) | Rn(zn) | Rm(zm));
7572 void Assembler::sabdlb(const ZRegister& zd,
7582 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
7583 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
7585 Emit(0x45003000 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
7588 void Assembler::sabdlt(const ZRegister& zd,
7598 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
7599 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
7601 Emit(0x45003400 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
7618 void Assembler::saddlb(const ZRegister& zd,
7628 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
7629 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
7631 Emit(0x45000000 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
7634 void Assembler::saddlbt(const ZRegister& zd,
7643 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
7644 VIXL_ASSERT(zd.IsLaneSizeD() || zd.IsLaneSizeH() || zd.IsLaneSizeS());
7646 Emit(0x45008000 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
7649 void Assembler::saddlt(const ZRegister& zd,
7659 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
7660 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
7662 Emit(0x45000400 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
7665 void Assembler::saddwb(const ZRegister& zd,
7673 VIXL_ASSERT(AreSameLaneSize(zd, zn));
7674 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zm.GetLaneSizeInBytes() * 2));
7675 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
7677 Emit(0x45004000 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
7680 void Assembler::saddwt(const ZRegister& zd,
7688 VIXL_ASSERT(AreSameLaneSize(zd, zn));
7689 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zm.GetLaneSizeInBytes() * 2));
7690 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
7692 Emit(0x45004400 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
7725 void Assembler::shadd(const ZRegister& zd,
7735 VIXL_ASSERT(zd.Is(zn));
7736 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
7738 Emit(0x44108000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
7741 void Assembler::shsub(const ZRegister& zd,
7751 VIXL_ASSERT(zd.Is(zn));
7752 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
7754 Emit(0x44128000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
7757 void Assembler::shsubr(const ZRegister& zd,
7767 VIXL_ASSERT(zd.Is(zn));
7768 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
7770 Emit(0x44168000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
7773 void Assembler::sli(const ZRegister& zd, const ZRegister& zn, int shift) {
7779 VIXL_ASSERT(AreSameLaneSize(zd, zn));
7781 EncodeSVEShiftLeftImmediate(shift, zd.GetLaneSizeInBits());
7783 SVEBitwiseShiftImmediate(zd, zn, encoded_imm, 0x4500f400);
7786 void Assembler::smaxp(const ZRegister& zd,
7796 VIXL_ASSERT(zd.Is(zn));
7797 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
7799 Emit(0x4414a000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
7802 void Assembler::sminp(const ZRegister& zd,
7812 VIXL_ASSERT(zd.Is(zn));
7813 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
7815 Emit(0x4416a000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
7909 void Assembler::smulh(const ZRegister& zd,
7917 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
7919 Emit(0x04206800 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
7922 void Assembler::smullb(const ZRegister& zd,
7931 VIXL_ASSERT(!zd.IsLaneSizeB() && !zd.IsLaneSizeQ());
7932 VIXL_ASSERT(zd.GetLaneSizeInBytes() == zn.GetLaneSizeInBytes() * 2);
7934 Emit(0x45007000 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
7937 void Assembler::smullt(const ZRegister& zd,
7946 VIXL_ASSERT(!zd.IsLaneSizeB() && !zd.IsLaneSizeQ());
7947 VIXL_ASSERT(zd.GetLaneSizeInBytes() == zn.GetLaneSizeInBytes() * 2);
7949 Emit(0x45007400 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
7952 void Assembler::sqabs(const ZRegister& zd,
7960 VIXL_ASSERT(AreSameLaneSize(zd, zn));
7962 Emit(0x4408a000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
7965 void Assembler::sqadd(const ZRegister& zd,
7975 VIXL_ASSERT(zd.Is(zn));
7976 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
7978 Emit(0x44188000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
7981 void Assembler::sqcadd(const ZRegister& zd,
7991 VIXL_ASSERT(zd.Is(zn));
7992 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
7996 Emit(0x4501d800 | rotate_bit | SVESize(zd) | Rd(zd) | Rn(zm));
8221 void Assembler::sqdmulh(const ZRegister& zd,
8230 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
8232 Instr synthesised_op = SVEMulIndexHelper(zd.GetLaneSizeInBytesLog2(),
8239 Emit(synthesised_op | Rd(zd) | Rn(zn));
8242 void Assembler::sqdmulh(const ZRegister& zd,
8250 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
8252 Emit(0x04207000 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
8255 void Assembler::sqdmullb(const ZRegister& zd,
8264 VIXL_ASSERT(!zd.IsLaneSizeB() && !zd.IsLaneSizeQ());
8265 VIXL_ASSERT(zd.GetLaneSizeInBytes() == zn.GetLaneSizeInBytes() * 2);
8267 Emit(0x45006000 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
8270 void Assembler::sqdmullt(const ZRegister& zd,
8279 VIXL_ASSERT(!zd.IsLaneSizeB() && !zd.IsLaneSizeQ());
8280 VIXL_ASSERT(zd.GetLaneSizeInBytes() == zn.GetLaneSizeInBytes() * 2);
8282 Emit(0x45006400 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
8285 void Assembler::sqneg(const ZRegister& zd,
8293 VIXL_ASSERT(AreSameLaneSize(zd, zn));
8295 Emit(0x4409a000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
8410 void Assembler::sqrdmulh(const ZRegister& zd,
8419 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
8421 Instr synthesised_op = SVEMulIndexHelper(zd.GetLaneSizeInBytesLog2(),
8428 Emit(synthesised_op | Rd(zd) | Rn(zn));
8431 void Assembler::sqrdmulh(const ZRegister& zd,
8439 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
8441 Emit(0x04207400 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
8444 void Assembler::sqrshl(const ZRegister& zd,
8455 VIXL_ASSERT(zd.Is(zn));
8456 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
8458 Emit(0x440a8000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
8461 void Assembler::sqrshlr(const ZRegister& zd,
8472 VIXL_ASSERT(zd.Is(zn));
8473 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
8475 Emit(0x440e8000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
8478 void Assembler::sqshl(const ZRegister& zd,
8489 VIXL_ASSERT(zd.Is(zn));
8491 EncodeSVEShiftLeftImmediate(shift, zd.GetLaneSizeInBits());
8492 SVEBitwiseShiftImmediatePred(zd, pg, encoded_imm, 0x04068000);
8495 void Assembler::sqshl(const ZRegister& zd,
8506 VIXL_ASSERT(zd.Is(zn));
8507 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
8509 Emit(0x44088000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
8512 void Assembler::sqshlr(const ZRegister& zd,
8523 VIXL_ASSERT(zd.Is(zn));
8524 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
8526 Emit(0x440c8000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
8529 void Assembler::sqshlu(const ZRegister& zd,
8540 VIXL_ASSERT(zd.Is(zn));
8543 EncodeSVEShiftLeftImmediate(shift, zd.GetLaneSizeInBits());
8544 SVEBitwiseShiftImmediatePred(zd, pg, encoded_imm, 0x040f8000);
8547 void Assembler::sqsub(const ZRegister& zd,
8557 VIXL_ASSERT(zd.Is(zn));
8558 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
8560 Emit(0x441a8000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
8563 void Assembler::sqsubr(const ZRegister& zd,
8573 VIXL_ASSERT(zd.Is(zn));
8574 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
8576 Emit(0x441e8000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
8579 void Assembler::sqxtnb(const ZRegister& zd, const ZRegister& zn) {
8585 VIXL_ASSERT(zd.IsLaneSizeS() || zd.IsLaneSizeH() || zd.IsLaneSizeB());
8586 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() / 2));
8589 Instr size = EncodeSVEShiftLeftImmediate(0, zd.GetLaneSizeInBits());
8590 SVEBitwiseShiftImmediate(zd, zn, size, 0x45204000);
8593 void Assembler::sqxtnt(const ZRegister& zd, const ZRegister& zn) {
8599 VIXL_ASSERT(zd.IsLaneSizeS() || zd.IsLaneSizeH() || zd.IsLaneSizeB());
8600 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() / 2));
8603 Instr size = EncodeSVEShiftLeftImmediate(0, zd.GetLaneSizeInBits());
8604 SVEBitwiseShiftImmediate(zd, zn, size, 0x45204400);
8607 void Assembler::sqxtunb(const ZRegister& zd, const ZRegister& zn) {
8613 VIXL_ASSERT(zd.IsLaneSizeS() || zd.IsLaneSizeH() || zd.IsLaneSizeB());
8614 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() / 2));
8617 Instr size = EncodeSVEShiftLeftImmediate(0, zd.GetLaneSizeInBits());
8618 SVEBitwiseShiftImmediate(zd, zn, size, 0x45205000);
8621 void Assembler::sqxtunt(const ZRegister& zd, const ZRegister& zn) {
8627 VIXL_ASSERT(zd.IsLaneSizeS() || zd.IsLaneSizeH() || zd.IsLaneSizeB());
8628 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() / 2));
8631 Instr size = EncodeSVEShiftLeftImmediate(0, zd.GetLaneSizeInBits());
8632 SVEBitwiseShiftImmediate(zd, zn, size, 0x45205400);
8635 void Assembler::srhadd(const ZRegister& zd,
8645 VIXL_ASSERT(zd.Is(zn));
8646 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
8648 Emit(0x44148000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
8651 void Assembler::sri(const ZRegister& zd, const ZRegister& zn, int shift) {
8657 VIXL_ASSERT(AreSameLaneSize(zd, zn));
8659 EncodeSVEShiftRightImmediate(shift, zd.GetLaneSizeInBits());
8661 SVEBitwiseShiftImmediate(zd, zn, encoded_imm, 0x4500f000);
8664 void Assembler::srshl(const ZRegister& zd,
8675 VIXL_ASSERT(zd.Is(zn));
8676 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
8678 Emit(0x44028000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
8681 void Assembler::srshlr(const ZRegister& zd,
8692 VIXL_ASSERT(zd.Is(zn));
8693 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
8695 Emit(0x44068000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
8698 void Assembler::srshr(const ZRegister& zd,
8709 VIXL_ASSERT(zd.Is(zn));
8711 EncodeSVEShiftRightImmediate(shift, zd.GetLaneSizeInBits());
8712 SVEBitwiseShiftImmediatePred(zd, pg, encoded_imm, 0x040c8000);
8729 void Assembler::sshllb(const ZRegister& zd, const ZRegister& zn, int shift) {
8735 VIXL_ASSERT(!zd.IsLaneSizeB());
8736 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
8740 SVEBitwiseShiftImmediate(zd, zn, encoded_imm, 0x4500a000);
8743 void Assembler::sshllt(const ZRegister& zd, const ZRegister& zn, int shift) {
8749 VIXL_ASSERT(!zd.IsLaneSizeB());
8750 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
8754 SVEBitwiseShiftImmediate(zd, zn, encoded_imm, 0x4500a400);
8771 void Assembler::ssublb(const ZRegister& zd,
8781 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
8782 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
8784 Emit(0x45001000 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
8787 void Assembler::ssublbt(const ZRegister& zd,
8796 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
8797 VIXL_ASSERT(zd.IsLaneSizeD() || zd.IsLaneSizeH() || zd.IsLaneSizeS());
8799 Emit(0x45008800 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
8802 void Assembler::ssublt(const ZRegister& zd,
8812 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
8813 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
8815 Emit(0x45001400 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
8818 void Assembler::ssubltb(const ZRegister& zd,
8827 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
8828 VIXL_ASSERT(zd.IsLaneSizeD() || zd.IsLaneSizeH() || zd.IsLaneSizeS());
8830 Emit(0x45008c00 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
8833 void Assembler::ssubwb(const ZRegister& zd,
8841 VIXL_ASSERT(AreSameLaneSize(zd, zn));
8842 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zm.GetLaneSizeInBytes() * 2));
8843 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
8845 Emit(0x45005000 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
8848 void Assembler::ssubwt(const ZRegister& zd,
8856 VIXL_ASSERT(AreSameLaneSize(zd, zn));
8857 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zm.GetLaneSizeInBytes() * 2));
8858 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
8860 Emit(0x45005400 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
8914 void Assembler::subhnb(const ZRegister& zd,
8923 VIXL_ASSERT(zn.GetLaneSizeInBytes() == (zd.GetLaneSizeInBytes() * 2));
8926 Emit(0x45207000 | SVESize(zn) | Rd(zd) | Rn(zn) | Rm(zm));
8929 void Assembler::subhnt(const ZRegister& zd,
8938 VIXL_ASSERT(zn.GetLaneSizeInBytes() == (zd.GetLaneSizeInBytes() * 2));
8941 Emit(0x45207400 | SVESize(zn) | Rd(zd) | Rn(zn) | Rm(zm));
8944 void Assembler::suqadd(const ZRegister& zd,
8954 VIXL_ASSERT(zd.Is(zn));
8955 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
8957 Emit(0x441c8000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
8960 void Assembler::tbl(const ZRegister& zd,
8971 VIXL_ASSERT(AreSameLaneSize(zd, zn1, zn2, zm));
8973 Emit(0x05202800 | SVESize(zd) | Rd(zd) | Rn(zn1) | Rn(zn2) | Rm(zm));
8976 void Assembler::tbx(const ZRegister& zd,
8984 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
8986 Emit(0x05202c00 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
9032 void Assembler::uabdlb(const ZRegister& zd,
9042 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
9043 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
9045 Emit(0x45003800 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
9048 void Assembler::uabdlt(const ZRegister& zd,
9058 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
9059 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
9061 Emit(0x45003c00 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
9078 void Assembler::uaddlb(const ZRegister& zd,
9088 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
9089 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
9091 Emit(0x45000800 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
9094 void Assembler::uaddlt(const ZRegister& zd,
9104 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
9105 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
9107 Emit(0x45000c00 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
9110 void Assembler::uaddwb(const ZRegister& zd,
9118 VIXL_ASSERT(AreSameLaneSize(zd, zn));
9119 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zm.GetLaneSizeInBytes() * 2));
9120 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
9122 Emit(0x45004800 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
9125 void Assembler::uaddwt(const ZRegister& zd,
9133 VIXL_ASSERT(AreSameLaneSize(zd, zn));
9134 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zm.GetLaneSizeInBytes() * 2));
9135 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
9137 Emit(0x45004c00 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
9140 void Assembler::uhadd(const ZRegister& zd,
9150 VIXL_ASSERT(zd.Is(zn));
9151 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9153 Emit(0x44118000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
9156 void Assembler::uhsub(const ZRegister& zd,
9166 VIXL_ASSERT(zd.Is(zn));
9167 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9169 Emit(0x44138000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
9172 void Assembler::uhsubr(const ZRegister& zd,
9182 VIXL_ASSERT(zd.Is(zn));
9183 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9185 Emit(0x44178000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
9188 void Assembler::umaxp(const ZRegister& zd,
9198 VIXL_ASSERT(zd.Is(zn));
9199 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9201 Emit(0x4415a000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
9204 void Assembler::uminp(const ZRegister& zd,
9214 VIXL_ASSERT(zd.Is(zn));
9215 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9217 Emit(0x4417a000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
9280 void Assembler::umulh(const ZRegister& zd,
9288 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9290 Emit(0x04206c00 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
9293 void Assembler::umullb(const ZRegister& zd,
9302 VIXL_ASSERT(!zd.IsLaneSizeB() && !zd.IsLaneSizeQ());
9303 VIXL_ASSERT(zd.GetLaneSizeInBytes() == zn.GetLaneSizeInBytes() * 2);
9305 Emit(0x45007800 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
9308 void Assembler::umullt(const ZRegister& zd,
9317 VIXL_ASSERT(!zd.IsLaneSizeB() && !zd.IsLaneSizeQ());
9318 VIXL_ASSERT(zd.GetLaneSizeInBytes() == zn.GetLaneSizeInBytes() * 2);
9320 Emit(0x45007c00 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
9323 void Assembler::uqadd(const ZRegister& zd,
9333 VIXL_ASSERT(zd.Is(zn));
9334 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9336 Emit(0x44198000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
9339 void Assembler::uqrshl(const ZRegister& zd,
9350 VIXL_ASSERT(zd.Is(zn));
9351 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9353 Emit(0x440b8000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
9356 void Assembler::uqrshlr(const ZRegister& zd,
9367 VIXL_ASSERT(zd.Is(zn));
9368 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9370 Emit(0x440f8000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
9373 void Assembler::uqshl(const ZRegister& zd,
9384 VIXL_ASSERT(zd.Is(zn));
9386 EncodeSVEShiftLeftImmediate(shift, zd.GetLaneSizeInBits());
9387 SVEBitwiseShiftImmediatePred(zd, pg, encoded_imm, 0x04078000);
9390 void Assembler::uqshl(const ZRegister& zd,
9401 VIXL_ASSERT(zd.Is(zn));
9402 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9404 Emit(0x44098000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
9407 void Assembler::uqshlr(const ZRegister& zd,
9418 VIXL_ASSERT(zd.Is(zn));
9419 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9421 Emit(0x440d8000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
9424 void Assembler::uqsub(const ZRegister& zd,
9434 VIXL_ASSERT(zd.Is(zn));
9435 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9437 Emit(0x441b8000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
9440 void Assembler::uqsubr(const ZRegister& zd,
9450 VIXL_ASSERT(zd.Is(zn));
9451 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9453 Emit(0x441f8000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
9456 void Assembler::uqxtnb(const ZRegister& zd, const ZRegister& zn) {
9462 VIXL_ASSERT(zd.IsLaneSizeS() || zd.IsLaneSizeH() || zd.IsLaneSizeB());
9463 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() / 2));
9466 Instr size = EncodeSVEShiftLeftImmediate(0, zd.GetLaneSizeInBits());
9467 SVEBitwiseShiftImmediate(zd, zn, size, 0x45204800);
9470 void Assembler::uqxtnt(const ZRegister& zd, const ZRegister& zn) {
9476 VIXL_ASSERT(zd.IsLaneSizeS() || zd.IsLaneSizeH() || zd.IsLaneSizeB());
9477 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() / 2));
9480 Instr size = EncodeSVEShiftLeftImmediate(0, zd.GetLaneSizeInBits());
9481 SVEBitwiseShiftImmediate(zd, zn, size, 0x45204c00);
9484 void Assembler::urecpe(const ZRegister& zd,
9492 VIXL_ASSERT(zd.IsLaneSizeS() && zn.IsLaneSizeS());
9494 Emit(0x4400a000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
9497 void Assembler::urhadd(const ZRegister& zd,
9507 VIXL_ASSERT(zd.Is(zn));
9508 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9510 Emit(0x44158000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
9513 void Assembler::urshl(const ZRegister& zd,
9524 VIXL_ASSERT(zd.Is(zn));
9525 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9527 Emit(0x44038000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
9530 void Assembler::urshlr(const ZRegister& zd,
9541 VIXL_ASSERT(zd.Is(zn));
9542 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9544 Emit(0x44078000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
9547 void Assembler::urshr(const ZRegister& zd,
9558 VIXL_ASSERT(zd.Is(zn));
9560 EncodeSVEShiftRightImmediate(shift, zd.GetLaneSizeInBits());
9561 SVEBitwiseShiftImmediatePred(zd, pg, encoded_imm, 0x040d8000);
9564 void Assembler::ursqrte(const ZRegister& zd,
9572 VIXL_ASSERT(zd.IsLaneSizeS() && zn.IsLaneSizeS());
9574 Emit(0x4401a000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
9591 void Assembler::ushllb(const ZRegister& zd, const ZRegister& zn, int shift) {
9597 VIXL_ASSERT(!zd.IsLaneSizeB());
9598 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
9602 SVEBitwiseShiftImmediate(zd, zn, encoded_imm, 0x4500a800);
9605 void Assembler::ushllt(const ZRegister& zd, const ZRegister& zn, int shift) {
9611 VIXL_ASSERT(!zd.IsLaneSizeB());
9612 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
9616 SVEBitwiseShiftImmediate(zd, zn, encoded_imm, 0x4500ac00);
9619 void Assembler::usqadd(const ZRegister& zd,
9629 VIXL_ASSERT(zd.Is(zn));
9630 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9632 Emit(0x441d8000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
9649 void Assembler::usublb(const ZRegister& zd,
9659 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
9660 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
9662 Emit(0x45001800 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
9665 void Assembler::usublt(const ZRegister& zd,
9675 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
9676 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
9678 Emit(0x45001c00 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
9681 void Assembler::usubwb(const ZRegister& zd,
9689 VIXL_ASSERT(AreSameLaneSize(zd, zn));
9690 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zm.GetLaneSizeInBytes() * 2));
9691 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
9693 Emit(0x45005800 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
9696 void Assembler::usubwt(const ZRegister& zd,
9704 VIXL_ASSERT(AreSameLaneSize(zd, zn));
9705 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zm.GetLaneSizeInBytes() * 2));
9706 VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
9708 Emit(0x45005c00 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
9797 void Assembler::xar(const ZRegister& zd,
9807 VIXL_ASSERT(zd.Is(zn));
9808 VIXL_ASSERT(AreSameLaneSize(zd, zm));
9811 EncodeSVEShiftRightImmediate(shift, zd.GetLaneSizeInBits());
9812 SVEBitwiseShiftImmediate(zd, zm, encoded_imm, 0x04203400);