Lines Matching defs:zt1
3834 const ZRegister& zt1,
3840 unsigned msize_in_bytes_log2 = zt1.GetLaneSizeInBytesLog2();
3844 Emit(op | mem_op | msz | num | Rt(zt1) | PgLow8(pg));
4042 const ZRegister& zt1,
4059 SVELdSt234Helper(num_regs, zt1, pg, addr, op);
4072 void Assembler::ld2##MSZ(const ZRegister& zt1, \
4078 VIXL_ASSERT(AreConsecutive(zt1, zt2)); \
4079 VIXL_ASSERT(AreSameFormat(zt1, zt2)); \
4080 VIXL_ASSERT(zt1.IsLaneSize##LANE_SIZE()); \
4081 SVELd234Helper(2, zt1, pg, addr); \
4084 void Assembler::ld3##MSZ(const ZRegister& zt1, \
4091 VIXL_ASSERT(AreConsecutive(zt1, zt2, zt3)); \
4092 VIXL_ASSERT(AreSameFormat(zt1, zt2, zt3)); \
4093 VIXL_ASSERT(zt1.IsLaneSize##LANE_SIZE()); \
4094 SVELd234Helper(3, zt1, pg, addr); \
4097 void Assembler::ld4##MSZ(const ZRegister& zt1, \
4105 VIXL_ASSERT(AreConsecutive(zt1, zt2, zt3, zt4)); \
4106 VIXL_ASSERT(AreSameFormat(zt1, zt2, zt3, zt4)); \
4107 VIXL_ASSERT(zt1.IsLaneSize##LANE_SIZE()); \
4108 SVELd234Helper(4, zt1, pg, addr); \
5159 const ZRegister& zt1,
5176 SVELdSt234Helper(num_regs, zt1, pg, addr, op);
5187 void Assembler::st2##MSZ(const ZRegister& zt1, \
5193 VIXL_ASSERT(AreConsecutive(zt1, zt2)); \
5194 VIXL_ASSERT(AreSameFormat(zt1, zt2)); \
5195 VIXL_ASSERT(zt1.IsLaneSize##LANE_SIZE()); \
5196 SVESt234Helper(2, zt1, pg, addr); \
5199 void Assembler::st3##MSZ(const ZRegister& zt1, \
5206 VIXL_ASSERT(AreConsecutive(zt1, zt2, zt3)); \
5207 VIXL_ASSERT(AreSameFormat(zt1, zt2, zt3)); \
5208 VIXL_ASSERT(zt1.IsLaneSize##LANE_SIZE()); \
5209 SVESt234Helper(3, zt1, pg, addr); \
5212 void Assembler::st4##MSZ(const ZRegister& zt1, \
5220 VIXL_ASSERT(AreConsecutive(zt1, zt2, zt3, zt4)); \
5221 VIXL_ASSERT(AreSameFormat(zt1, zt2, zt3, zt4)); \
5222 VIXL_ASSERT(zt1.IsLaneSize##LANE_SIZE()); \
5223 SVESt234Helper(4, zt1, pg, addr); \