Lines Matching defs:zt
3820 const ZRegister& zt,
3829 SVEDtype(msize_in_bytes_log2, zt.GetLaneSizeInBytesLog2(), is_signed);
3830 Emit(op | mem_op | dtype | Rt(zt) | PgLow8(pg));
3848 const ZRegister& zt,
3852 VIXL_ASSERT(zt.GetLaneSizeInBytesLog2() >= msize_in_bytes_log2);
3856 VIXL_ASSERT(zt.GetLaneSizeInBytesLog2() != msize_in_bytes_log2);
3863 zt,
3882 SVELdSt1Helper(msize_in_bytes_log2, zt, pg, addr, is_signed, op);
3886 const ZRegister& zt,
3890 VIXL_ASSERT(zt.GetLaneSizeInBytesLog2() >= msize_in_bytes_log2);
3894 VIXL_ASSERT(zt.GetLaneSizeInBytesLog2() != msize_in_bytes_log2);
3901 zt,
3917 zt,
3930 SVELdSt1Helper(msize_in_bytes_log2, zt, pg, addr, is_signed, op);
3934 const ZRegister& zt,
3941 VIXL_ASSERT(zt.IsLaneSizeS() || zt.IsLaneSizeD());
3947 VIXL_ASSERT(AreSameLaneSize(zt, addr.GetVectorBase()));
3949 if (zt.IsLaneSizeS()) {
3955 if (zt.IsLaneSizeS()) {
3963 VIXL_ASSERT(AreSameLaneSize(zt, addr.GetVectorOffset()));
3965 if (zt.IsLaneSizeS()) {
3990 } else if (zt.IsLaneSizeD()) {
4038 Emit(op | mem_op | msz | u | ff | Rt(zt) | PgLow8(pg));
4065 void Assembler::ld1##MSZ(const ZRegister& zt, \
4069 SVELd1Helper(k##LANE_SIZE##RegSizeInBytesLog2, zt, pg, addr, false); \
4117 void Assembler::ld1s##MSZ(const ZRegister& zt, \
4121 SVELd1Helper(k##LANE_SIZE##RegSizeInBytesLog2, zt, pg, addr, true); \
4128 const ZRegister& zt,
4133 VIXL_ASSERT(zt.GetLaneSizeInBytesLog2() >= msize_in_bytes_log2);
4137 VIXL_ASSERT(zt.GetLaneSizeInBytesLog2() != msize_in_bytes_log2);
4144 zt.GetLaneSizeInBytesLog2(),
4148 ImmUnsignedField<21, 16>(imm / divisor) | Rt(zt) | PgLow8(pg));
4156 void Assembler::ld1rb(const ZRegister& zt,
4161 SVELd1BroadcastHelper(kBRegSizeInBytesLog2, zt, pg, addr, false);
4168 void Assembler::ld1rh(const ZRegister& zt,
4173 SVELd1BroadcastHelper(kHRegSizeInBytesLog2, zt, pg, addr, false);
4179 void Assembler::ld1rw(const ZRegister& zt,
4184 SVELd1BroadcastHelper(kSRegSizeInBytesLog2, zt, pg, addr, false);
4187 void Assembler::ld1rd(const ZRegister& zt,
4192 SVELd1BroadcastHelper(kDRegSizeInBytesLog2, zt, pg, addr, false);
4199 void Assembler::ld1rsb(const ZRegister& zt,
4204 SVELd1BroadcastHelper(kBRegSizeInBytesLog2, zt, pg, addr, true);
4210 void Assembler::ld1rsh(const ZRegister& zt,
4215 SVELd1BroadcastHelper(kHRegSizeInBytesLog2, zt, pg, addr, true);
4218 void Assembler::ld1rsw(const ZRegister& zt,
4223 SVELd1BroadcastHelper(kWRegSizeInBytesLog2, zt, pg, addr, true);
4251 void Assembler::ldff1b(const ZRegister& zt,
4262 Emit(LDFF1B_z_p_bz_d_64_unscaled | Rt(zt) | PgLow8(pg) | RnSP(xn) | Rm(zm));
4268 void Assembler::ldff1b(const ZRegister& zt,
4279 Emit(LDFF1B_z_p_ai_d | Rt(zt) | PgLow8(pg) | Rn(zn) | ImmField<20, 16>(imm5));
4287 void Assembler::ldff1d(const ZRegister& zt,
4298 Emit(LDFF1D_z_p_bz_d_64_scaled | Rt(zt) | PgLow8(pg) | RnSP(xn) | Rm(zm));
4301 void Assembler::ldff1d(const ZRegister& zt,
4312 Emit(LDFF1D_z_p_ai_d | Rt(zt) | PgLow8(pg) | Rn(zn) | ImmField<20, 16>(imm5));
4320 void Assembler::ldff1h(const ZRegister& zt,
4331 Emit(LDFF1H_z_p_bz_d_64_scaled | Rt(zt) | PgLow8(pg) | RnSP(xn) | Rm(zm));
4337 void Assembler::ldff1h(const ZRegister& zt,
4348 Emit(LDFF1H_z_p_ai_d | Rt(zt) | PgLow8(pg) | Rn(zn) | ImmField<20, 16>(imm5));
4354 void Assembler::ldff1sb(const ZRegister& zt,
4365 Emit(LDFF1SB_z_p_bz_d_64_unscaled | Rt(zt) | PgLow8(pg) | RnSP(xn) | Rm(zm));
4371 void Assembler::ldff1sb(const ZRegister& zt,
4382 Emit(LDFF1SB_z_p_ai_d | Rt(zt) | PgLow8(pg) | Rn(zn) |
4391 void Assembler::ldff1sh(const ZRegister& zt,
4402 Emit(LDFF1SH_z_p_bz_d_64_scaled | Rt(zt) | PgLow8(pg) | RnSP(xn) | Rm(zm));
4408 void Assembler::ldff1sh(const ZRegister& zt,
4419 Emit(LDFF1SH_z_p_ai_d | Rt(zt) | PgLow8(pg) | Rn(zn) |
4428 void Assembler::ldff1sw(const ZRegister& zt,
4439 Emit(LDFF1SW_z_p_bz_d_64_scaled | Rt(zt) | PgLow8(pg) | RnSP(xn) | Rm(zm));
4442 void Assembler::ldff1sw(const ZRegister& zt,
4453 Emit(LDFF1SW_z_p_ai_d | Rt(zt) | PgLow8(pg) | Rn(zn) |
4462 void Assembler::ldff1w(const ZRegister& zt,
4473 Emit(LDFF1W_z_p_bz_d_64_scaled | Rt(zt) | PgLow8(pg) | RnSP(xn) | Rm(zm));
4479 void Assembler::ldff1w(const ZRegister& zt,
4490 Emit(LDFF1W_z_p_ai_d | Rt(zt) | PgLow8(pg) | Rn(zn) | ImmField<20, 16>(imm5));
4746 void Assembler::SVELd1St1ScaImmHelper(const ZRegister& zt,
4763 Emit(op | Rt(zt) | PgLow8(pg) | RnSP(addr.GetScalarBase()));
4766 void Assembler::SVELd1VecScaHelper(const ZRegister& zt,
4775 VIXL_ASSERT(AreSameLaneSize(zn, zt));
4783 Emit(op | Rt(zt) | PgLow8(pg) |
4787 void Assembler::SVESt1VecScaHelper(const ZRegister& zt,
4795 VIXL_ASSERT(AreSameLaneSize(zn, zt));
4800 Emit(op | Rt(zt) | PgLow8(pg) |
4815 void Assembler::ld1r##FN(const ZRegister& zt, \
4821 VIXL_ASSERT(zt.IsLaneSize##SZ()); \
4822 SVELd1St1ScaImmHelper(zt, pg, addr, SCA, IMM, BYTES); \
4829 void Assembler::ldff1##MSZ(const ZRegister& zt, \
4833 SVELdff1Helper(k##LANE_SIZE##RegSizeInBytesLog2, zt, pg, addr, false); \
4838 void Assembler::ldff1s##MSZ(const ZRegister& zt, \
4842 SVELdff1Helper(k##LANE_SIZE##RegSizeInBytesLog2, zt, pg, addr, true); \
4846 void Assembler::ldnf1b(const ZRegister& zt,
4855 zt,
4862 void Assembler::ldnf1d(const ZRegister& zt,
4871 zt,
4878 void Assembler::ldnf1h(const ZRegister& zt,
4887 zt,
4894 void Assembler::ldnf1sb(const ZRegister& zt,
4903 zt,
4910 void Assembler::ldnf1sh(const ZRegister& zt,
4919 zt,
4926 void Assembler::ldnf1sw(const ZRegister& zt,
4935 zt,
4942 void Assembler::ldnf1w(const ZRegister& zt,
4951 zt,
4958 void Assembler::ldnt1b(const ZRegister& zt,
4966 SVELd1VecScaHelper(zt, pg, addr, 0, /* is_signed = */ false);
4968 SVELd1St1ScaImmHelper(zt,
4976 void Assembler::ldnt1d(const ZRegister& zt,
4984 SVELd1VecScaHelper(zt, pg, addr, 3, /* is_signed = */ false);
4986 SVELd1St1ScaImmHelper(zt,
4994 void Assembler::ldnt1h(const ZRegister& zt,
5002 SVELd1VecScaHelper(zt, pg, addr, 1, /* is_signed = */ false);
5004 SVELd1St1ScaImmHelper(zt,
5012 void Assembler::ldnt1w(const ZRegister& zt,
5020 SVELd1VecScaHelper(zt, pg, addr, 2, /* is_signed = */ false);
5022 SVELd1St1ScaImmHelper(zt,
5030 void Assembler::ldnt1sb(const ZRegister& zt,
5034 SVELd1VecScaHelper(zt, pg, addr, 0, /* is_signed = */ true);
5037 void Assembler::ldnt1sh(const ZRegister& zt,
5041 SVELd1VecScaHelper(zt, pg, addr, 1, /* is_signed = */ true);
5044 void Assembler::ldnt1sw(const ZRegister& zt,
5048 SVELd1VecScaHelper(zt, pg, addr, 2, /* is_signed = */ true);
5124 const ZRegister& zt,
5137 zt,
5155 SVELdSt1Helper(msize_in_bytes_log2, zt, pg, addr, false, op);
5180 void Assembler::st1##MSZ(const ZRegister& zt, \
5184 SVESt1Helper(k##LANE_SIZE##RegSizeInBytesLog2, zt, pg, addr); \
5231 void Assembler::stnt1b(const ZRegister& zt,
5239 SVESt1VecScaHelper(zt, pg, addr, 0);
5241 SVELd1St1ScaImmHelper(zt,
5249 void Assembler::stnt1d(const ZRegister& zt,
5257 SVESt1VecScaHelper(zt, pg, addr, 3);
5259 SVELd1St1ScaImmHelper(zt,
5267 void Assembler::stnt1h(const ZRegister& zt,
5275 SVESt1VecScaHelper(zt, pg, addr, 1);
5277 SVELd1St1ScaImmHelper(zt,
5285 void Assembler::stnt1w(const ZRegister& zt,
5293 SVESt1VecScaHelper(zt, pg, addr, 2);
5295 SVELd1St1ScaImmHelper(zt,
8867 void Assembler::stnt1b(const ZRegister& zt, const PRegister& pg, const ZRegister& zn, const Register& rm) {
8874 Emit(0xe4002000 | Rt(zt) | PgLow8(pg) | Rn(zn) | Rm(rm));
8877 void Assembler::stnt1d(const ZRegister& zt, const PRegister& pg, const ZRegister& zn, const Register& rm) {
8884 Emit(0xe5802000 | Rt(zt) | PgLow8(pg) | Rn(zn) | Rm(rm));
8890 void Assembler::stnt1h(const ZRegister& zt, const PRegister& pg, const ZRegister& zn, const Register& rm) {
8897 Emit(0xe4802000 | Rt(zt) | PgLow8(pg) | Rn(zn) | Rm(rm));
8903 void Assembler::stnt1w(const ZRegister& zt, const PRegister& pg, const ZRegister& zn, const Register& rm) {
8910 Emit(0xe5002000 | Rt(zt) | PgLow8(pg) | Rn(zn) | Rm(rm));