Lines Matching defs:zn
100 void Assembler::and_(const ZRegister& zd, const ZRegister& zn, uint64_t imm) {
101 USE(zn);
103 VIXL_ASSERT(zd.Is(zn));
115 void Assembler::eor(const ZRegister& zd, const ZRegister& zn, uint64_t imm) {
116 USE(zn);
118 VIXL_ASSERT(zd.Is(zn));
122 void Assembler::orr(const ZRegister& zd, const ZRegister& zn, uint64_t imm) {
123 USE(zn);
125 VIXL_ASSERT(zd.Is(zn));
131 const ZRegister& zn,
135 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
136 Emit(AND_z_zz | Rd(zd) | Rn(zn) | Rm(zm));
140 const ZRegister& zn,
144 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
145 Emit(BIC_z_zz | Rd(zd) | Rn(zn) | Rm(zm));
149 const ZRegister& zn,
153 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
154 Emit(EOR_z_zz | Rd(zd) | Rn(zn) | Rm(zm));
158 const ZRegister& zn,
162 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
163 Emit(ORR_z_zz | Rd(zd) | Rn(zn) | Rm(zm));
180 const ZRegister& zn,
187 USE(zn);
189 VIXL_ASSERT(zd.Is(zn));
197 const ZRegister& zn,
204 USE(zn);
206 VIXL_ASSERT(zd.Is(zn));
207 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm) ||
211 if (AreSameLaneSize(zd, zn, zm)) {
219 const ZRegister& zn,
226 USE(zn);
228 VIXL_ASSERT(zd.Is(zn));
237 const ZRegister& zn,
244 USE(zn);
246 VIXL_ASSERT(zd.Is(zn));
247 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
254 const ZRegister& zn,
261 USE(zn);
263 VIXL_ASSERT(zd.Is(zn));
272 const ZRegister& zn,
279 USE(zn);
281 VIXL_ASSERT(zd.Is(zn));
282 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm) ||
286 if (AreSameLaneSize(zd, zn, zm)) {
294 const ZRegister& zn,
301 USE(zn);
303 VIXL_ASSERT(zd.Is(zn));
304 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
311 const ZRegister& zn,
318 USE(zn);
320 VIXL_ASSERT(zd.Is(zn));
329 const ZRegister& zn,
336 USE(zn);
338 VIXL_ASSERT(zd.Is(zn));
339 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm) ||
343 if (AreSameLaneSize(zd, zn, zm)) {
351 const ZRegister& zn,
358 USE(zn);
360 VIXL_ASSERT(zd.Is(zn));
361 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
380 const ZRegister& zn,
386 Emit(op | tszh | tszl_and_imm | Rd(zd) | Rn(zn));
389 void Assembler::asr(const ZRegister& zd, const ZRegister& zn, int shift) {
391 VIXL_ASSERT(AreSameLaneSize(zd, zn));
394 SVEBitwiseShiftImmediate(zd, zn, encoded_imm, ASR_z_zi);
398 const ZRegister& zn,
401 VIXL_ASSERT(AreSameLaneSize(zd, zn));
404 Emit(ASR_z_zw | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
407 void Assembler::lsl(const ZRegister& zd, const ZRegister& zn, int shift) {
411 SVEBitwiseShiftImmediate(zd, zn, encoded_imm, LSL_z_zi);
415 const ZRegister& zn,
418 VIXL_ASSERT(AreSameLaneSize(zd, zn));
421 Emit(LSL_z_zw | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
424 void Assembler::lsr(const ZRegister& zd, const ZRegister& zn, int shift) {
428 SVEBitwiseShiftImmediate(zd, zn, encoded_imm, LSR_z_zi);
432 const ZRegister& zn,
435 VIXL_ASSERT(AreSameLaneSize(zd, zn));
438 Emit(LSR_z_zw | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
572 const ZRegister& zn,
578 USE(zn);
580 VIXL_ASSERT(zd.Is(zn));
581 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
589 const ZRegister& zn,
595 USE(zn);
597 VIXL_ASSERT(zd.Is(zn));
598 VIXL_ASSERT(AreSameLaneSize(zd, zn));
608 const ZRegister& zn,
614 USE(zn);
616 VIXL_ASSERT(zd.Is(zn));
617 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
625 const ZRegister& zn,
631 USE(zn);
633 VIXL_ASSERT(zd.Is(zn));
634 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
642 const ZRegister& zn,
648 USE(zn);
650 VIXL_ASSERT(zd.Is(zn));
651 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
659 const ZRegister& zn,
665 USE(zn);
667 VIXL_ASSERT(zd.Is(zn));
668 VIXL_ASSERT(AreSameLaneSize(zd, zn));
678 const ZRegister& zn,
684 USE(zn);
686 VIXL_ASSERT(zd.Is(zn));
687 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
695 const ZRegister& zn,
701 USE(zn);
703 VIXL_ASSERT(zd.Is(zn));
704 VIXL_ASSERT(AreSameLaneSize(zd, zn));
714 const ZRegister& zn,
720 USE(zn);
722 VIXL_ASSERT(zd.Is(zn));
723 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
731 const ZRegister& zn,
737 USE(zn);
739 VIXL_ASSERT(zd.Is(zn));
740 VIXL_ASSERT(AreSameLaneSize(zd, zn));
750 const ZRegister& zn,
756 USE(zn);
758 VIXL_ASSERT(zd.Is(zn));
759 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
767 const ZRegister& zn,
773 USE(zn);
775 VIXL_ASSERT(zd.Is(zn));
776 VIXL_ASSERT(AreSameLaneSize(zd, zn));
786 const ZRegister& zn,
792 USE(zn);
794 VIXL_ASSERT(zd.Is(zn));
795 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
803 const ZRegister& zn,
809 USE(zn);
811 VIXL_ASSERT(zd.Is(zn));
812 VIXL_ASSERT(AreSameLaneSize(zd, zn));
822 const ZRegister& zn,
828 USE(zn);
830 VIXL_ASSERT(zd.Is(zn));
831 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
839 const ZRegister& zn,
845 USE(zn);
847 VIXL_ASSERT(zd.Is(zn));
848 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
856 const ZRegister& zn,
862 USE(zn);
864 VIXL_ASSERT(zd.Is(zn));
865 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
873 const ZRegister& zn,
879 USE(zn);
881 VIXL_ASSERT(zd.Is(zn));
882 VIXL_ASSERT(AreSameLaneSize(zd, zn));
892 const ZRegister& zn,
898 USE(zn);
900 VIXL_ASSERT(zd.Is(zn));
901 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
909 const ZRegister& zn,
915 USE(zn);
917 VIXL_ASSERT(zd.Is(zn));
918 VIXL_ASSERT(AreSameLaneSize(zd, zn));
928 const ZRegister& zn,
934 USE(zn);
936 VIXL_ASSERT(zd.Is(zn));
937 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
944 const ZRegister& zn,
951 USE(zn);
953 VIXL_ASSERT(zd.Is(zn));
954 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
964 const ZRegister& zn,
971 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
974 Emit(FADD_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
978 const ZRegister& zn,
985 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
988 Emit(FMUL_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
992 const ZRegister& zn,
999 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
1002 Emit(FRECPS_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
1006 const ZRegister& zn,
1013 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
1016 Emit(FRSQRTS_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
1020 const ZRegister& zn,
1027 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
1030 Emit(FSUB_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
1034 const ZRegister& zn,
1041 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
1044 Emit(FTSMUL_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
1051 const ZRegister& zn,
1059 VIXL_ASSERT(AreSameLaneSize(zn, zm));
1060 VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
1062 Emit(FACGE_p_p_zz | SVESize(zn) | Pd(pd) | PgLow8(pg) | Rn(zn) | Rm(zm));
1067 const ZRegister& zn,
1075 VIXL_ASSERT(AreSameLaneSize(zn, zm));
1076 VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
1078 Emit(FACGT_p_p_zz | SVESize(zn) | Pd(pd) | PgLow8(pg) | Rn(zn) | Rm(zm));
1083 const ZRegister& zn,
1091 VIXL_ASSERT(AreSameLaneSize(zn, zm));
1092 VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
1094 Emit(FCMEQ_p_p_zz | SVESize(zn) | Pd(pd) | PgLow8(pg) | Rn(zn) | Rm(zm));
1099 const ZRegister& zn,
1107 VIXL_ASSERT(AreSameLaneSize(zn, zm));
1108 VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
1110 Emit(FCMGE_p_p_zz | SVESize(zn) | Pd(pd) | PgLow8(pg) | Rn(zn) | Rm(zm));
1115 const ZRegister& zn,
1123 VIXL_ASSERT(AreSameLaneSize(zn, zm));
1124 VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
1126 Emit(FCMGT_p_p_zz | SVESize(zn) | Pd(pd) | PgLow8(pg) | Rn(zn) | Rm(zm));
1131 const ZRegister& zn,
1139 VIXL_ASSERT(AreSameLaneSize(zn, zm));
1140 VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
1142 Emit(FCMNE_p_p_zz | SVESize(zn) | Pd(pd) | PgLow8(pg) | Rn(zn) | Rm(zm));
1147 const ZRegister& zn,
1155 VIXL_ASSERT(AreSameLaneSize(zn, zm));
1156 VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
1158 Emit(FCMUO_p_p_zz | SVESize(zn) | Pd(pd) | PgLow8(pg) | Rn(zn) | Rm(zm));
1165 const ZRegister& zn,
1173 VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
1177 Emit(FCMEQ_p_p_z0 | SVESize(zn) | Pd(pd) | PgLow8(pg) | Rn(zn));
1182 const ZRegister& zn,
1190 VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
1194 Emit(FCMGE_p_p_z0 | SVESize(zn) | Pd(pd) | PgLow8(pg) | Rn(zn));
1199 const ZRegister& zn,
1207 VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
1211 Emit(FCMGT_p_p_z0 | SVESize(zn) | Pd(pd) | PgLow8(pg) | Rn(zn));
1216 const ZRegister& zn,
1224 VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
1228 Emit(FCMLE_p_p_z0 | SVESize(zn) | Pd(pd) | PgLow8(pg) | Rn(zn));
1233 const ZRegister& zn,
1241 VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
1245 Emit(FCMLT_p_p_z0 | SVESize(zn) | Pd(pd) | PgLow8(pg) | Rn(zn));
1250 const ZRegister& zn,
1258 VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
1262 Emit(FCMNE_p_p_z0 | SVESize(zn) | Pd(pd) | PgLow8(pg) | Rn(zn));
1269 const ZRegister& zn,
1276 USE(zn);
1278 VIXL_ASSERT(zd.Is(zn));
1279 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
1291 const ZRegister& zn,
1299 VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
1305 Rn(zn) | Rm(zm));
1311 const ZRegister& zn,
1316 VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
1321 Rd(zda) | Rn(zn));
1328 const ZRegister& zn) {
1335 VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
1336 VIXL_ASSERT(AreSameLaneSize(zn, vd));
1338 Emit(FADDV_v_p_z | SVESize(zn) | Rd(vd) | PgLow8(pg) | Rn(zn));
1343 const ZRegister& zn) {
1350 VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
1351 VIXL_ASSERT(AreSameLaneSize(zn, vd));
1353 Emit(FMAXNMV_v_p_z | SVESize(zn) | Rd(vd) | PgLow8(pg) | Rn(zn));
1358 const ZRegister& zn) {
1365 VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
1366 VIXL_ASSERT(AreSameLaneSize(zn, vd));
1368 Emit(FMAXV_v_p_z | SVESize(zn) | Rd(vd) | PgLow8(pg) | Rn(zn));
1373 const ZRegister& zn) {
1380 VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
1381 VIXL_ASSERT(AreSameLaneSize(zn, vd));
1383 Emit(FMINNMV_v_p_z | SVESize(zn) | Rd(vd) | PgLow8(pg) | Rn(zn));
1388 const ZRegister& zn) {
1395 VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
1396 VIXL_ASSERT(AreSameLaneSize(zn, vd));
1398 Emit(FMINV_v_p_z | SVESize(zn) | Rd(vd) | PgLow8(pg) | Rn(zn));
1420 const ZRegister& zn,
1427 VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
1430 Emit(FMLA_z_p_zzz | SVESize(zda) | Rd(zda) | PgLow8(pg) | Rn(zn) | Rm(zm));
1435 const ZRegister& zn,
1442 VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
1445 Emit(FMLS_z_p_zzz | SVESize(zda) | Rd(zda) | PgLow8(pg) | Rn(zn) | Rm(zm));
1480 const ZRegister& zn,
1487 VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
1490 Emit(FNMLA_z_p_zzz | SVESize(zda) | Rd(zda) | PgLow8(pg) | Rn(zn) | Rm(zm));
1495 const ZRegister& zn,
1502 VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
1505 Emit(FNMLS_z_p_zzz | SVESize(zda) | Rd(zda) | PgLow8(pg) | Rn(zn) | Rm(zm));
1608 const ZRegister& zn,
1612 VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
1623 Emit(synthesized_op | Rd(zda) | Rn(zn));
1627 const ZRegister& zn,
1631 VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
1642 Emit(synthesized_op | Rd(zda) | Rn(zn));
1649 const ZRegister& zn,
1657 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
1668 Emit(synthesized_op | Rd(zd) | Rn(zn));
1675 const ZRegister& zn) {
1679 switch (zn.GetLaneSizeInBytes()) {
1713 Emit(op | Rd(zd) | PgLow8(pg) | Rn(zn));
1718 const ZRegister& zn) {
1721 switch (zn.GetLaneSizeInBytes()) {
1758 Emit(op | Rd(zd) | PgLow8(pg) | Rn(zn));
1763 const ZRegister& zn) {
1766 switch (zn.GetLaneSizeInBytes()) {
1803 Emit(op | Rd(zd) | PgLow8(pg) | Rn(zn));
1808 const ZRegister& zn) {
1814 VIXL_ASSERT(AreSameLaneSize(zd, zn));
1817 Emit(FRECPX_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
1822 const ZRegister& zn) {
1824 VIXL_ASSERT(AreSameLaneSize(zd, zn));
1827 Emit(FRINTA_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
1832 const ZRegister& zn) {
1834 VIXL_ASSERT(AreSameLaneSize(zd, zn));
1837 Emit(FRINTI_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
1842 const ZRegister& zn) {
1844 VIXL_ASSERT(AreSameLaneSize(zd, zn));
1847 Emit(FRINTM_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
1852 const ZRegister& zn) {
1854 VIXL_ASSERT(AreSameLaneSize(zd, zn));
1857 Emit(FRINTN_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
1862 const ZRegister& zn) {
1864 VIXL_ASSERT(AreSameLaneSize(zd, zn));
1867 Emit(FRINTP_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
1872 const ZRegister& zn) {
1874 VIXL_ASSERT(AreSameLaneSize(zd, zn));
1877 Emit(FRINTX_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
1882 const ZRegister& zn) {
1884 VIXL_ASSERT(AreSameLaneSize(zd, zn));
1887 Emit(FRINTZ_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
1892 const ZRegister& zn) {
1898 VIXL_ASSERT(AreSameLaneSize(zd, zn));
1901 Emit(FSQRT_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
1906 const ZRegister& zn) {
1909 switch (zn.GetLaneSizeInBytes()) {
1946 Emit(op | Rd(zd) | PgLow8(pg) | Rn(zn));
1951 const ZRegister& zn) {
1954 switch (zn.GetLaneSizeInBytes()) {
1991 Emit(op | Rd(zd) | PgLow8(pg) | Rn(zn));
1996 void Assembler::frecpe(const ZRegister& zd, const ZRegister& zn) {
2002 VIXL_ASSERT(AreSameLaneSize(zd, zn));
2005 Emit(FRECPE_z_z | SVESize(zd) | Rd(zd) | Rn(zn));
2008 void Assembler::frsqrte(const ZRegister& zd, const ZRegister& zn) {
2014 VIXL_ASSERT(AreSameLaneSize(zd, zn));
2017 Emit(FRSQRTE_z_z | SVESize(zd) | Rd(zd) | Rn(zn));
2255 const ZRegister& zn,
2262 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
2264 Emit(ADD_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
2268 const ZRegister& zn,
2275 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
2277 Emit(SQADD_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
2281 const ZRegister& zn,
2288 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
2290 Emit(SQSUB_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
2294 const ZRegister& zn,
2301 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
2303 Emit(SUB_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
2307 const ZRegister& zn,
2314 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
2316 Emit(UQADD_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
2320 const ZRegister& zn,
2327 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
2329 Emit(UQSUB_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
2336 const ZRegister& zn,
2342 USE(zn);
2344 VIXL_ASSERT(zd.Is(zn));
2345 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2352 const ZRegister& zn,
2358 USE(zn);
2360 VIXL_ASSERT(zd.Is(zn));
2361 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2368 const ZRegister& zn,
2374 USE(zn);
2376 VIXL_ASSERT(zd.Is(zn));
2377 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2384 const ZRegister& zn,
2390 USE(zn);
2392 VIXL_ASSERT(zd.Is(zn));
2393 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2400 const ZRegister& zn,
2406 USE(zn);
2408 VIXL_ASSERT(zd.Is(zn));
2409 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2416 const ZRegister& zn,
2422 USE(zn);
2424 VIXL_ASSERT(zd.Is(zn));
2425 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2432 const ZRegister& zn,
2438 USE(zn);
2440 VIXL_ASSERT(zd.Is(zn));
2441 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2448 const ZRegister& zn,
2454 USE(zn);
2456 VIXL_ASSERT(zd.Is(zn));
2457 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2465 const ZRegister& zn,
2471 USE(zn);
2473 VIXL_ASSERT(zd.Is(zn));
2474 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2482 const ZRegister& zn,
2488 USE(zn);
2490 VIXL_ASSERT(zd.Is(zn));
2491 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2498 const ZRegister& zn,
2504 USE(zn);
2506 VIXL_ASSERT(zd.Is(zn));
2507 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2514 const ZRegister& zn,
2520 USE(zn);
2522 VIXL_ASSERT(zd.Is(zn));
2523 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2530 const ZRegister& zn,
2536 USE(zn);
2538 VIXL_ASSERT(zd.Is(zn));
2539 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2546 const ZRegister& zn,
2552 USE(zn);
2554 VIXL_ASSERT(zd.Is(zn));
2555 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2562 const ZRegister& zn,
2568 USE(zn);
2570 VIXL_ASSERT(zd.Is(zn));
2571 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2578 const ZRegister& zn,
2584 USE(zn);
2586 VIXL_ASSERT(zd.Is(zn));
2587 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2595 const ZRegister& zn,
2601 USE(zn);
2603 VIXL_ASSERT(zd.Is(zn));
2604 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2612 const ZRegister& zn,
2618 USE(zn);
2620 VIXL_ASSERT(zd.Is(zn));
2621 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2628 const ZRegister& zn,
2634 USE(zn);
2636 VIXL_ASSERT(zd.Is(zn));
2637 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2644 const ZRegister& zn,
2650 USE(zn);
2652 VIXL_ASSERT(zd.Is(zn));
2653 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
2746 const ZRegister& zn,
2749 Emit(op | SVESize(zn) | Pd(pd) | PgLow8(pg) | Rn(zn) | Rm(zm));
2754 const ZRegister& zn,
2757 Emit(op | SVESize(zn) | Pd(pd) | PgLow8(pg) | Rn(zn) | ImmField<20, 16>(imm));
2762 const ZRegister& zn,
2765 Emit(op | SVESize(zn) | Pd(pd) | PgLow8(pg) | Rn(zn) |
2772 const ZRegister& zn,
2776 cmpeq(pd, pg, zn, zm);
2779 cmpge(pd, pg, zn, zm);
2782 cmpgt(pd, pg, zn, zm);
2785 cmple(pd, pg, zn, zm);
2788 cmplt(pd, pg, zn, zm);
2791 cmpne(pd, pg, zn, zm);
2794 cmphi(pd, pg, zn, zm);
2797 cmphs(pd, pg, zn, zm);
2800 cmplo(pd, pg, zn, zm);
2803 cmpls(pd, pg, zn, zm);
2814 const ZRegister& zn,
2822 VIXL_ASSERT(AreSameLaneSize(pd, zn));
2824 CompareVectors(pd, pg, zn, imm5, CMPEQ_p_p_zi);
2829 const ZRegister& zn,
2837 VIXL_ASSERT(AreSameLaneSize(pd, zn));
2839 CompareVectors(pd, pg, zn, imm5, CMPGE_p_p_zi);
2844 const ZRegister& zn,
2852 VIXL_ASSERT(AreSameLaneSize(pd, zn));
2854 CompareVectors(pd, pg, zn, imm5, CMPGT_p_p_zi);
2859 const ZRegister& zn,
2867 VIXL_ASSERT(AreSameLaneSize(pd, zn));
2869 CompareVectors(pd, pg, zn, imm5, CMPLE_p_p_zi);
2874 const ZRegister& zn,
2882 VIXL_ASSERT(AreSameLaneSize(pd, zn));
2884 CompareVectors(pd, pg, zn, imm5, CMPLT_p_p_zi);
2889 const ZRegister& zn,
2897 VIXL_ASSERT(AreSameLaneSize(pd, zn));
2899 CompareVectors(pd, pg, zn, imm5, CMPNE_p_p_zi);
2906 const ZRegister& zn,
2914 VIXL_ASSERT(AreSameLaneSize(pd, zn));
2916 CompareVectors(pd, pg, zn, imm7, CMPHI_p_p_zi);
2921 const ZRegister& zn,
2929 VIXL_ASSERT(AreSameLaneSize(pd, zn));
2931 CompareVectors(pd, pg, zn, imm7, CMPHS_p_p_zi);
2936 const ZRegister& zn,
2944 VIXL_ASSERT(AreSameLaneSize(pd, zn));
2946 CompareVectors(pd, pg, zn, imm7, CMPLO_p_p_zi);
2951 const ZRegister& zn,
2959 VIXL_ASSERT(AreSameLaneSize(pd, zn));
2961 CompareVectors(pd, pg, zn, imm7, CMPLS_p_p_zi);
2971 const ZRegister& zn,
2974 VIXL_ASSERT(AreSameLaneSize(pd, zn));
2976 if (!AreSameLaneSize(zn, zm)) {
2980 CompareVectors(pd, pg, zn, zm, op);
2988 const ZRegister& zn,
2991 VIXL_ASSERT(AreSameLaneSize(pd, zn));
2993 if (!AreSameLaneSize(zn, zm)) {
2997 CompareVectors(pd, pg, zn, zm, op);
3005 const ZRegister& zn,
3008 VIXL_ASSERT(AreSameLaneSize(pd, zn));
3010 if (!AreSameLaneSize(zn, zm)) {
3014 CompareVectors(pd, pg, zn, zm, op);
3022 const ZRegister& zn,
3025 VIXL_ASSERT(AreSameLaneSize(pd, zn));
3027 if (!AreSameLaneSize(zn, zm)) {
3031 CompareVectors(pd, pg, zn, zm, op);
3039 const ZRegister& zn,
3042 VIXL_ASSERT(AreSameLaneSize(pd, zn));
3044 if (!AreSameLaneSize(zn, zm)) {
3048 CompareVectors(pd, pg, zn, zm, op);
3053 const ZRegister& zn,
3056 VIXL_ASSERT(AreSameLaneSize(pd, zn));
3057 if (AreSameLaneSize(zn, zm)) {
3058 cmpge(pd, pg, zm, zn);
3062 VIXL_ASSERT(!zn.IsLaneSizeD());
3064 CompareVectors(pd, pg, zn, zm, CMPLE_p_p_zw);
3069 const ZRegister& zn,
3072 VIXL_ASSERT(AreSameLaneSize(pd, zn));
3073 if (AreSameLaneSize(zn, zm)) {
3074 cmphi(pd, pg, zm, zn);
3078 VIXL_ASSERT(!zn.IsLaneSizeD());
3080 CompareVectors(pd, pg, zn, zm, CMPLO_p_p_zw);
3085 const ZRegister& zn,
3088 VIXL_ASSERT(AreSameLaneSize(pd, zn));
3089 if (AreSameLaneSize(zn, zm)) {
3090 cmphs(pd, pg, zm, zn);
3094 VIXL_ASSERT(!zn.IsLaneSizeD());
3096 CompareVectors(pd, pg, zn, zm, CMPLS_p_p_zw);
3101 const ZRegister& zn,
3104 VIXL_ASSERT(AreSameLaneSize(pd, zn));
3105 if (AreSameLaneSize(zn, zm)) {
3106 cmpgt(pd, pg, zm, zn);
3110 VIXL_ASSERT(!zn.IsLaneSizeD());
3112 CompareVectors(pd, pg, zn, zm, CMPLT_p_p_zw);
3120 const ZRegister& zn,
3123 VIXL_ASSERT(AreSameLaneSize(pd, zn));
3125 if (!AreSameLaneSize(zn, zm)) {
3129 CompareVectors(pd, pg, zn, zm, op);
3134 void Assembler::fexpa(const ZRegister& zd, const ZRegister& zn) {
3140 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3143 Emit(FEXPA_z_z | SVESize(zd) | Rd(zd) | Rn(zn));
3147 const ZRegister& zn,
3154 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
3157 Emit(FTSSEL_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
3160 void Assembler::movprfx(const ZRegister& zd, const ZRegister& zn) {
3166 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3168 Emit(MOVPRFX_z_z | Rd(zd) | Rn(zn));
3189 const ZRegister& zn,
3196 VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
3198 Emit(MLA_z_p_zzz | SVESize(zda) | Rd(zda) | PgLow8(pg) | Rn(zn) | Rm(zm));
3203 const ZRegister& zn,
3210 VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
3212 Emit(MLS_z_p_zzz | SVESize(zda) | Rd(zda) | PgLow8(pg) | Rn(zn) | Rm(zm));
3232 const ZRegister& zn,
3236 VIXL_ASSERT(zda.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 4));
3237 VIXL_ASSERT(AreSameLaneSize(zm, zn));
3239 Emit(SDOT_z_zzz | SVESize(zda) | Rd(zda) | Rn(zn) | Rm(zm));
3243 const ZRegister& zn,
3247 VIXL_ASSERT(zda.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 4));
3248 VIXL_ASSERT(AreSameLaneSize(zm, zn));
3250 Emit(UDOT_z_zzz | SVESize(zda) | Rd(zda) | Rn(zn) | Rm(zm));
3257 const ZRegister& zn) {
3261 Emit(ANDV_r_p_z | SVESize(zn) | Rd(vd) | PgLow8(pg) | Rn(zn));
3266 const ZRegister& zn) {
3270 Emit(EORV_r_p_z | SVESize(zn) | Rd(vd) | PgLow8(pg) | Rn(zn));
3275 const ZRegister& zn) {
3281 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3286 Emit(MOVPRFX_z_p_z | SVESize(zd) | m | Rd(zd) | PgLow8(pg) | Rn(zn));
3291 const ZRegister& zn) {
3295 Emit(ORV_r_p_z | SVESize(zn) | Rd(vd) | PgLow8(pg) | Rn(zn));
3300 const ZRegister& zn) {
3302 VIXL_ASSERT(zn.GetLaneSizeInBytes() != kDRegSizeInBytes);
3304 Emit(SADDV_r_p_z | SVESize(zn) | Rd(dd) | PgLow8(pg) | Rn(zn));
3309 const ZRegister& zn) {
3313 Emit(SMAXV_r_p_z | SVESize(zn) | Rd(vd) | PgLow8(pg) | Rn(zn));
3318 const ZRegister& zn) {
3322 Emit(SMINV_r_p_z | SVESize(zn) | Rd(vd) | PgLow8(pg) | Rn(zn));
3327 const ZRegister& zn) {
3330 Emit(UADDV_r_p_z | SVESize(zn) | Rd(dd) | PgLow8(pg) | Rn(zn));
3335 const ZRegister& zn) {
3339 Emit(UMAXV_r_p_z | SVESize(zn) | Rd(vd) | PgLow8(pg) | Rn(zn));
3344 const ZRegister& zn) {
3348 Emit(UMINV_r_p_z | SVESize(zn) | Rd(vd) | PgLow8(pg) | Rn(zn));
3355 const ZRegister& zn) {
3361 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3363 Emit(ABS_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
3368 const ZRegister& zn) {
3374 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3376 Emit(CLS_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
3381 const ZRegister& zn) {
3387 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3389 Emit(CLZ_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
3394 const ZRegister& zn) {
3400 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3402 Emit(CNOT_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
3407 const ZRegister& zn) {
3413 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3415 Emit(CNT_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
3420 const ZRegister& zn) {
3426 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3429 Emit(FABS_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
3434 const ZRegister& zn) {
3440 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3443 Emit(FNEG_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
3448 const ZRegister& zn) {
3454 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3456 Emit(NEG_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
3461 const ZRegister& zn) {
3467 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3469 Emit(NOT_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
3474 const ZRegister& zn) {
3480 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3483 Emit(SXTB_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
3488 const ZRegister& zn) {
3494 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3497 Emit(SXTH_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
3502 const ZRegister& zn) {
3508 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3511 Emit(SXTW_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
3516 const ZRegister& zn) {
3522 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3525 Emit(UXTB_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
3530 const ZRegister& zn) {
3536 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3539 Emit(UXTH_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
3544 const ZRegister& zn) {
3550 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3553 Emit(UXTW_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
3615 const ZRegister& zn,
3622 USE(zn);
3624 VIXL_ASSERT(zd.Is(zn));
3625 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3656 void Assembler::mul(const ZRegister& zd, const ZRegister& zn, int imm8) {
3661 USE(zn);
3663 VIXL_ASSERT(zd.Is(zn));
3664 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3669 void Assembler::smax(const ZRegister& zd, const ZRegister& zn, int imm8) {
3674 USE(zn);
3676 VIXL_ASSERT(zd.Is(zn));
3677 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3682 void Assembler::smin(const ZRegister& zd, const ZRegister& zn, int imm8) {
3687 USE(zn);
3689 VIXL_ASSERT(zd.Is(zn));
3690 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3696 const ZRegister& zn,
3703 USE(zn);
3705 VIXL_ASSERT(zd.Is(zn));
3706 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3712 const ZRegister& zn,
3719 USE(zn);
3721 VIXL_ASSERT(zd.Is(zn));
3722 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3728 const ZRegister& zn,
3735 USE(zn);
3737 VIXL_ASSERT(zd.Is(zn));
3738 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3744 const ZRegister& zn,
3751 USE(zn);
3753 VIXL_ASSERT(zd.Is(zn));
3754 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3759 void Assembler::umax(const ZRegister& zd, const ZRegister& zn, int imm8) {
3764 USE(zn);
3766 VIXL_ASSERT(zd.Is(zn));
3767 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3772 void Assembler::umin(const ZRegister& zd, const ZRegister& zn, int imm8) {
3777 USE(zn);
3779 VIXL_ASSERT(zd.Is(zn));
3780 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3786 const ZRegister& zn,
3793 USE(zn);
3795 VIXL_ASSERT(zd.Is(zn));
3796 VIXL_ASSERT(AreSameLaneSize(zd, zn));
3802 const ZRegister& zn,
3809 USE(zn);
3811 VIXL_ASSERT(zd.Is(zn));
3812 VIXL_ASSERT(AreSameLaneSize(zd, zn));
4270 const ZRegister& zn,
4279 Emit(LDFF1B_z_p_ai_d | Rt(zt) | PgLow8(pg) | Rn(zn) | ImmField<20, 16>(imm5));
4303 const ZRegister& zn,
4312 Emit(LDFF1D_z_p_ai_d | Rt(zt) | PgLow8(pg) | Rn(zn) | ImmField<20, 16>(imm5));
4339 const ZRegister& zn,
4348 Emit(LDFF1H_z_p_ai_d | Rt(zt) | PgLow8(pg) | Rn(zn) | ImmField<20, 16>(imm5));
4373 const ZRegister& zn,
4382 Emit(LDFF1SB_z_p_ai_d | Rt(zt) | PgLow8(pg) | Rn(zn) |
4410 const ZRegister& zn,
4419 Emit(LDFF1SH_z_p_ai_d | Rt(zt) | PgLow8(pg) | Rn(zn) |
4444 const ZRegister& zn,
4453 Emit(LDFF1SW_z_p_ai_d | Rt(zt) | PgLow8(pg) | Rn(zn) |
4481 const ZRegister& zn,
4490 Emit(LDFF1W_z_p_ai_d | Rt(zt) | PgLow8(pg) | Rn(zn) | ImmField<20, 16>(imm5));
4499 ZRegister zn = addr.GetVectorBase();
4500 VIXL_ASSERT(zn.IsLaneSizeS() || zn.IsLaneSizeD());
4505 op = zn.IsLaneSizeS() ? static_cast<Instr>(PRFB_i_p_ai_s)
4509 op = zn.IsLaneSizeS() ? static_cast<Instr>(PRFH_i_p_ai_s)
4513 op = zn.IsLaneSizeS() ? static_cast<Instr>(PRFW_i_p_ai_s)
4517 op = zn.IsLaneSizeS() ? static_cast<Instr>(PRFD_i_p_ai_s)
4526 Emit(op | SVEImmPrefetchOperation(prfop) | PgLow8(pg) | Rn(zn) |
4773 ZRegister zn = addr.GetVectorBase();
4774 VIXL_ASSERT(zn.IsLaneSizeS() || zn.IsLaneSizeD());
4775 VIXL_ASSERT(AreSameLaneSize(zn, zt));
4777 uint32_t esize = zn.GetLaneSizeInBytesLog2();
4779 if (!is_signed) b14_13 = zn.IsLaneSizeS() ? 0x1 : 0x2;
4793 ZRegister zn = addr.GetVectorBase();
4794 VIXL_ASSERT(zn.IsLaneSizeS() || zn.IsLaneSizeD());
4795 VIXL_ASSERT(AreSameLaneSize(zn, zt));
4797 uint32_t bit22 = zn.IsLaneSizeS() ? (1 << 22) : 0;
5070 ZRegister zn = addr.GetVectorBase();
5073 VIXL_ASSERT(zn.IsLaneSizeS() || zn.IsLaneSizeD());
5075 op = Rn(zn) | ImmUnsignedField<20, 16>(imm >> msize_in_bytes_log2);
5079 ZRegister zn = addr.GetVectorBase();
5080 VIXL_ASSERT(zn.IsLaneSizeS() || zn.IsLaneSizeD());
5082 op = Rn(zn) | Rm(xm);
5326 const ZRegister& zn,
5330 VIXL_ASSERT(zda.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 4));
5331 VIXL_ASSERT(AreSameLaneSize(zn, zm));
5337 op = SDOT_z_zzzi_s | Rx<18, 16>(zm) | (index << 19) | Rd(zda) | Rn(zn);
5341 op = SDOT_z_zzzi_d | Rx<19, 16>(zm) | (index << 20) | Rd(zda) | Rn(zn);
5352 const ZRegister& zn,
5356 VIXL_ASSERT(zda.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 4));
5357 VIXL_ASSERT(AreSameLaneSize(zn, zm));
5363 op = UDOT_z_zzzi_s | Rx<18, 16>(zm) | (index << 19) | Rd(zda) | Rn(zn);
5367 op = UDOT_z_zzzi_d | Rx<19, 16>(zm) | (index << 20) | Rd(zda) | Rn(zn);
5564 const ZRegister& zn,
5582 if (zd.Is(zn)) {
5587 VIXL_ASSERT(CPUHas(CPUFeatures::kSVE2) && AreConsecutive(zn, zm));
5588 op = 0x05600000 | Rn(zn);
5598 const ZRegister& zn,
5605 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
5607 Emit(TRN1_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
5611 const ZRegister& zn,
5618 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
5620 Emit(TRN2_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
5624 const ZRegister& zn,
5631 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
5633 Emit(UZP1_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
5637 const ZRegister& zn,
5644 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
5646 Emit(UZP2_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
5650 const ZRegister& zn,
5657 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
5659 Emit(ZIP1_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
5663 const ZRegister& zn,
5670 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
5672 Emit(ZIP2_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
5711 const ZRegister& zn,
5717 USE(zn);
5719 VIXL_ASSERT(zd.Is(zn));
5720 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
5759 const ZRegister& zn,
5765 USE(zn);
5767 VIXL_ASSERT(zd.Is(zn));
5768 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
5775 const ZRegister& zn) {
5781 VIXL_ASSERT(AreSameLaneSize(zd, zn));
5786 Emit(COMPACT_z_p_z | sz | Rd(zd) | PgLow8(pg) | Rn(zn));
5820 const ZRegister& zn) {
5827 Emit(LASTA_r_p_z | SVESize(zn) | Rd(rd) | PgLow8(pg) | Rn(zn));
5832 const ZRegister& zn) {
5840 Emit(LASTA_v_p_z | SVESize(zn) | Rd(vd) | PgLow8(pg) | Rn(zn));
5845 const ZRegister& zn) {
5852 Emit(LASTB_r_p_z | SVESize(zn) | Rd(rd) | PgLow8(pg) | Rn(zn));
5857 const ZRegister& zn) {
5865 Emit(LASTB_v_p_z | SVESize(zn) | Rd(vd) | PgLow8(pg) | Rn(zn));
5870 const ZRegister& zn) {
5876 VIXL_ASSERT(AreSameLaneSize(zd, zn));
5878 Emit(RBIT_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
5883 const ZRegister& zn) {
5889 VIXL_ASSERT(AreSameLaneSize(zd, zn));
5892 Emit(REVB_z_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
5897 const ZRegister& zn) {
5903 VIXL_ASSERT(AreSameLaneSize(zd, zn));
5906 Emit(REVH_z_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
5911 const ZRegister& zn) {
5917 VIXL_ASSERT(AreSameLaneSize(zd, zn));
5920 Emit(REVW_z_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
5925 const ZRegister& zn,
5927 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
5929 if (zd.Aliases(zn)) {
5934 USE(zn);
5936 VIXL_ASSERT(zd.Is(zn));
5940 splice_con(zd, pg, zn, zm);
5972 void Assembler::dup(const ZRegister& zd, const ZRegister& zn, unsigned index) {
5978 VIXL_ASSERT(AreSameFormat(zd, zn));
5987 ImmUnsignedField<20, 16>(tsz_5) | Rd(zd) | Rn(zn));
6011 void Assembler::rev(const ZRegister& zd, const ZRegister& zn) {
6017 VIXL_ASSERT(AreSameFormat(zd, zn));
6019 Emit(REV_z_z | SVESize(zd) | Rd(zd) | Rn(zn));
6022 void Assembler::sunpkhi(const ZRegister& zd, const ZRegister& zn) {
6028 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
6031 Emit(SUNPKHI_z_z | SVESize(zd) | Rd(zd) | Rn(zn));
6034 void Assembler::sunpklo(const ZRegister& zd, const ZRegister& zn) {
6040 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
6043 Emit(SUNPKLO_z_z | SVESize(zd) | Rd(zd) | Rn(zn));
6047 const ZRegister& zn,
6054 VIXL_ASSERT(AreSameFormat(zd, zn, zm));
6056 Emit(TBL_z_zz_1 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
6059 void Assembler::uunpkhi(const ZRegister& zd, const ZRegister& zn) {
6065 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
6068 Emit(UUNPKHI_z_z | SVESize(zd) | Rd(zd) | Rn(zn));
6071 void Assembler::uunpklo(const ZRegister& zd, const ZRegister& zn) {
6077 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
6080 Emit(UUNPKLO_z_z | SVESize(zd) | Rd(zd) | Rn(zn));
6453 const ZRegister& zn,
6456 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
6458 Emit(SEL_z_p_zz | SVESize(zd) | Rd(zd) | Pg<13, 10>(pg) | Rn(zn) | Rm(zm));
6485 void Assembler::bic(const ZRegister& zd, const ZRegister& zn, uint64_t imm) {
6486 and_(zd, zn, ~imm);
6489 void Assembler::eon(const ZRegister& zd, const ZRegister& zn, uint64_t imm) {
6490 eor(zd, zn, ~imm);
6493 void Assembler::orn(const ZRegister& zd, const ZRegister& zn, uint64_t imm) {
6494 orr(zd, zn, ~imm);
6551 void Assembler::mov(const ZRegister& zd, const ZRegister& zn) {
6552 VIXL_ASSERT(AreSameLaneSize(zd, zn));
6553 orr(zd.VnD(), zn.VnD(), zn.VnD());
6556 void Assembler::mov(const ZRegister& zd, const ZRegister& zn, unsigned index) {
6557 VIXL_ASSERT(AreSameLaneSize(zd, zn));
6558 dup(zd, zn, index);
6577 const ZRegister& zn) {
6578 VIXL_ASSERT(AreSameLaneSize(zd, zn));
6579 sel(zd, pg, zn, zd);
6622 const ZRegister& zn,
6629 VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
6633 Emit(0x4500d000 | sz | Rd(zda) | Rn(zn) | Rm(zm));
6637 const ZRegister& zn,
6644 VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
6648 Emit(0x4500d400 | sz | Rd(zda) | Rn(zn) | Rm(zm));
6652 const ZRegister& zn,
6659 VIXL_ASSERT(AreSameLaneSize(zn, zm));
6660 VIXL_ASSERT(zn.GetLaneSizeInBytes() == (zd.GetLaneSizeInBytes() * 2));
6661 VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
6663 Emit(0x45206000 | SVESize(zn) | Rd(zd) | Rn(zn) | Rm(zm));
6667 const ZRegister& zn,
6674 VIXL_ASSERT(AreSameLaneSize(zn, zm));
6675 VIXL_ASSERT(zn.GetLaneSizeInBytes() == (zd.GetLaneSizeInBytes() * 2));
6676 VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
6678 Emit(0x45206400 | SVESize(zn) | Rd(zd) | Rn(zn) | Rm(zm));
6683 const ZRegister& zn,
6689 USE(zn);
6691 VIXL_ASSERT(zd.Is(zn));
6692 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
6698 const ZRegister& zn,
6705 USE(zn);
6707 VIXL_ASSERT(zd.Is(zn));
6708 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm, zk));
6715 const ZRegister& zn,
6723 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
6725 Emit(0x4500b400 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
6729 const ZRegister& zn,
6737 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
6739 Emit(0x4500b000 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
6743 const ZRegister& zn,
6751 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
6753 Emit(0x4500b800 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
6757 const ZRegister& zn,
6764 USE(zn);
6766 VIXL_ASSERT(zd.Is(zn));
6767 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm, zk));
6774 const ZRegister& zn,
6781 USE(zn);
6783 VIXL_ASSERT(zd.Is(zn));
6784 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm, zk));
6791 const ZRegister& zn,
6798 USE(zn);
6800 VIXL_ASSERT(zd.Is(zn));
6801 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm, zk));
6808 const ZRegister& zn,
6815 USE(zn);
6817 VIXL_ASSERT(zd.Is(zn));
6818 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
6826 const ZRegister& zn,
6836 VIXL_ASSERT(AreSameLaneSize(zn, zm));
6838 VIXL_ASSERT(zda.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 4));
6854 Emit(0x44a04000 | zm_and_idx | rotate_bits | SVESize(zda) | Rd(zda) | Rn(zn));
6858 const ZRegister& zn,
6867 VIXL_ASSERT(AreSameLaneSize(zn, zm));
6869 VIXL_ASSERT(zda.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 4));
6872 Emit(0x44001000 | rotate_bits | SVESize(zda) | Rd(zda) | Rn(zn) | Rm(zm));
6876 const ZRegister& zn,
6885 VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
6890 Rn(zn));
6894 const ZRegister& zn,
6902 VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
6906 Emit(0x44002000 | rotate_bit | SVESize(zda) | Rd(zda) | Rn(zn) | Rm(zm));
6910 const ZRegister& zn,
6917 USE(zn);
6919 VIXL_ASSERT(zd.Is(zn));
6920 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm, zk));
6927 const ZRegister& zn,
6934 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
6936 Emit(0x45009000 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
6940 const ZRegister& zn,
6947 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
6949 Emit(0x45009400 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
6954 const ZRegister& zn,
6960 USE(zn);
6962 VIXL_ASSERT(zd.Is(zn));
6963 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
6971 const ZRegister& zn) {
6979 if (zd.IsLaneSizeD() && zn.IsLaneSizeS()) {
6982 VIXL_ASSERT(zd.IsLaneSizeS() && zn.IsLaneSizeH());
6986 Emit(op | Rd(zd) | PgLow8(pg) | Rn(zn));
6991 const ZRegister& zn) {
6999 if (zd.IsLaneSizeS() && zn.IsLaneSizeD()) {
7002 VIXL_ASSERT(zd.IsLaneSizeH() && zn.IsLaneSizeS());
7005 Emit(op | Rd(zd) | PgLow8(pg) | Rn(zn));
7010 const ZRegister& zn) {
7016 VIXL_ASSERT(zd.IsLaneSizeS() && zn.IsLaneSizeD());
7018 Emit(0x650aa000 | Rd(zd) | PgLow8(pg) | Rn(zn));
7023 const ZRegister& zn) {
7030 Emit(0x640aa000 | Rd(zd) | PgLow8(pg) | Rn(zn));
7035 const ZRegister& zn) {
7041 VIXL_ASSERT(AreSameLaneSize(zd, zn));
7046 Emit(0x6518a000 | size | Rd(zd) | PgLow8(pg) | Rn(zn));
7051 const ZRegister& zn,
7057 USE(zn);
7059 VIXL_ASSERT(zd.Is(zn));
7060 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
7068 const ZRegister& zn,
7074 USE(zn);
7076 VIXL_ASSERT(zd.Is(zn));
7077 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
7085 const ZRegister& zn,
7091 USE(zn);
7093 VIXL_ASSERT(zd.Is(zn));
7094 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
7102 const ZRegister& zn,
7108 USE(zn);
7110 VIXL_ASSERT(zd.Is(zn));
7111 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
7118 const ZRegister& zn,
7126 VIXL_ASSERT(zn.IsLaneSizeH() && zm.IsLaneSizeH());
7128 Emit(0x64a08000 | Rd(zda) | Rn(zn) | Rm(zm));
7132 const ZRegister& zn,
7137 VIXL_ASSERT(zn.IsLaneSizeH() && zm.IsLaneSizeH());
7142 Emit(0x64a04000 | Rd(zda) | Rn(zn) | zm_and_idx);
7146 const ZRegister& zn,
7154 VIXL_ASSERT(zn.IsLaneSizeH() && zm.IsLaneSizeH());
7156 Emit(0x64a08400 | Rd(zda) | Rn(zn) | Rm(zm));
7160 const ZRegister& zn,
7169 VIXL_ASSERT(zn.IsLaneSizeH() && zm.IsLaneSizeH());
7174 Emit(0x64a04400 | Rd(zda) | Rn(zn) | zm_and_idx);
7178 const ZRegister& zn,
7186 VIXL_ASSERT(zn.IsLaneSizeH() && zm.IsLaneSizeH());
7188 Emit(0x64a0a000 | Rd(zda) | Rn(zn) | Rm(zm));
7192 const ZRegister& zn,
7201 VIXL_ASSERT(zn.IsLaneSizeH() && zm.IsLaneSizeH());
7206 Emit(0x64a06000 | Rd(zda) | Rn(zn) | zm_and_idx);
7210 const ZRegister& zn,
7218 VIXL_ASSERT(zn.IsLaneSizeH() && zm.IsLaneSizeH());
7220 Emit(0x64a0a400 | Rd(zda) | Rn(zn) | Rm(zm));
7224 const ZRegister& zn,
7233 VIXL_ASSERT(zn.IsLaneSizeH() && zm.IsLaneSizeH());
7238 Emit(0x64a06400 | Rd(zda) | Rn(zn) | zm_and_idx);
7243 const ZRegister& zn,
7250 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
7253 Emit(0x4520c000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn) | Rm(zm));
7257 const ZRegister& zn,
7264 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
7267 Emit(0x4520a000 | Rd(zd) | Rn(zn) | Rm(zm));
7272 const ZRegister& zn,
7279 VIXL_ASSERT(AreSameLaneSize(pd, zn, zm));
7282 Emit(0x45208000 | SVESize(zm) | Pd(pd) | PgLow8(pg) | Rn(zn) | Rm(zm));
7286 const ZRegister& zn,
7294 VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
7303 Emit(synthesised_op | Rd(zda) | Rn(zn));
7307 const ZRegister& zn,
7315 VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
7324 Emit(synthesised_op | Rd(zda) | Rn(zn));
7328 const ZRegister& zn,
7336 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
7345 Emit(synthesised_op | Rd(zd) | Rn(zn));
7349 const ZRegister& zn,
7356 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
7358 Emit(0x04206000 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
7362 const ZRegister& zn,
7369 USE(zn);
7371 VIXL_ASSERT(zd.Is(zn));
7372 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm, zk));
7380 const ZRegister& zn,
7387 VIXL_ASSERT(AreSameLaneSize(pd, zn, zm));
7390 Emit(0x45208010 | SVESize(zm) | Pd(pd) | PgLow8(pg) | Rn(zn) | Rm(zm));
7394 const ZRegister& zn,
7402 Emit(0x04206400 | Rd(zd) | Rn(zn) | Rm(zm));
7406 const ZRegister& zn,
7413 VIXL_ASSERT(AreSameLaneSize(zn, zm));
7415 VIXL_ASSERT(zd.GetLaneSizeInBytes() == zn.GetLaneSizeInBytes() * 2);
7419 Emit(0x45006800 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
7423 const ZRegister& zn,
7430 VIXL_ASSERT(AreSameLaneSize(zn, zm));
7432 VIXL_ASSERT(zd.GetLaneSizeInBytes() == zn.GetLaneSizeInBytes() * 2);
7436 Emit(0x45006c00 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
7440 const ZRegister& zn,
7447 VIXL_ASSERT(AreSameLaneSize(zn, zm));
7448 VIXL_ASSERT(zn.GetLaneSizeInBytes() == (zd.GetLaneSizeInBytes() * 2));
7449 VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
7451 Emit(0x45206800 | SVESize(zn) | Rd(zd) | Rn(zn) | Rm(zm));
7455 const ZRegister& zn,
7462 VIXL_ASSERT(AreSameLaneSize(zn, zm));
7463 VIXL_ASSERT(zn.GetLaneSizeInBytes() == (zd.GetLaneSizeInBytes() * 2));
7464 VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
7466 Emit(0x45206c00 | SVESize(zn) | Rd(zd) | Rn(zn) | Rm(zm));
7488 void Assembler::MNE(const ZRegister& zd, const ZRegister& zn, int shift) { \
7491 VIXL_ASSERT(zn.GetLaneSizeInBytes() == (zd.GetLaneSizeInBytes() * 2)); \
7494 SVEBitwiseShiftImmediate(zd, zn, encoded_imm, X); \
7500 const ZRegister& zn,
7507 VIXL_ASSERT(AreSameLaneSize(zn, zm));
7508 VIXL_ASSERT(zn.GetLaneSizeInBytes() == (zd.GetLaneSizeInBytes() * 2));
7509 VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
7511 Emit(0x45207800 | SVESize(zn) | Rd(zd) | Rn(zn) | Rm(zm));
7515 const ZRegister& zn,
7522 VIXL_ASSERT(AreSameLaneSize(zn, zm));
7523 VIXL_ASSERT(zn.GetLaneSizeInBytes() == (zd.GetLaneSizeInBytes() * 2));
7524 VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
7526 Emit(0x45207c00 | SVESize(zn) | Rd(zd) | Rn(zn) | Rm(zm));
7530 const ZRegister& zn,
7537 VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
7539 Emit(0x4500f800 | SVESize(zda) | Rd(zda) | Rn(zn) | Rm(zm));
7543 const ZRegister& zn,
7550 VIXL_ASSERT(AreSameLaneSize(zn, zm));
7551 VIXL_ASSERT(zda.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
7554 Emit(0x4500c000 | SVESize(zda) | Rd(zda) | Rn(zn) | Rm(zm));
7558 const ZRegister& zn,
7565 VIXL_ASSERT(AreSameLaneSize(zn, zm));
7566 VIXL_ASSERT(zda.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
7569 Emit(0x4500c400 | SVESize(zda) | Rd(zda) | Rn(zn) | Rm(zm));
7573 const ZRegister& zn,
7581 VIXL_ASSERT(AreSameLaneSize(zn, zm));
7582 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
7585 Emit(0x45003000 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
7589 const ZRegister& zn,
7597 VIXL_ASSERT(AreSameLaneSize(zn, zm));
7598 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
7601 Emit(0x45003400 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
7606 const ZRegister& zn) {
7612 VIXL_ASSERT(zda.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
7615 Emit(0x4404a000 | SVESize(zda) | Rd(zda) | PgLow8(pg) | Rn(zn));
7619 const ZRegister& zn,
7627 VIXL_ASSERT(AreSameLaneSize(zn, zm));
7628 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
7631 Emit(0x45000000 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
7635 const ZRegister& zn,
7642 VIXL_ASSERT(AreSameLaneSize(zn, zm));
7643 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
7646 Emit(0x45008000 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
7650 const ZRegister& zn,
7658 VIXL_ASSERT(AreSameLaneSize(zn, zm));
7659 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
7662 Emit(0x45000400 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
7666 const ZRegister& zn,
7673 VIXL_ASSERT(AreSameLaneSize(zd, zn));
7677 Emit(0x45004000 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
7681 const ZRegister& zn,
7688 VIXL_ASSERT(AreSameLaneSize(zd, zn));
7692 Emit(0x45004400 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
7696 const ZRegister& zn,
7703 VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
7707 Emit(0x4580d000 | sz | Rd(zda) | Rn(zn) | Rm(zm));
7711 const ZRegister& zn,
7718 VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
7722 Emit(0x4580d400 | sz | Rd(zda) | Rn(zn) | Rm(zm));
7727 const ZRegister& zn,
7733 USE(zn);
7735 VIXL_ASSERT(zd.Is(zn));
7736 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
7743 const ZRegister& zn,
7749 USE(zn);
7751 VIXL_ASSERT(zd.Is(zn));
7752 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
7759 const ZRegister& zn,
7765 USE(zn);
7767 VIXL_ASSERT(zd.Is(zn));
7768 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
7773 void Assembler::sli(const ZRegister& zd, const ZRegister& zn, int shift) {
7779 VIXL_ASSERT(AreSameLaneSize(zd, zn));
7783 SVEBitwiseShiftImmediate(zd, zn, encoded_imm, 0x4500f400);
7788 const ZRegister& zn,
7794 USE(zn);
7796 VIXL_ASSERT(zd.Is(zn));
7797 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
7804 const ZRegister& zn,
7810 USE(zn);
7812 VIXL_ASSERT(zd.Is(zn));
7813 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
7836 const ZRegister& zn, \
7840 VIXL_ASSERT(AreSameLaneSize(zn, zm)); \
7842 VIXL_ASSERT(zda.GetLaneSizeInBytes() == zn.GetLaneSizeInBytes() * 2); \
7844 Emit(OP | SVESize(zda) | Rd(zda) | Rn(zn) | zm_with_index); \
7850 const ZRegister& zn,
7858 VIXL_ASSERT(AreSameLaneSize(zn, zm));
7859 VIXL_ASSERT(zda.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
7861 Emit(0x44004000 | SVESize(zda) | Rd(zda) | Rn(zn) | Rm(zm));
7865 const ZRegister& zn,
7873 VIXL_ASSERT(AreSameLaneSize(zn, zm));
7874 VIXL_ASSERT(zda.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
7876 Emit(0x44004400 | SVESize(zda) | Rd(zda) | Rn(zn) | Rm(zm));
7880 const ZRegister& zn,
7888 VIXL_ASSERT(AreSameLaneSize(zn, zm));
7889 VIXL_ASSERT(zda.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
7891 Emit(0x44005000 | SVESize(zda) | Rd(zda) | Rn(zn) | Rm(zm));
7895 const ZRegister& zn,
7903 VIXL_ASSERT(AreSameLaneSize(zn, zm));
7904 VIXL_ASSERT(zda.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
7906 Emit(0x44005400 | SVESize(zda) | Rd(zda) | Rn(zn) | Rm(zm));
7910 const ZRegister& zn,
7917 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
7919 Emit(0x04206800 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
7923 const ZRegister& zn,
7930 VIXL_ASSERT(AreSameLaneSize(zn, zm));
7932 VIXL_ASSERT(zd.GetLaneSizeInBytes() == zn.GetLaneSizeInBytes() * 2);
7934 Emit(0x45007000 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
7938 const ZRegister& zn,
7945 VIXL_ASSERT(AreSameLaneSize(zn, zm));
7947 VIXL_ASSERT(zd.GetLaneSizeInBytes() == zn.GetLaneSizeInBytes() * 2);
7949 Emit(0x45007400 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
7954 const ZRegister& zn) {
7960 VIXL_ASSERT(AreSameLaneSize(zd, zn));
7962 Emit(0x4408a000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
7967 const ZRegister& zn,
7973 USE(zn);
7975 VIXL_ASSERT(zd.Is(zn));
7976 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
7982 const ZRegister& zn,
7989 USE(zn);
7991 VIXL_ASSERT(zd.Is(zn));
7992 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
8003 const ZRegister& zn,
8011 VIXL_ASSERT(AreSameLaneSize(zn, zm));
8029 Emit(0x44202000 | zm_and_idx | SVESize(zda) | Rd(zda) | Rn(zn));
8033 const ZRegister& zn,
8040 VIXL_ASSERT(AreSameLaneSize(zn, zm));
8041 VIXL_ASSERT(zda.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
8044 Emit(0x44006000 | SVESize(zda) | Rd(zda) | Rn(zn) | Rm(zm));
8048 const ZRegister& zn,
8055 VIXL_ASSERT(AreSameLaneSize(zn, zm));
8056 VIXL_ASSERT(zda.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
8059 Emit(0x44000800 | SVESize(zda) | Rd(zda) | Rn(zn) | Rm(zm));
8066 const ZRegister& zn,
8074 VIXL_ASSERT(AreSameLaneSize(zn, zm));
8092 Emit(0x44202400 | zm_and_idx | SVESize(zda) | Rd(zda) | Rn(zn));
8096 const ZRegister& zn,
8103 VIXL_ASSERT(AreSameLaneSize(zn, zm));
8104 VIXL_ASSERT(zda.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
8107 Emit(0x44006400 | SVESize(zda) | Rd(zda) | Rn(zn) | Rm(zm));
8114 const ZRegister& zn,
8122 VIXL_ASSERT(AreSameLaneSize(zn, zm));
8140 Emit(0x44203000 | zm_and_idx | SVESize(zda) | Rd(zda) | Rn(zn));
8144 const ZRegister& zn,
8151 VIXL_ASSERT(AreSameLaneSize(zn, zm));
8152 VIXL_ASSERT(zda.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
8155 Emit(0x44006800 | SVESize(zda) | Rd(zda) | Rn(zn) | Rm(zm));
8159 const ZRegister& zn,
8166 VIXL_ASSERT(AreSameLaneSize(zn, zm));
8167 VIXL_ASSERT(zda.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
8170 Emit(0x44000c00 | SVESize(zda) | Rd(zda) | Rn(zn) | Rm(zm));
8177 const ZRegister& zn,
8185 VIXL_ASSERT(AreSameLaneSize(zn, zm));
8203 Emit(0x44203400 | zm_and_idx | SVESize(zda) | Rd(zda) | Rn(zn));
8207 const ZRegister& zn,
8214 VIXL_ASSERT(AreSameLaneSize(zn, zm));
8215 VIXL_ASSERT(zda.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
8218 Emit(0x44006c00 | SVESize(zda) | Rd(zda) | Rn(zn) | Rm(zm));
8222 const ZRegister& zn,
8230 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
8239 Emit(synthesised_op | Rd(zd) | Rn(zn));
8243 const ZRegister& zn,
8250 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
8252 Emit(0x04207000 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
8256 const ZRegister& zn,
8263 VIXL_ASSERT(AreSameLaneSize(zn, zm));
8265 VIXL_ASSERT(zd.GetLaneSizeInBytes() == zn.GetLaneSizeInBytes() * 2);
8267 Emit(0x45006000 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
8271 const ZRegister& zn,
8278 VIXL_ASSERT(AreSameLaneSize(zn, zm));
8280 VIXL_ASSERT(zd.GetLaneSizeInBytes() == zn.GetLaneSizeInBytes() * 2);
8282 Emit(0x45006400 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
8287 const ZRegister& zn) {
8293 VIXL_ASSERT(AreSameLaneSize(zd, zn));
8295 Emit(0x4409a000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
8299 const ZRegister& zn,
8308 VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
8313 Rn(zn));
8317 const ZRegister& zn,
8325 VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
8329 Emit(0x44003000 | rotate_bit | SVESize(zda) | Rd(zda) | Rn(zn) | Rm(zm));
8337 const ZRegister& zn,
8341 VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
8355 Emit(synthesized_op | Rd(zda) | Rn(zn));
8359 const ZRegister& zn,
8366 VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
8368 Emit(0x44007000 | SVESize(zda) | Rd(zda) | Rn(zn) | Rm(zm));
8376 const ZRegister& zn,
8380 VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
8394 Emit(synthesized_op | Rd(zda) | Rn(zn));
8398 const ZRegister& zn,
8405 VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
8407 Emit(0x44007400 | SVESize(zda) | Rd(zda) | Rn(zn) | Rm(zm));
8411 const ZRegister& zn,
8419 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
8428 Emit(synthesised_op | Rd(zd) | Rn(zn));
8432 const ZRegister& zn,
8439 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
8441 Emit(0x04207400 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
8446 const ZRegister& zn,
8453 USE(zn);
8455 VIXL_ASSERT(zd.Is(zn));
8456 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
8463 const ZRegister& zn,
8470 USE(zn);
8472 VIXL_ASSERT(zd.Is(zn));
8473 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
8480 const ZRegister& zn,
8487 USE(zn);
8489 VIXL_ASSERT(zd.Is(zn));
8497 const ZRegister& zn,
8504 USE(zn);
8506 VIXL_ASSERT(zd.Is(zn));
8507 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
8514 const ZRegister& zn,
8521 USE(zn);
8523 VIXL_ASSERT(zd.Is(zn));
8524 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
8531 const ZRegister& zn,
8538 USE(zn);
8540 VIXL_ASSERT(zd.Is(zn));
8549 const ZRegister& zn,
8555 USE(zn);
8557 VIXL_ASSERT(zd.Is(zn));
8558 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
8565 const ZRegister& zn,
8571 USE(zn);
8573 VIXL_ASSERT(zd.Is(zn));
8574 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
8579 void Assembler::sqxtnb(const ZRegister& zd, const ZRegister& zn) {
8586 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() / 2));
8590 SVEBitwiseShiftImmediate(zd, zn, size, 0x45204000);
8593 void Assembler::sqxtnt(const ZRegister& zd, const ZRegister& zn) {
8600 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() / 2));
8604 SVEBitwiseShiftImmediate(zd, zn, size, 0x45204400);
8607 void Assembler::sqxtunb(const ZRegister& zd, const ZRegister& zn) {
8614 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() / 2));
8618 SVEBitwiseShiftImmediate(zd, zn, size, 0x45205000);
8621 void Assembler::sqxtunt(const ZRegister& zd, const ZRegister& zn) {
8628 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() / 2));
8632 SVEBitwiseShiftImmediate(zd, zn, size, 0x45205400);
8637 const ZRegister& zn,
8643 USE(zn);
8645 VIXL_ASSERT(zd.Is(zn));
8646 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
8651 void Assembler::sri(const ZRegister& zd, const ZRegister& zn, int shift) {
8657 VIXL_ASSERT(AreSameLaneSize(zd, zn));
8661 SVEBitwiseShiftImmediate(zd, zn, encoded_imm, 0x4500f000);
8666 const ZRegister& zn,
8673 USE(zn);
8675 VIXL_ASSERT(zd.Is(zn));
8676 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
8683 const ZRegister& zn,
8690 USE(zn);
8692 VIXL_ASSERT(zd.Is(zn));
8693 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
8700 const ZRegister& zn,
8707 USE(zn);
8709 VIXL_ASSERT(zd.Is(zn));
8715 void Assembler::srsra(const ZRegister& zda, const ZRegister& zn, int shift) {
8722 VIXL_ASSERT(AreSameLaneSize(zda, zn));
8726 SVEBitwiseShiftImmediate(zda, zn, encoded_imm, 0x4500e800);
8729 void Assembler::sshllb(const ZRegister& zd, const ZRegister& zn, int shift) {
8736 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
8739 EncodeSVEShiftLeftImmediate(shift, zn.GetLaneSizeInBits());
8740 SVEBitwiseShiftImmediate(zd, zn, encoded_imm, 0x4500a000);
8743 void Assembler::sshllt(const ZRegister& zd, const ZRegister& zn, int shift) {
8750 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
8753 EncodeSVEShiftLeftImmediate(shift, zn.GetLaneSizeInBits());
8754 SVEBitwiseShiftImmediate(zd, zn, encoded_imm, 0x4500a400);
8757 void Assembler::ssra(const ZRegister& zda, const ZRegister& zn, int shift) {
8764 VIXL_ASSERT(AreSameLaneSize(zda, zn));
8768 SVEBitwiseShiftImmediate(zda, zn, encoded_imm, 0x4500e000);
8772 const ZRegister& zn,
8780 VIXL_ASSERT(AreSameLaneSize(zn, zm));
8781 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
8784 Emit(0x45001000 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
8788 const ZRegister& zn,
8795 VIXL_ASSERT(AreSameLaneSize(zn, zm));
8796 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
8799 Emit(0x45008800 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
8803 const ZRegister& zn,
8811 VIXL_ASSERT(AreSameLaneSize(zn, zm));
8812 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
8815 Emit(0x45001400 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
8819 const ZRegister& zn,
8826 VIXL_ASSERT(AreSameLaneSize(zn, zm));
8827 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
8830 Emit(0x45008c00 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
8834 const ZRegister& zn,
8841 VIXL_ASSERT(AreSameLaneSize(zd, zn));
8845 Emit(0x45005000 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
8849 const ZRegister& zn,
8856 VIXL_ASSERT(AreSameLaneSize(zd, zn));
8860 Emit(0x45005400 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
8867 void Assembler::stnt1b(const ZRegister& zt, const PRegister& pg, const ZRegister& zn, const Register& rm) {
8874 Emit(0xe4002000 | Rt(zt) | PgLow8(pg) | Rn(zn) | Rm(rm));
8877 void Assembler::stnt1d(const ZRegister& zt, const PRegister& pg, const ZRegister& zn, const Register& rm) {
8884 Emit(0xe5802000 | Rt(zt) | PgLow8(pg) | Rn(zn) | Rm(rm));
8890 void Assembler::stnt1h(const ZRegister& zt, const PRegister& pg, const ZRegister& zn, const Register& rm) {
8897 Emit(0xe4802000 | Rt(zt) | PgLow8(pg) | Rn(zn) | Rm(rm));
8903 void Assembler::stnt1w(const ZRegister& zt, const PRegister& pg, const ZRegister& zn, const Register& rm) {
8910 Emit(0xe5002000 | Rt(zt) | PgLow8(pg) | Rn(zn) | Rm(rm));
8915 const ZRegister& zn,
8922 VIXL_ASSERT(AreSameLaneSize(zn, zm));
8923 VIXL_ASSERT(zn.GetLaneSizeInBytes() == (zd.GetLaneSizeInBytes() * 2));
8924 VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
8926 Emit(0x45207000 | SVESize(zn) | Rd(zd) | Rn(zn) | Rm(zm));
8930 const ZRegister& zn,
8937 VIXL_ASSERT(AreSameLaneSize(zn, zm));
8938 VIXL_ASSERT(zn.GetLaneSizeInBytes() == (zd.GetLaneSizeInBytes() * 2));
8939 VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
8941 Emit(0x45207400 | SVESize(zn) | Rd(zd) | Rn(zn) | Rm(zm));
8946 const ZRegister& zn,
8952 USE(zn);
8954 VIXL_ASSERT(zd.Is(zn));
8955 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
8977 const ZRegister& zn,
8984 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
8986 Emit(0x05202c00 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
8990 const ZRegister& zn,
8997 VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
8999 Emit(0x4500fc00 | SVESize(zda) | Rd(zda) | Rn(zn) | Rm(zm));
9003 const ZRegister& zn,
9010 VIXL_ASSERT(AreSameLaneSize(zn, zm));
9011 VIXL_ASSERT(zda.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
9014 Emit(0x4500c800 | SVESize(zda) | Rd(zda) | Rn(zn) | Rm(zm));
9018 const ZRegister& zn,
9025 VIXL_ASSERT(AreSameLaneSize(zn, zm));
9026 VIXL_ASSERT(zda.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
9029 Emit(0x4500cc00 | SVESize(zda) | Rd(zda) | Rn(zn) | Rm(zm));
9033 const ZRegister& zn,
9041 VIXL_ASSERT(AreSameLaneSize(zn, zm));
9042 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
9045 Emit(0x45003800 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
9049 const ZRegister& zn,
9057 VIXL_ASSERT(AreSameLaneSize(zn, zm));
9058 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
9061 Emit(0x45003c00 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
9066 const ZRegister& zn) {
9072 VIXL_ASSERT(zda.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
9075 Emit(0x4405a000 | SVESize(zda) | Rd(zda) | PgLow8(pg) | Rn(zn));
9079 const ZRegister& zn,
9087 VIXL_ASSERT(AreSameLaneSize(zn, zm));
9088 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
9091 Emit(0x45000800 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
9095 const ZRegister& zn,
9103 VIXL_ASSERT(AreSameLaneSize(zn, zm));
9104 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
9107 Emit(0x45000c00 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
9111 const ZRegister& zn,
9118 VIXL_ASSERT(AreSameLaneSize(zd, zn));
9122 Emit(0x45004800 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
9126 const ZRegister& zn,
9133 VIXL_ASSERT(AreSameLaneSize(zd, zn));
9137 Emit(0x45004c00 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
9142 const ZRegister& zn,
9148 USE(zn);
9150 VIXL_ASSERT(zd.Is(zn));
9151 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9158 const ZRegister& zn,
9164 USE(zn);
9166 VIXL_ASSERT(zd.Is(zn));
9167 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9174 const ZRegister& zn,
9180 USE(zn);
9182 VIXL_ASSERT(zd.Is(zn));
9183 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9190 const ZRegister& zn,
9196 USE(zn);
9198 VIXL_ASSERT(zd.Is(zn));
9199 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9206 const ZRegister& zn,
9212 USE(zn);
9214 VIXL_ASSERT(zd.Is(zn));
9215 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9221 const ZRegister& zn,
9229 VIXL_ASSERT(AreSameLaneSize(zn, zm));
9230 VIXL_ASSERT(zda.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
9232 Emit(0x44004800 | SVESize(zda) | Rd(zda) | Rn(zn) | Rm(zm));
9236 const ZRegister& zn,
9244 VIXL_ASSERT(AreSameLaneSize(zn, zm));
9245 VIXL_ASSERT(zda.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
9247 Emit(0x44004c00 | SVESize(zda) | Rd(zda) | Rn(zn) | Rm(zm));
9251 const ZRegister& zn,
9259 VIXL_ASSERT(AreSameLaneSize(zn, zm));
9260 VIXL_ASSERT(zda.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
9262 Emit(0x44005800 | SVESize(zda) | Rd(zda) | Rn(zn) | Rm(zm));
9266 const ZRegister& zn,
9274 VIXL_ASSERT(AreSameLaneSize(zn, zm));
9275 VIXL_ASSERT(zda.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
9277 Emit(0x44005c00 | SVESize(zda) | Rd(zda) | Rn(zn) | Rm(zm));
9281 const ZRegister& zn,
9288 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9290 Emit(0x04206c00 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
9294 const ZRegister& zn,
9301 VIXL_ASSERT(AreSameLaneSize(zn, zm));
9303 VIXL_ASSERT(zd.GetLaneSizeInBytes() == zn.GetLaneSizeInBytes() * 2);
9305 Emit(0x45007800 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
9309 const ZRegister& zn,
9316 VIXL_ASSERT(AreSameLaneSize(zn, zm));
9318 VIXL_ASSERT(zd.GetLaneSizeInBytes() == zn.GetLaneSizeInBytes() * 2);
9320 Emit(0x45007c00 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
9325 const ZRegister& zn,
9331 USE(zn);
9333 VIXL_ASSERT(zd.Is(zn));
9334 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9341 const ZRegister& zn,
9348 USE(zn);
9350 VIXL_ASSERT(zd.Is(zn));
9351 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9358 const ZRegister& zn,
9365 USE(zn);
9367 VIXL_ASSERT(zd.Is(zn));
9368 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9375 const ZRegister& zn,
9382 USE(zn);
9384 VIXL_ASSERT(zd.Is(zn));
9392 const ZRegister& zn,
9399 USE(zn);
9401 VIXL_ASSERT(zd.Is(zn));
9402 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9409 const ZRegister& zn,
9416 USE(zn);
9418 VIXL_ASSERT(zd.Is(zn));
9419 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9426 const ZRegister& zn,
9432 USE(zn);
9434 VIXL_ASSERT(zd.Is(zn));
9435 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9442 const ZRegister& zn,
9448 USE(zn);
9450 VIXL_ASSERT(zd.Is(zn));
9451 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9456 void Assembler::uqxtnb(const ZRegister& zd, const ZRegister& zn) {
9463 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() / 2));
9467 SVEBitwiseShiftImmediate(zd, zn, size, 0x45204800);
9470 void Assembler::uqxtnt(const ZRegister& zd, const ZRegister& zn) {
9477 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() / 2));
9481 SVEBitwiseShiftImmediate(zd, zn, size, 0x45204c00);
9486 const ZRegister& zn) {
9492 VIXL_ASSERT(zd.IsLaneSizeS() && zn.IsLaneSizeS());
9494 Emit(0x4400a000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
9499 const ZRegister& zn,
9505 USE(zn);
9507 VIXL_ASSERT(zd.Is(zn));
9508 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9515 const ZRegister& zn,
9522 USE(zn);
9524 VIXL_ASSERT(zd.Is(zn));
9525 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9532 const ZRegister& zn,
9539 USE(zn);
9541 VIXL_ASSERT(zd.Is(zn));
9542 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9549 const ZRegister& zn,
9556 USE(zn);
9558 VIXL_ASSERT(zd.Is(zn));
9566 const ZRegister& zn) {
9572 VIXL_ASSERT(zd.IsLaneSizeS() && zn.IsLaneSizeS());
9574 Emit(0x4401a000 | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
9577 void Assembler::ursra(const ZRegister& zda, const ZRegister& zn, int shift) {
9584 VIXL_ASSERT(AreSameLaneSize(zda, zn));
9588 SVEBitwiseShiftImmediate(zda, zn, encoded_imm, 0x4500ec00);
9591 void Assembler::ushllb(const ZRegister& zd, const ZRegister& zn, int shift) {
9598 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
9601 EncodeSVEShiftLeftImmediate(shift, zn.GetLaneSizeInBits());
9602 SVEBitwiseShiftImmediate(zd, zn, encoded_imm, 0x4500a800);
9605 void Assembler::ushllt(const ZRegister& zd, const ZRegister& zn, int shift) {
9612 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
9615 EncodeSVEShiftLeftImmediate(shift, zn.GetLaneSizeInBits());
9616 SVEBitwiseShiftImmediate(zd, zn, encoded_imm, 0x4500ac00);
9621 const ZRegister& zn,
9627 USE(zn);
9629 VIXL_ASSERT(zd.Is(zn));
9630 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
9635 void Assembler::usra(const ZRegister& zda, const ZRegister& zn, int shift) {
9642 VIXL_ASSERT(AreSameLaneSize(zda, zn));
9646 SVEBitwiseShiftImmediate(zda, zn, encoded_imm, 0x4500e400);
9650 const ZRegister& zn,
9658 VIXL_ASSERT(AreSameLaneSize(zn, zm));
9659 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
9662 Emit(0x45001800 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
9666 const ZRegister& zn,
9674 VIXL_ASSERT(AreSameLaneSize(zn, zm));
9675 VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
9678 Emit(0x45001c00 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
9682 const ZRegister& zn,
9689 VIXL_ASSERT(AreSameLaneSize(zd, zn));
9693 Emit(0x45005800 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
9697 const ZRegister& zn,
9704 VIXL_ASSERT(AreSameLaneSize(zd, zn));
9708 Emit(0x45005c00 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
9798 const ZRegister& zn,
9805 USE(zn);
9807 VIXL_ASSERT(zd.Is(zn));
9816 const ZRegister& zn,
9821 VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
9823 Emit(0x6420e400 | SVESize(zda) | Rd(zda) | Rn(zn) | Rm(zm));
9827 const ZRegister& zn,
9832 VIXL_ASSERT(zn.IsLaneSizeB() && zm.IsLaneSizeB());
9834 Emit(0x45009800 | Rd(zda) | Rn(zn) | Rm(zm));
9838 const ZRegister& zn,
9843 VIXL_ASSERT(zn.IsLaneSizeB() && zm.IsLaneSizeB());
9845 Emit(0x45809800 | Rd(zda) | Rn(zn) | Rm(zm));
9849 const ZRegister& zn,
9854 VIXL_ASSERT(zn.IsLaneSizeB() && zm.IsLaneSizeB());
9856 Emit(0x45c09800 | Rd(zda) | Rn(zn) | Rm(zm));
9860 const ZRegister& zn,
9865 VIXL_ASSERT(zn.IsLaneSizeB() && zm.IsLaneSizeB());
9867 Emit(0x44807800 | Rd(zda) | Rn(zn) | Rm(zm));
9871 const ZRegister& zn,
9877 VIXL_ASSERT(zn.IsLaneSizeB() && zm.IsLaneSizeB());
9881 Emit(0x44a01800 | Rx<18, 16>(zm) | (index << 19) | Rd(zda) | Rn(zn));
9885 const ZRegister& zn,
9891 VIXL_ASSERT(zn.IsLaneSizeB() && zm.IsLaneSizeB());
9895 Emit(0x44a01c00 | Rx<18, 16>(zm) | (index << 19) | Rd(zda) | Rn(zn));