Lines Matching defs:shift
32 void Assembler::ResolveSVEImm8Shift(int* imm8, int* shift) {
33 if (*shift < 0) {
34 VIXL_ASSERT(*shift == -1);
35 // Derive the shift amount from the immediate.
37 *shift = 0;
40 *shift = 8;
45 VIXL_ASSERT((*shift == 0) || (*shift == 8));
181 int shift) {
191 EncodeSVEShiftRightImmediate(shift, zd.GetLaneSizeInBits());
220 int shift) {
231 EncodeSVEShiftRightImmediate(shift, zd.GetLaneSizeInBits());
255 int shift) {
266 EncodeSVEShiftLeftImmediate(shift, zd.GetLaneSizeInBits());
312 int shift) {
323 EncodeSVEShiftRightImmediate(shift, zd.GetLaneSizeInBits());
368 Instr Assembler::EncodeSVEShiftLeftImmediate(int shift, int lane_size_in_bits) {
369 VIXL_ASSERT((shift >= 0) && (shift < lane_size_in_bits));
370 return lane_size_in_bits + shift;
373 Instr Assembler::EncodeSVEShiftRightImmediate(int shift,
375 VIXL_ASSERT((shift > 0) && (shift <= lane_size_in_bits));
376 return (2 * lane_size_in_bits) - shift;
389 void Assembler::asr(const ZRegister& zd, const ZRegister& zn, int shift) {
393 EncodeSVEShiftRightImmediate(shift, zd.GetLaneSizeInBits());
407 void Assembler::lsl(const ZRegister& zd, const ZRegister& zn, int shift) {
410 EncodeSVEShiftLeftImmediate(shift, zd.GetLaneSizeInBits());
424 void Assembler::lsr(const ZRegister& zd, const ZRegister& zn, int shift) {
427 EncodeSVEShiftRightImmediate(shift, zd.GetLaneSizeInBits());
3561 int shift) {
3562 // CPY <Zd>.<T>, <Pg>/<ZM>, #<imm>{, <shift>}
3569 ResolveSVEImm8Shift(&imm8, &shift);
3571 Instr sh = (shift > 0) ? (1 << 13) : 0;
3595 int shift) {
3596 if (shift < 0) {
3597 VIXL_ASSERT(shift == -1);
3598 // Derive the shift amount from the immediate.
3600 shift = 0;
3603 shift = 8;
3608 VIXL_ASSERT((shift == 0) || (shift == 8));
3610 Instr shift_bit = (shift > 0) ? (1 << 13) : 0;
3617 int shift) {
3618 // ADD <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
3627 SVEIntAddSubtractImmUnpredicatedHelper(ADD_z_zi, zd, imm8, shift);
3630 void Assembler::dup(const ZRegister& zd, int imm8, int shift) {
3631 // DUP <Zd>.<T>, #<imm>{, <shift>}
3637 ResolveSVEImm8Shift(&imm8, &shift);
3638 VIXL_ASSERT((shift < 8) || !zd.IsLaneSizeB());
3640 Instr shift_bit = (shift > 0) ? (1 << 13) : 0;
3698 int shift) {
3699 // SQADD <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
3708 SVEIntAddSubtractImmUnpredicatedHelper(SQADD_z_zi, zd, imm8, shift);
3714 int shift) {
3715 // SQSUB <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
3724 SVEIntAddSubtractImmUnpredicatedHelper(SQSUB_z_zi, zd, imm8, shift);
3730 int shift) {
3731 // SUB <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
3740 SVEIntAddSubtractImmUnpredicatedHelper(SUB_z_zi, zd, imm8, shift);
3746 int shift) {
3747 // SUBR <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
3756 SVEIntAddSubtractImmUnpredicatedHelper(SUBR_z_zi, zd, imm8, shift);
3788 int shift) {
3789 // UQADD <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
3798 SVEIntAddSubtractImmUnpredicatedHelper(UQADD_z_zi, zd, imm8, shift);
3804 int shift) {
3805 // UQSUB <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
3814 SVEIntAddSubtractImmUnpredicatedHelper(UQSUB_z_zi, zd, imm8, shift);
4608 // All prefetch scalar-plus-vector addressing modes use a shift corresponding
5094 // 64-bit scaled offset: [<Xn|SP>, <Zm>.D, LSL #<shift>]
5102 // 32-bit scaled offset: [<Xn|SP>, <Zm>.S, <mod> #<shift>]
5104 // 32-bit unpacked scaled offset: [<Xn|SP>, <Zm>.D, <mod> #<shift>]
6538 int shift) {
6540 cpy(zd, pg, imm8, shift);
6589 void Assembler::mov(const ZRegister& zd, int imm8, int shift) {
6590 dup(zd, imm8, shift);
7488 void Assembler::MNE(const ZRegister& zd, const ZRegister& zn, int shift) { \
7493 EncodeSVEShiftRightImmediate(shift, zd.GetLaneSizeInBits()); \
7773 void Assembler::sli(const ZRegister& zd, const ZRegister& zn, int shift) {
7781 EncodeSVEShiftLeftImmediate(shift, zd.GetLaneSizeInBits());
8481 int shift) {
8491 EncodeSVEShiftLeftImmediate(shift, zd.GetLaneSizeInBits());
8532 int shift) {
8543 EncodeSVEShiftLeftImmediate(shift, zd.GetLaneSizeInBits());
8588 // XTN instructions look like immediate shifts with zero shift distance.
8602 // XTN instructions look like immediate shifts with zero shift distance.
8616 // XTN instructions look like immediate shifts with zero shift distance.
8630 // XTN instructions look like immediate shifts with zero shift distance.
8651 void Assembler::sri(const ZRegister& zd, const ZRegister& zn, int shift) {
8659 EncodeSVEShiftRightImmediate(shift, zd.GetLaneSizeInBits());
8701 int shift) {
8711 EncodeSVEShiftRightImmediate(shift, zd.GetLaneSizeInBits());
8715 void Assembler::srsra(const ZRegister& zda, const ZRegister& zn, int shift) {
8724 EncodeSVEShiftRightImmediate(shift, zda.GetLaneSizeInBits());
8729 void Assembler::sshllb(const ZRegister& zd, const ZRegister& zn, int shift) {
8739 EncodeSVEShiftLeftImmediate(shift, zn.GetLaneSizeInBits());
8743 void Assembler::sshllt(const ZRegister& zd, const ZRegister& zn, int shift) {
8753 EncodeSVEShiftLeftImmediate(shift, zn.GetLaneSizeInBits());
8757 void Assembler::ssra(const ZRegister& zda, const ZRegister& zn, int shift) {
8766 EncodeSVEShiftRightImmediate(shift, zda.GetLaneSizeInBits());
9376 int shift) {
9386 EncodeSVEShiftLeftImmediate(shift, zd.GetLaneSizeInBits());
9465 // XTN instructions look like immediate shifts with zero shift distance.
9479 // XTN instructions look like immediate shifts with zero shift distance.
9550 int shift) {
9560 EncodeSVEShiftRightImmediate(shift, zd.GetLaneSizeInBits());
9577 void Assembler::ursra(const ZRegister& zda, const ZRegister& zn, int shift) {
9586 EncodeSVEShiftRightImmediate(shift, zda.GetLaneSizeInBits());
9591 void Assembler::ushllb(const ZRegister& zd, const ZRegister& zn, int shift) {
9601 EncodeSVEShiftLeftImmediate(shift, zn.GetLaneSizeInBits());
9605 void Assembler::ushllt(const ZRegister& zd, const ZRegister& zn, int shift) {
9615 EncodeSVEShiftLeftImmediate(shift, zn.GetLaneSizeInBits());
9635 void Assembler::usra(const ZRegister& zda, const ZRegister& zn, int shift) {
9644 EncodeSVEShiftRightImmediate(shift, zda.GetLaneSizeInBits());
9800 int shift) {
9811 EncodeSVEShiftRightImmediate(shift, zd.GetLaneSizeInBits());