Lines Matching defs:index
1313 int index,
1320 Emit(FCMLA_z_zzzi_h | SVEMulComplexIndexHelper(zm, index) | rotate_bit |
1525 int index,
1532 // Allowable register number and lane index depends on the lane size.
1536 VIXL_ASSERT(IsUint3(index));
1538 // bit of the index. So, if index is less than four, the top bit of index
1541 if (index < 4) size = 0;
1542 // Top two bits of "zm" encode the index.
1543 zm_with_index |= (index & 3) << (Rm_offset + 3);
1548 VIXL_CHECK(IsUint2(index));
1549 // Top two bits of "zm" encode the index.
1550 zm_with_index |= (index & 3) << (Rm_offset + 3);
1555 VIXL_CHECK(IsUint1(index));
1556 // Top bit of "zm" encodes the index.
1557 zm_with_index |= (index & 1) << (Rm_offset + 4);
1566 Instr Assembler::SVEMulLongIndexHelper(const ZRegister& zm, int index) {
1571 VIXL_CHECK(IsUint3(index));
1572 imm_field = ExtractUnsignedBitfield32(2, 1, index) << 19;
1577 VIXL_CHECK(IsUint2(index));
1578 imm_field = ExtractBit(index, 1) << 20;
1583 imm_field |= ExtractBit(index, 0) << 11;
1588 Instr Assembler::SVEMulComplexIndexHelper(const ZRegister& zm, int index) {
1593 VIXL_CHECK(IsUint2(index));
1594 zm_idx_size = (index << 19) | Rx<18, 16>(zm) | 0;
1599 VIXL_CHECK(IsUint1(index));
1600 zm_idx_size = (index << 20) | Rx<19, 16>(zm) | (1 << 22);
1610 int index) {
1614 // The encoding of opcode, index, Zm, and size are synthesized in this
1618 index,
1629 int index) {
1633 // The encoding of opcode, index, Zm, and size are synthesized in this
1637 index,
1651 unsigned index) {
1659 // The encoding of opcode, index, Zm, and size are synthesized in this
1663 index,
2201 void Assembler::index(const ZRegister& zd, int start, int step) {
2212 void Assembler::index(const ZRegister& zd,
2228 void Assembler::index(const ZRegister& zd, const Register& rn, int imm5) {
2240 void Assembler::index(const ZRegister& zd, int imm5, const Register& rm) {
5328 int index) {
5336 VIXL_ASSERT(IsUint2(index));
5337 op = SDOT_z_zzzi_s | Rx<18, 16>(zm) | (index << 19) | Rd(zda) | Rn(zn);
5340 VIXL_ASSERT(IsUint1(index));
5341 op = SDOT_z_zzzi_d | Rx<19, 16>(zm) | (index << 20) | Rd(zda) | Rn(zn);
5354 int index) {
5362 VIXL_ASSERT(IsUint2(index));
5363 op = UDOT_z_zzzi_s | Rx<18, 16>(zm) | (index << 19) | Rd(zda) | Rn(zn);
5366 VIXL_ASSERT(IsUint1(index));
5367 op = UDOT_z_zzzi_d | Rx<19, 16>(zm) | (index << 20) | Rd(zda) | Rn(zn);
5972 void Assembler::dup(const ZRegister& zd, const ZRegister& zn, unsigned index) {
5979 VIXL_ASSERT((index * zd.GetLaneSizeInBits()) < 512);
5981 unsigned imm_7 = (index << (n + 1)) | (1 << n);
6556 void Assembler::mov(const ZRegister& zd, const ZRegister& zn, unsigned index) {
6558 dup(zd, zn, index);
6828 int index,
6839 VIXL_ASSERT(index >= 0);
6844 VIXL_ASSERT((zm.GetCode() <= 7) && (index <= 3));
6845 zm_and_idx = (index << 19) | Rx<18, 16>(zm);
6849 VIXL_ASSERT((zm.GetCode() <= 15) && (index <= 1));
6850 zm_and_idx = (index << 20) | Rx<19, 16>(zm);
6878 int index,
6889 Emit(0x44a06000 | SVEMulComplexIndexHelper(zm, index) | rotate_bit | Rd(zda) |
7134 int index) {
7138 VIXL_ASSERT((zm.GetCode() <= 7) && (index <= 7));
7139 Instr zm_and_idx = (ExtractUnsignedBitfield32(2, 1, index) << 19) |
7140 (ExtractBit(index, 0) << 11) | Rx<18, 16>(zm);
7162 int index) {
7170 VIXL_ASSERT((zm.GetCode() <= 7) && (index <= 7));
7171 Instr zm_and_idx = (ExtractUnsignedBitfield32(2, 1, index) << 19) |
7172 (ExtractBit(index, 0) << 11) | Rx<18, 16>(zm);
7194 int index) {
7202 VIXL_ASSERT((zm.GetCode() <= 7) && (index <= 7));
7203 Instr zm_and_idx = (ExtractUnsignedBitfield32(2, 1, index) << 19) |
7204 (ExtractBit(index, 0) << 11) | Rx<18, 16>(zm);
7226 int index) {
7234 VIXL_ASSERT((zm.GetCode() <= 7) && (index <= 7));
7235 Instr zm_and_idx = (ExtractUnsignedBitfield32(2, 1, index) << 19) |
7236 (ExtractBit(index, 0) << 11) | Rx<18, 16>(zm);
7288 int index) {
7298 index,
7309 int index) {
7319 index,
7330 int index) {
7340 index,
7838 int index) { \
7843 Instr zm_with_index = SVEMulLongIndexHelper(zm, index); \
8005 int index) {
8013 VIXL_ASSERT(index >= 0);
8018 VIXL_ASSERT((zm.GetCode() <= 7) && (index <= 7));
8019 zm_and_idx = (ExtractUnsignedBitfield32(2, 1, index) << 19) |
8020 (ExtractBit(index, 0) << 11) | Rx<18, 16>(zm);
8024 VIXL_ASSERT((zm.GetCode() <= 15) && (index <= 3));
8025 zm_and_idx = (ExtractBit(index, 1) << 20) | (ExtractBit(index, 0) << 11) |
8068 int index) {
8076 VIXL_ASSERT(index >= 0);
8081 VIXL_ASSERT((zm.GetCode() <= 7) && (index <= 7));
8082 zm_and_idx = (ExtractUnsignedBitfield32(2, 1, index) << 19) |
8083 (ExtractBit(index, 0) << 11) | Rx<18, 16>(zm);
8087 VIXL_ASSERT((zm.GetCode() <= 15) && (index <= 3));
8088 zm_and_idx = (ExtractBit(index, 1) << 20) | (ExtractBit(index, 0) << 11) |
8116 int index) {
8124 VIXL_ASSERT(index >= 0);
8129 VIXL_ASSERT((zm.GetCode() <= 7) && (index <= 7));
8130 zm_and_idx = (ExtractUnsignedBitfield32(2, 1, index) << 19) |
8131 (ExtractBit(index, 0) << 11) | Rx<18, 16>(zm);
8135 VIXL_ASSERT((zm.GetCode() <= 15) && (index <= 3));
8136 zm_and_idx = (ExtractBit(index, 1) << 20) | (ExtractBit(index, 0) << 11) |
8179 int index) {
8187 VIXL_ASSERT(index >= 0);
8192 VIXL_ASSERT((zm.GetCode() <= 7) && (index <= 7));
8193 zm_and_idx = (ExtractUnsignedBitfield32(2, 1, index) << 19) |
8194 (ExtractBit(index, 0) << 11) | Rx<18, 16>(zm);
8198 VIXL_ASSERT((zm.GetCode() <= 15) && (index <= 3));
8199 zm_and_idx = (ExtractBit(index, 1) << 20) | (ExtractBit(index, 0) << 11) |
8224 int index) {
8234 index,
8301 int index,
8312 Emit(0x44a07000 | SVEMulComplexIndexHelper(zm, index) | rotate_bit | Rd(zda) |
8339 int index) {
8346 // The encoding of opcode, index, Zm, and size are synthesized in this
8350 index,
8378 int index) {
8385 // The encoding of opcode, index, Zm, and size are synthesized in this
8389 index,
8413 int index) {
8423 index,
9873 int index) {
9879 VIXL_ASSERT(IsUint2(index));
9881 Emit(0x44a01800 | Rx<18, 16>(zm) | (index << 19) | Rd(zda) | Rn(zn));
9887 int index) {
9893 VIXL_ASSERT(IsUint2(index));
9895 Emit(0x44a01c00 | Rx<18, 16>(zm) | (index << 19) | Rd(zda) | Rn(zn));