Lines Matching defs:imm
2120 void movk(const Register& rd, uint64_t imm, int shift = -1) {
2121 MoveWide(rd, imm, shift, MOVK);
2125 void movn(const Register& rd, uint64_t imm, int shift = -1) {
2126 MoveWide(rd, imm, shift, MOVN);
2130 void movz(const Register& rd, uint64_t imm, int shift = -1) {
2131 MoveWide(rd, imm, shift, MOVZ);
2135 void mov(const Register& rd, uint64_t imm) {
2136 if (!OneInstrMoveImmediateHelper(this, rd, imm)) {
2225 void fmov(const VRegister& vd, double imm);
2228 void fmov(const VRegister& vd, float imm);
2231 void fmov(const VRegister& vd, Float16 imm);
2771 const uint64_t imm,
3568 void fcmeq(const VRegister& vd, const VRegister& vn, double imm);
3571 void fcmgt(const VRegister& vd, const VRegister& vn, double imm);
3574 void fcmge(const VRegister& vd, const VRegister& vn, double imm);
3577 void fcmle(const VRegister& vd, const VRegister& vn, double imm);
3580 void fcmlt(const VRegister& vd, const VRegister& vn, double imm);
3685 void and_(const ZRegister& zd, const ZRegister& zn, uint64_t imm);
3742 void bic(const ZRegister& zd, const ZRegister& zn, uint64_t imm);
4060 void dupm(const ZRegister& zd, uint64_t imm);
4063 void eon(const ZRegister& zd, const ZRegister& zn, uint64_t imm);
4078 void eor(const ZRegister& zd, const ZRegister& zn, uint64_t imm);
4123 double imm);
4231 void fcpy(const ZRegister& zd, const PRegisterM& pg, double imm);
4235 void fcpy(const ZRegister& zd, const PRegisterM& pg, Float16 imm) {
4236 fcpy(zd, pg, FPToDouble(imm, kIgnoreDefaultNaN));
4263 void fdup(const ZRegister& zd, double imm);
4266 void fdup(const ZRegister& zd, Float16 imm) {
4267 fdup(zd, FPToDouble(imm, kIgnoreDefaultNaN));
4284 double imm);
4296 double imm);
4314 double imm);
4326 double imm);
4369 void fmov(const ZRegister& zd, double imm);
4372 void fmov(const ZRegister& zd, const PRegisterM& pg, double imm);
4385 double imm);
4488 double imm);
4503 double imm);
5078 void mov(const ZRegister& zd, uint64_t imm);
5153 void orn(const ZRegister& zd, const ZRegister& zn, uint64_t imm);
5168 void orr(const ZRegister& zd, const ZRegister& zn, uint64_t imm);
7132 uint64_t imm);
7215 static Instr ImmField(int64_t imm) {
7219 VIXL_ASSERT(IsIntN(fieldsize, imm));
7220 return static_cast<Instr>(TruncateToUintN(fieldsize, imm) << lobit);
7226 static Instr ImmUnsignedField(uint64_t imm) {
7229 VIXL_ASSERT(IsUintN(hibit - lobit + 1, imm));
7230 return static_cast<Instr>(imm << lobit);
7236 Instr imm = static_cast<Instr>(TruncateToUint21(imm21));
7237 Instr immhi = (imm >> ImmPCRelLo_width) << ImmPCRelHi_offset;
7238 Instr immlo = imm << ImmPCRelLo_offset;
7278 static Instr ImmAddSub(int imm) {
7279 VIXL_ASSERT(IsImmAddSub(imm));
7280 if (IsUint12(imm)) { // No shift required.
7281 imm <<= ImmAddSub_offset;
7283 imm = ((imm >> 12) << ImmAddSub_offset) | (1 << ImmAddSubShift_offset);
7285 return imm;
7397 static Instr ImmCondCmp(unsigned imm) {
7398 VIXL_ASSERT(IsUint5(imm));
7399 return imm << ImmCondCmp_offset;
7505 static Instr ImmMoveWide(uint64_t imm) {
7506 VIXL_ASSERT(IsUint16(imm));
7507 return static_cast<Instr>(imm << ImmMoveWide_offset);
7516 static Instr ImmFP16(Float16 imm);
7517 static Instr ImmFP32(float imm);
7518 static Instr ImmFP64(double imm);
7544 static bool IsImmFP16(Float16 imm);
7546 static bool IsImmFP32(float imm) { return IsImmFP32(FloatToRawbits(imm)); }
7550 static bool IsImmFP64(double imm) { return IsImmFP64(DoubleToRawbits(imm)); }
7561 static bool IsImmMovn(uint64_t imm, unsigned reg_size);
7562 static bool IsImmMovz(uint64_t imm, unsigned reg_size);
7974 void SVELogicalImmediate(const ZRegister& zd, uint64_t imm, Instr op);
8004 int imm,
8010 unsigned imm,
8143 static uint32_t FP16ToImm8(Float16 imm);
8144 static uint32_t FP32ToImm8(float imm);
8145 static uint32_t FP64ToImm8(double imm);
8149 uint64_t imm,
8166 void LoadLiteral(const CPURegister& rt, uint64_t imm, LoadLiteralOp op);