Lines Matching refs:wn
826 const Register& wn,
829 VIXL_ASSERT(wd.Is32Bits() && wn.Is32Bits() && wm.Is32Bits());
830 Emit(SF(wm) | Rm(wm) | CRC32B | Rn(wn) | Rd(wd));
835 const Register& wn,
838 VIXL_ASSERT(wd.Is32Bits() && wn.Is32Bits() && wm.Is32Bits());
839 Emit(SF(wm) | Rm(wm) | CRC32H | Rn(wn) | Rd(wd));
844 const Register& wn,
847 VIXL_ASSERT(wd.Is32Bits() && wn.Is32Bits() && wm.Is32Bits());
848 Emit(SF(wm) | Rm(wm) | CRC32W | Rn(wn) | Rd(wd));
853 const Register& wn,
856 VIXL_ASSERT(wd.Is32Bits() && wn.Is32Bits() && xm.Is64Bits());
857 Emit(SF(xm) | Rm(xm) | CRC32X | Rn(wn) | Rd(wd));
862 const Register& wn,
865 VIXL_ASSERT(wd.Is32Bits() && wn.Is32Bits() && wm.Is32Bits());
866 Emit(SF(wm) | Rm(wm) | CRC32CB | Rn(wn) | Rd(wd));
871 const Register& wn,
874 VIXL_ASSERT(wd.Is32Bits() && wn.Is32Bits() && wm.Is32Bits());
875 Emit(SF(wm) | Rm(wm) | CRC32CH | Rn(wn) | Rd(wd));
880 const Register& wn,
883 VIXL_ASSERT(wd.Is32Bits() && wn.Is32Bits() && wm.Is32Bits());
884 Emit(SF(wm) | Rm(wm) | CRC32CW | Rn(wn) | Rd(wd));
889 const Register& wn,
892 VIXL_ASSERT(wd.Is32Bits() && wn.Is32Bits() && xm.Is64Bits());
893 Emit(SF(xm) | Rm(xm) | CRC32CX | Rn(wn) | Rd(wd));
930 const Register& wn,
934 VIXL_ASSERT(wn.Is32Bits() && wm.Is32Bits());
935 DataProcessing3Source(xd, wn, wm, xa, UMADDL_x);
940 const Register& wn,
944 VIXL_ASSERT(wn.Is32Bits() && wm.Is32Bits());
945 DataProcessing3Source(xd, wn, wm, xa, SMADDL_x);
950 const Register& wn,
954 VIXL_ASSERT(wn.Is32Bits() && wm.Is32Bits());
955 DataProcessing3Source(xd, wn, wm, xa, UMSUBL_x);
960 const Register& wn,
964 VIXL_ASSERT(wn.Is32Bits() && wm.Is32Bits());
965 DataProcessing3Source(xd, wn, wm, xa, SMSUBL_x);
970 const Register& wn,
973 VIXL_ASSERT(wn.Is32Bits() && wm.Is32Bits());
974 DataProcessing3Source(xd, wn, wm, xzr, SMADDL_x);