Lines Matching refs:vm
317 const VRegister& vm,
322 VIXL_ASSERT(AreSameFormat(vd, vm));
323 Emit(op | (vd.IsQ() ? NEON_Q : 0) | Rm(vm) | Rn(vn) | Rd(vd));
329 const VRegister& vm) {
331 NEONTable(vd, vn, vm, NEON_TBL_1v);
338 const VRegister& vm) {
343 NEONTable(vd, vn, vm, NEON_TBL_2v);
351 const VRegister& vm) {
356 NEONTable(vd, vn, vm, NEON_TBL_3v);
365 const VRegister& vm) {
370 NEONTable(vd, vn, vm, NEON_TBL_4v);
376 const VRegister& vm) {
378 NEONTable(vd, vn, vm, NEON_TBX_1v);
385 const VRegister& vm) {
390 NEONTable(vd, vn, vm, NEON_TBX_2v);
398 const VRegister& vm) {
403 NEONTable(vd, vn, vm, NEON_TBX_3v);
412 const VRegister& vm) {
417 NEONTable(vd, vn, vm, NEON_TBX_4v);
2919 const VRegister& vm,
2921 VIXL_ASSERT(AreSameFormat(vn, vm));
2933 Emit(format | op | Rm(vm) | Rn(vn) | Rd(vd));
2939 const VRegister& vm,
2942 VIXL_ASSERT((vm.Is8B() && vd.Is8H()) || (vm.Is4H() && vd.Is4S()) ||
2943 (vm.Is2S() && vd.Is2D()) || (vm.Is16B() && vd.Is8H()) ||
2944 (vm.Is8H() && vd.Is4S()) || (vm.Is4S() && vd.Is2D()));
2945 Emit(VFormat(vm) | vop | Rm(vm) | Rn(vn) | Rd(vd));
2951 const VRegister& vm,
2953 VIXL_ASSERT(AreSameFormat(vm, vn));
2957 Emit(VFormat(vd) | vop | Rm(vm) | Rn(vn) | Rd(vd));
3005 const VRegister& vm) { \
3008 NEON3DifferentL(vd, vn, vm, OP); \
3028 const VRegister& vm) { \
3031 NEON3DifferentHN(vd, vn, vm, OP); \
3038 const VRegister& vm) {
3040 VIXL_ASSERT(vm.IsD());
3041 NEON3DifferentW(vd, vn, vm, NEON_UADDW);
3047 const VRegister& vm) {
3049 VIXL_ASSERT(vm.IsQ());
3050 NEON3DifferentW(vd, vn, vm, NEON_UADDW2);
3056 const VRegister& vm) {
3058 VIXL_ASSERT(vm.IsD());
3059 NEON3DifferentW(vd, vn, vm, NEON_SADDW);
3065 const VRegister& vm) {
3067 VIXL_ASSERT(vm.IsQ());
3068 NEON3DifferentW(vd, vn, vm, NEON_SADDW2);
3074 const VRegister& vm) {
3076 VIXL_ASSERT(vm.IsD());
3077 NEON3DifferentW(vd, vn, vm, NEON_USUBW);
3083 const VRegister& vm) {
3085 VIXL_ASSERT(vm.IsQ());
3086 NEON3DifferentW(vd, vn, vm, NEON_USUBW2);
3092 const VRegister& vm) {
3094 VIXL_ASSERT(vm.IsD());
3095 NEON3DifferentW(vd, vn, vm, NEON_SSUBW);
3101 const VRegister& vm) {
3103 VIXL_ASSERT(vm.IsQ());
3104 NEON3DifferentW(vd, vn, vm, NEON_SSUBW2);
3371 const VRegister& vm,
3384 FPDataProcessing3Source(vd, vn, vm, va, op);
3390 const VRegister& vm,
3403 FPDataProcessing3Source(vd, vn, vm, va, op);
3409 const VRegister& vm,
3422 FPDataProcessing3Source(vd, vn, vm, va, op);
3428 const VRegister& vm,
3441 FPDataProcessing3Source(vd, vn, vm, va, op);
3447 const VRegister& vm) {
3449 VIXL_ASSERT(AreSameSizeAndType(vd, vn, vm));
3460 Emit(FPType(vd) | op | Rm(vm) | Rn(vn) | Rd(vd));
3479 const VRegister& vm,
3482 VIXL_ASSERT(vn.IsSameSizeAndType(vm));
3484 Emit(FPType(vn) | op | Rm(vm) | Rn(vn));
3488 void Assembler::fcmp(const VRegister& vn, const VRegister& vm) {
3491 FPCompareMacro(vn, vm, DisableTrap);
3495 void Assembler::fcmpe(const VRegister& vn, const VRegister& vm) {
3498 FPCompareMacro(vn, vm, EnableTrap);
3517 const VRegister& vm,
3522 VIXL_ASSERT(vn.IsSameSizeAndType(vm));
3524 Emit(FPType(vn) | op | Rm(vm) | Cond(cond) | Rn(vn) | Nzcv(nzcv));
3528 const VRegister& vm,
3533 FPCCompareMacro(vn, vm, nzcv, cond, DisableTrap);
3538 const VRegister& vm,
3543 FPCCompareMacro(vn, vm, nzcv, cond, EnableTrap);
3549 const VRegister& vm,
3554 VIXL_ASSERT(AreSameFormat(vd, vn, vm));
3555 Emit(FPType(vd) | FCSEL | Rm(vm) | Cond(cond) | Rn(vn) | Rd(vd));
3834 const VRegister& vm,
3836 VIXL_ASSERT(AreSameFormat(vd, vn, vm));
3847 Emit(format | op | Rm(vm) | Rn(vn) | Rd(vd));
3853 const VRegister& vm,
3855 VIXL_ASSERT(AreSameFormat(vd, vn, vm));
3856 Emit(FPFormat(vd) | op | Rm(vm) | Rn(vn) | Rd(vd));
3862 const VRegister& vm,
3864 VIXL_ASSERT(AreSameFormat(vd, vn, vm));
3867 Emit(op | Rm(vm) | Rn(vn) | Rd(vd));
4220 const VRegister& vm) { \
4223 NEON3Same(vd, vn, vm, OP); \
4262 const VRegister& vm) { \
4294 NEON3SameFP16(vd, vn, vm, op); \
4296 NEONFP3Same(vd, vn, vm, op); \
4314 const VRegister& vm) { \
4319 VIXL_ASSERT((vd.Is2S() && vn.Is2H() && vm.Is2H()) || \
4320 (vd.Is4S() && vn.Is4H() && vm.Is4H())); \
4321 Emit(FPFormat(vd) | VEC_OP | Rm(vm) | Rn(vn) | Rd(vd)); \
4336 const VRegister& vm) {
4338 VIXL_ASSERT(AreSameFormat(vd, vn, vm));
4349 Emit(format | op | Rm(vm) | Rn(vn) | Rd(vd));
4355 const VRegister& vm) {
4357 VIXL_ASSERT(AreSameFormat(vd, vn, vm));
4368 Emit(format | op | Rm(vm) | Rn(vn) | Rd(vd));
4374 const VRegister& vm) {
4376 VIXL_ASSERT(AreSameFormat(vn, vm));
4379 Emit(VFormat(vd) | NEON_SDOT | Rm(vm) | Rn(vn) | Rd(vd));
4385 const VRegister& vm) {
4387 VIXL_ASSERT(AreSameFormat(vn, vm));
4390 Emit(VFormat(vd) | NEON_UDOT | Rm(vm) | Rn(vn) | Rd(vd));
4395 const VRegister& vm) {
4397 VIXL_ASSERT(AreSameFormat(vn, vm));
4400 Emit(VFormat(vd) | 0x0e809c00 | Rm(vm) | Rn(vn) | Rd(vd));
4471 const VRegister& vm,
4476 VIXL_ASSERT((vm.IsH() && (vd.Is8H() || vd.Is4H())) ||
4477 (vm.IsS() && vd.Is4S()));
4480 Emit(VFormat(vd) | Rm(vm) | NEON_FCMLA_byelement |
4488 const VRegister& vm,
4491 VIXL_ASSERT(AreSameFormat(vd, vn, vm));
4494 Emit(VFormat(vd) | Rm(vm) | NEON_FCMLA | ImmRotFcmlaVec(rot) | Rn(vn) |
4502 const VRegister& vm,
4505 VIXL_ASSERT(AreSameFormat(vd, vn, vm));
4508 Emit(VFormat(vd) | Rm(vm) | NEON_FCADD | ImmRotFcadd(rot) | Rn(vn) | Rd(vd));
4599 const VRegister& vm,
4604 VIXL_ASSERT((vd.Is2S() && vm.Is1S()) || (vd.Is4S() && vm.Is1S()) ||
4605 (vd.Is1S() && vm.Is1S()) || (vd.Is2D() && vm.Is1D()) ||
4606 (vd.Is1D() && vm.Is1D()) || (vd.Is4H() && vm.Is1H()) ||
4607 (vd.Is8H() && vm.Is1H()) || (vd.Is1H() && vm.Is1H()));
4608 VIXL_ASSERT((vm.Is1S() && (vm_index < 4)) || (vm.Is1D() && (vm_index < 2)) ||
4609 (vm.Is1H() && (vm.GetCode() < 16) && (vm_index < 8)));
4613 if (vm.Is1D()) {
4615 } else if (vm.Is1S()) {
4626 if (!vm.Is1H()) {
4632 Emit(op | ImmNEONHLM(vm_index, index_num_bits) | Rm(vm) | Rn(vn) | Rd(vd));
4638 const VRegister& vm,
4642 VIXL_ASSERT((vd.Is4H() && vm.Is1H()) || (vd.Is8H() && vm.Is1H()) ||
4643 (vd.Is1H() && vm.Is1H()) || (vd.Is2S() && vm.Is1S()) ||
4644 (vd.Is4S() && vm.Is1S()) || (vd.Is1S() && vm.Is1S()));
4645 VIXL_ASSERT((vm.Is1H() && (vm.GetCode() < 16) && (vm_index < 8)) ||
4646 (vm.Is1S() && (vm_index < 4)));
4649 int index_num_bits = vm.Is1H() ? 3 : 2;
4656 Emit(format | op | ImmNEONHLM(vm_index, index_num_bits) | Rm(vm) | Rn(vn) |
4663 const VRegister& vm,
4666 VIXL_ASSERT((vd.Is4S() && vn.Is4H() && vm.Is1H()) ||
4667 (vd.Is4S() && vn.Is8H() && vm.Is1H()) ||
4668 (vd.Is1S() && vn.Is1H() && vm.Is1H()) ||
4669 (vd.Is2D() && vn.Is2S() && vm.Is1S()) ||
4670 (vd.Is2D() && vn.Is4S() && vm.Is1S()) ||
4671 (vd.Is1D() && vn.Is1S() && vm.Is1S()));
4673 VIXL_ASSERT((vm.Is1H() && (vm.GetCode() < 16) && (vm_index < 8)) ||
4674 (vm.Is1S() && (vm_index < 4)));
4677 int index_num_bits = vm.Is1H() ? 3 : 2;
4684 Emit(format | op | ImmNEONHLM(vm_index, index_num_bits) | Rm(vm) | Rn(vn) |
4691 const VRegister& vm,
4694 VIXL_ASSERT((vd.Is2S() && vn.Is8B() && vm.Is1S4B()) ||
4695 (vd.Is4S() && vn.Is16B() && vm.Is1S4B()));
4699 ImmNEONHLM(vm_index, index_num_bits) | Rm(vm) | Rn(vn) | Rd(vd));
4705 const VRegister& vm,
4708 VIXL_ASSERT((vd.Is2S() && vn.Is8B() && vm.Is1S4B()) ||
4709 (vd.Is4S() && vn.Is16B() && vm.Is1S4B()));
4713 ImmNEONHLM(vm_index, index_num_bits) | Rm(vm) | Rn(vn) | Rd(vd));
4718 const VRegister& vm,
4721 VIXL_ASSERT((vd.Is2S() && vn.Is8B() && vm.Is1S4B()) ||
4722 (vd.Is4S() && vn.Is16B() && vm.Is1S4B()));
4725 Emit(q | 0x0f00f000 | ImmNEONHLM(vm_index, index_num_bits) | Rm(vm) | Rn(vn) |
4732 const VRegister& vm,
4735 VIXL_ASSERT((vd.Is2S() && vn.Is8B() && vm.Is1S4B()) ||
4736 (vd.Is4S() && vn.Is16B() && vm.Is1S4B()));
4739 Emit(q | 0x0f80f000 | ImmNEONHLM(vm_index, index_num_bits) | Rm(vm) | Rn(vn) |
4755 const VRegister& vm, \
4759 NEONByElement(vd, vn, vm, vm_index, OP); \
4774 const VRegister& vm, \
4777 NEONByElement(vd, vn, vm, vm_index, OP); \
4794 const VRegister& vm, \
4798 NEONFPByElement(vd, vn, vm, vm_index, OP, OP_H); \
4830 const VRegister& vm, \
4834 NEONByElementL(vd, vn, vm, vm_index, OP); \
4852 const VRegister& vm, \
4859 VIXL_ASSERT(vm.IsH()); \
4862 VIXL_ASSERT(vm.GetCode() < 16); \
4863 Emit(FPFormat(vd) | OP | Rd(vd) | Rn(vn) | Rm(vm) | \
5002 const VRegister& vm,
5005 VIXL_ASSERT(AreSameFormat(vd, vn, vm));
5008 Emit(VFormat(vd) | NEON_EXT | Rm(vm) | ImmNEONExt(index) | Rn(vn) | Rd(vd));
5407 const VRegister& vm,
5409 VIXL_ASSERT(AreSameFormat(vd, vn, vm));
5411 Emit(VFormat(vd) | op | Rm(vm) | Rn(vn) | Rd(vd));
5417 const VRegister& vm) {
5419 NEONPerm(vd, vn, vm, NEON_TRN1);
5425 const VRegister& vm) {
5427 NEONPerm(vd, vn, vm, NEON_TRN2);
5433 const VRegister& vm) {
5435 NEONPerm(vd, vn, vm, NEON_UZP1);
5441 const VRegister& vm) {
5443 NEONPerm(vd, vn, vm, NEON_UZP2);
5449 const VRegister& vm) {
5451 NEONPerm(vd, vn, vm, NEON_ZIP1);
5457 const VRegister& vm) {
5459 NEONPerm(vd, vn, vm, NEON_ZIP2);
5800 void Assembler::smmla(const VRegister& vd, const VRegister& vn, const VRegister& vm) {
5804 VIXL_ASSERT(vn.IsLaneSizeB() && vm.IsLaneSizeB());
5806 Emit(0x4e80a400 | Rd(vd) | Rn(vn) | Rm(vm));
5809 void Assembler::usmmla(const VRegister& vd, const VRegister& vn, const VRegister& vm) {
5813 VIXL_ASSERT(vn.IsLaneSizeB() && vm.IsLaneSizeB());
5815 Emit(0x4e80ac00 | Rd(vd) | Rn(vn) | Rm(vm));
5818 void Assembler::ummla(const VRegister& vd, const VRegister& vn, const VRegister& vm) {
5822 VIXL_ASSERT(vn.IsLaneSizeB() && vm.IsLaneSizeB());
5824 Emit(0x6e80a400 | Rd(vd) | Rn(vn) | Rm(vm));
6132 const VRegister& vm,
6136 VIXL_ASSERT(AreSameSizeAndType(vd, vn, vm, va));
6137 Emit(FPType(vd) | op | Rm(vm) | Rn(vn) | Rd(vd) | Ra(va));