Lines Matching refs:src
1099 const MemOperand& src) {
1100 LoadStorePair(rt, rt2, src, LoadPairOpFor(rt, rt2));
1113 const MemOperand& src) {
1115 LoadStorePair(xt, xt2, src, LDPSW_x);
1157 const MemOperand& src) {
1158 LoadStorePairNonTemporal(rt, rt2, src, LoadPairNonTemporalOpFor(rt, rt2));
1190 const MemOperand& src,
1194 LoadStore(rt, src, LDRB_w, option);
1208 const MemOperand& src,
1212 LoadStore(rt, src, rt.Is64Bits() ? LDRSB_x : LDRSB_w, option);
1217 const MemOperand& src,
1221 LoadStore(rt, src, LDRH_w, option);
1235 const MemOperand& src,
1239 LoadStore(rt, src, rt.Is64Bits() ? LDRSH_x : LDRSH_w, option);
1244 const MemOperand& src,
1248 LoadStore(rt, src, LoadOpFor(rt), option);
1262 const MemOperand& src,
1267 LoadStore(xt, src, LDRSW_x, option);
1272 const MemOperand& src,
1276 LoadStore(rt, src, LDRB_w, option);
1290 const MemOperand& src,
1294 LoadStore(rt, src, rt.Is64Bits() ? LDRSB_x : LDRSB_w, option);
1299 const MemOperand& src,
1303 LoadStore(rt, src, LDRH_w, option);
1317 const MemOperand& src,
1321 LoadStore(rt, src, rt.Is64Bits() ? LDRSH_x : LDRSH_w, option);
1326 const MemOperand& src,
1330 LoadStore(rt, src, LoadOpFor(rt), option);
1344 const MemOperand& src,
1349 LoadStore(xt, src, LDRSW_x, option);
1353 void Assembler::ldraa(const Register& xt, const MemOperand& src) {
1355 LoadStorePAC(xt, src, LDRAA);
1359 void Assembler::ldrab(const Register& xt, const MemOperand& src) {
1361 LoadStorePAC(xt, src, LDRAB);
1428 void Assembler::ldxrb(const Register& rt, const MemOperand& src) {
1429 VIXL_ASSERT(src.IsImmediateOffset() && (src.GetOffset() == 0));
1430 Emit(LDXRB_w | Rs_mask | Rt(rt) | Rt2_mask | RnSP(src.GetBaseRegister()));
1434 void Assembler::ldxrh(const Register& rt, const MemOperand& src) {
1435 VIXL_ASSERT(src.IsImmediateOffset() && (src.GetOffset() == 0));
1436 Emit(LDXRH_w | Rs_mask | Rt(rt) | Rt2_mask | RnSP(src.GetBaseRegister()));
1440 void Assembler::ldxr(const Register& rt, const MemOperand& src) {
1441 VIXL_ASSERT(src.IsImmediateOffset() && (src.GetOffset() == 0));
1443 Emit(op | Rs_mask | Rt(rt) | Rt2_mask | RnSP(src.GetBaseRegister()));
1460 const MemOperand& src) {
1462 VIXL_ASSERT(src.IsImmediateOffset() && (src.GetOffset() == 0));
1464 Emit(op | Rs_mask | Rt(rt) | Rt2(rt2) | RnSP(src.GetBaseRegister()));
1493 void Assembler::ldaxrb(const Register& rt, const MemOperand& src) {
1494 VIXL_ASSERT(src.IsImmediateOffset() && (src.GetOffset() == 0));
1495 Emit(LDAXRB_w | Rs_mask | Rt(rt) | Rt2_mask | RnSP(src.GetBaseRegister()));
1499 void Assembler::ldaxrh(const Register& rt, const MemOperand& src) {
1500 VIXL_ASSERT(src.IsImmediateOffset() && (src.GetOffset() == 0));
1501 Emit(LDAXRH_w | Rs_mask | Rt(rt) | Rt2_mask | RnSP(src.GetBaseRegister()));
1505 void Assembler::ldaxr(const Register& rt, const MemOperand& src) {
1506 VIXL_ASSERT(src.IsImmediateOffset() && (src.GetOffset() == 0));
1508 Emit(op | Rs_mask | Rt(rt) | Rt2_mask | RnSP(src.GetBaseRegister()));
1525 const MemOperand& src) {
1527 VIXL_ASSERT(src.IsImmediateOffset() && (src.GetOffset() == 0));
1529 Emit(op | Rs_mask | Rt(rt) | Rt2(rt2) | RnSP(src.GetBaseRegister()));
1580 void Assembler::ldarb(const Register& rt, const MemOperand& src) {
1581 VIXL_ASSERT(src.IsImmediateOffset() && (src.GetOffset() == 0));
1582 Emit(LDARB_w | Rs_mask | Rt(rt) | Rt2_mask | RnSP(src.GetBaseRegister()));
1586 void Assembler::ldarh(const Register& rt, const MemOperand& src) {
1587 VIXL_ASSERT(src.IsImmediateOffset() && (src.GetOffset() == 0));
1588 Emit(LDARH_w | Rs_mask | Rt(rt) | Rt2_mask | RnSP(src.GetBaseRegister()));
1592 void Assembler::ldar(const Register& rt, const MemOperand& src) {
1593 VIXL_ASSERT(src.IsImmediateOffset() && (src.GetOffset() == 0));
1595 Emit(op | Rs_mask | Rt(rt) | Rt2_mask | RnSP(src.GetBaseRegister()));
1621 void Assembler::ldlarb(const Register& rt, const MemOperand& src) {
1623 VIXL_ASSERT(src.IsImmediateOffset() && (src.GetOffset() == 0));
1624 Emit(LDLARB | Rs_mask | Rt(rt) | Rt2_mask | RnSP(src.GetBaseRegister()));
1628 void Assembler::ldlarh(const Register& rt, const MemOperand& src) {
1630 VIXL_ASSERT(src.IsImmediateOffset() && (src.GetOffset() == 0));
1631 Emit(LDLARH | Rs_mask | Rt(rt) | Rt2_mask | RnSP(src.GetBaseRegister()));
1635 void Assembler::ldlar(const Register& rt, const MemOperand& src) {
1637 VIXL_ASSERT(src.IsImmediateOffset() && (src.GetOffset() == 0));
1639 Emit(op | Rs_mask | Rt(rt) | Rt2_mask | RnSP(src.GetBaseRegister()));
1654 const MemOperand& src) { \
1656 VIXL_ASSERT(src.IsImmediateOffset() && (src.GetOffset() == 0)); \
1659 Emit(op | Rs(rs) | Rt(rt) | Rt2_mask | RnSP(src.GetBaseRegister())); \
1679 const MemOperand& src) { \
1681 VIXL_ASSERT(src.IsImmediateOffset() && (src.GetOffset() == 0)); \
1682 Emit(OP | Rs(rs) | Rt(rt) | Rt2_mask | RnSP(src.GetBaseRegister())); \
1701 const MemOperand& src) { \
1704 VIXL_ASSERT(src.IsImmediateOffset() && (src.GetOffset() == 0)); \
1710 Emit(op | Rs(rs) | Rt(rt) | Rt2_mask | RnSP(src.GetBaseRegister())); \
1751 const MemOperand& src) { \
1753 VIXL_ASSERT(src.IsImmediateOffset() && (src.GetOffset() == 0)); \
1755 Emit(op | Rs(rs) | Rt(rt) | RnSP(src.GetBaseRegister())); \
1758 void Assembler::st##FN(const Register& rs, const MemOperand& src) { \
1760 ld##FN(rs, AppropriateZeroRegFor(rs), src); \
1771 const MemOperand& src) { \
1773 VIXL_ASSERT(src.IsImmediateOffset() && (src.GetOffset() == 0)); \
1775 Emit(op | Rs(rs) | Rt(rt) | RnSP(src.GetBaseRegister())); \
1785 void Assembler::ldaprb(const Register& rt, const MemOperand& src) {
1787 VIXL_ASSERT(src.IsImmediateOffset() && (src.GetOffset() == 0));
1789 Emit(op | Rs(xzr) | Rt(rt) | RnSP(src.GetBaseRegister()));
1792 void Assembler::ldapurb(const Register& rt, const MemOperand& src) {
1794 VIXL_ASSERT(src.IsImmediateOffset() && IsImmLSUnscaled(src.GetOffset()));
1796 Instr base = RnSP(src.GetBaseRegister());
1797 int64_t offset = src.GetOffset();
1801 void Assembler::ldapursb(const Register& rt, const MemOperand& src) {
1803 VIXL_ASSERT(src.IsImmediateOffset() && IsImmLSUnscaled(src.GetOffset()));
1805 Instr base = RnSP(src.GetBaseRegister());
1806 int64_t offset = src.GetOffset();
1811 void Assembler::ldaprh(const Register& rt, const MemOperand& src) {
1813 VIXL_ASSERT(src.IsImmediateOffset() && (src.GetOffset() == 0));
1815 Emit(op | Rs(xzr) | Rt(rt) | RnSP(src.GetBaseRegister()));
1818 void Assembler::ldapurh(const Register& rt, const MemOperand& src) {
1820 VIXL_ASSERT(src.IsImmediateOffset() && IsImmLSUnscaled(src.GetOffset()));
1822 Instr base = RnSP(src.GetBaseRegister());
1823 int64_t offset = src.GetOffset();
1827 void Assembler::ldapursh(const Register& rt, const MemOperand& src) {
1829 VIXL_ASSERT(src.IsImmediateOffset() && IsImmLSUnscaled(src.GetOffset()));
1831 Instr base = RnSP(src.GetBaseRegister());
1832 int64_t offset = src.GetOffset();
1837 void Assembler::ldapr(const Register& rt, const MemOperand& src) {
1839 VIXL_ASSERT(src.IsImmediateOffset() && (src.GetOffset() == 0));
1841 Emit(op | Rs(xzr) | Rt(rt) | RnSP(src.GetBaseRegister()));
1844 void Assembler::ldapur(const Register& rt, const MemOperand& src) {
1846 VIXL_ASSERT(src.IsImmediateOffset() && IsImmLSUnscaled(src.GetOffset()));
1848 Instr base = RnSP(src.GetBaseRegister());
1849 int64_t offset = src.GetOffset();
1854 void Assembler::ldapursw(const Register& rt, const MemOperand& src) {
1857 VIXL_ASSERT(src.IsImmediateOffset() && IsImmLSUnscaled(src.GetOffset()));
1859 Instr base = RnSP(src.GetBaseRegister());
1860 int64_t offset = src.GetOffset();
2588 void Assembler::ld1(const VRegister& vt, const MemOperand& src) {
2590 LoadStoreStruct(vt, src, NEON_LD1_1v);
2596 const MemOperand& src) {
2601 LoadStoreStruct(vt, src, NEON_LD1_2v);
2608 const MemOperand& src) {
2613 LoadStoreStruct(vt, src, NEON_LD1_3v);
2621 const MemOperand& src) {
2626 LoadStoreStruct(vt, src, NEON_LD1_4v);
2632 const MemOperand& src) {
2637 LoadStoreStruct(vt, src, NEON_LD2);
2644 const MemOperand& src) {
2649 LoadStoreStructSingle(vt, lane, src, NEONLoadStoreSingleStructLoad2);
2655 const MemOperand& src) {
2660 LoadStoreStructSingleAllLanes(vt, src, NEON_LD2R);
2667 const MemOperand& src) {
2672 LoadStoreStruct(vt, src, NEON_LD3);
2680 const MemOperand& src) {
2685 LoadStoreStructSingle(vt, lane, src, NEONLoadStoreSingleStructLoad3);
2692 const MemOperand& src) {
2697 LoadStoreStructSingleAllLanes(vt, src, NEON_LD3R);
2705 const MemOperand& src) {
2710 LoadStoreStruct(vt, src, NEON_LD4);
2719 const MemOperand& src) {
2724 LoadStoreStructSingle(vt, lane, src, NEONLoadStoreSingleStructLoad4);
2732 const MemOperand& src) {
2737 LoadStoreStructSingleAllLanes(vt, src, NEON_LD4R);
2741 void Assembler::st1(const VRegister& vt, const MemOperand& src) {
2743 LoadStoreStruct(vt, src, NEON_ST1_1v);
2749 const MemOperand& src) {
2754 LoadStoreStruct(vt, src, NEON_ST1_2v);
2761 const MemOperand& src) {
2766 LoadStoreStruct(vt, src, NEON_ST1_3v);
2774 const MemOperand& src) {
2779 LoadStoreStruct(vt, src, NEON_ST1_4v);
2899 void Assembler::ld1(const VRegister& vt, int lane, const MemOperand& src) {
2901 LoadStoreStructSingle(vt, lane, src, NEONLoadStoreSingleStructLoad1);
2905 void Assembler::ld1r(const VRegister& vt, const MemOperand& src) {
2907 LoadStoreStructSingleAllLanes(vt, src, NEON_LD1R);