Lines Matching refs:rn
471 const Register& rn,
473 AddSub(rd, rn, operand, LeaveFlags, ADD);
478 const Register& rn,
480 AddSub(rd, rn, operand, SetFlags, ADD);
484 void Assembler::cmn(const Register& rn, const Operand& operand) {
485 Register zr = AppropriateZeroRegFor(rn);
486 adds(zr, rn, operand);
491 const Register& rn,
493 AddSub(rd, rn, operand, LeaveFlags, SUB);
498 const Register& rn,
500 AddSub(rd, rn, operand, SetFlags, SUB);
504 void Assembler::cmp(const Register& rn, const Operand& operand) {
505 Register zr = AppropriateZeroRegFor(rn);
506 subs(zr, rn, operand);
523 const Register& rn,
525 AddSubWithCarry(rd, rn, operand, LeaveFlags, ADC);
530 const Register& rn,
532 AddSubWithCarry(rd, rn, operand, SetFlags, ADC);
537 const Register& rn,
539 AddSubWithCarry(rd, rn, operand, LeaveFlags, SBC);
544 const Register& rn,
546 AddSubWithCarry(rd, rn, operand, SetFlags, SBC);
557 void Assembler::setf8(const Register& rn) {
559 Emit(SETF8 | Rn(rn));
563 void Assembler::setf16(const Register& rn) {
565 Emit(SETF16 | Rn(rn));
583 const Register& rn,
585 Logical(rd, rn, operand, AND);
590 const Register& rn,
592 Logical(rd, rn, operand, ANDS);
596 void Assembler::tst(const Register& rn, const Operand& operand) {
597 ands(AppropriateZeroRegFor(rn), rn, operand);
602 const Register& rn,
604 Logical(rd, rn, operand, BIC);
609 const Register& rn,
611 Logical(rd, rn, operand, BICS);
616 const Register& rn,
618 Logical(rd, rn, operand, ORR);
623 const Register& rn,
625 Logical(rd, rn, operand, ORN);
630 const Register& rn,
632 Logical(rd, rn, operand, EOR);
637 const Register& rn,
639 Logical(rd, rn, operand, EON);
644 const Register& rn,
646 VIXL_ASSERT(rd.GetSizeInBits() == rn.GetSizeInBits());
648 Emit(SF(rd) | LSLV | Rm(rm) | Rn(rn) | Rd(rd));
653 const Register& rn,
655 VIXL_ASSERT(rd.GetSizeInBits() == rn.GetSizeInBits());
657 Emit(SF(rd) | LSRV | Rm(rm) | Rn(rn) | Rd(rd));
662 const Register& rn,
664 VIXL_ASSERT(rd.GetSizeInBits() == rn.GetSizeInBits());
666 Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd));
671 const Register& rn,
673 VIXL_ASSERT(rd.GetSizeInBits() == rn.GetSizeInBits());
675 Emit(SF(rd) | RORV | Rm(rm) | Rn(rn) | Rd(rd));
681 const Register& rn,
684 VIXL_ASSERT(rd.GetSizeInBits() == rn.GetSizeInBits());
687 ImmS(imms, rn.GetSizeInBits()) | Rn(rn) | Rd(rd));
692 const Register& rn,
695 VIXL_ASSERT(rd.Is64Bits() || rn.Is32Bits());
698 ImmS(imms, rn.GetSizeInBits()) | Rn(rn) | Rd(rd));
703 const Register& rn,
706 VIXL_ASSERT(rd.GetSizeInBits() == rn.GetSizeInBits());
709 ImmS(imms, rn.GetSizeInBits()) | Rn(rn) | Rd(rd));
714 const Register& rn,
717 VIXL_ASSERT(rd.GetSizeInBits() == rn.GetSizeInBits());
720 Emit(SF(rd) | EXTR | N | Rm(rm) | ImmS(lsb, rn.GetSizeInBits()) | Rn(rn) |
726 const Register& rn,
729 ConditionalSelect(rd, rn, rm, cond, CSEL);
734 const Register& rn,
737 ConditionalSelect(rd, rn, rm, cond, CSINC);
742 const Register& rn,
745 ConditionalSelect(rd, rn, rm, cond, CSINV);
750 const Register& rn,
753 ConditionalSelect(rd, rn, rm, cond, CSNEG);
771 void Assembler::cinc(const Register& rd, const Register& rn, Condition cond) {
773 csinc(rd, rn, rn, InvertCondition(cond));
777 void Assembler::cinv(const Register& rd, const Register& rn, Condition cond) {
779 csinv(rd, rn, rn, InvertCondition(cond));
783 void Assembler::cneg(const Register& rd, const Register& rn, Condition cond) {
785 csneg(rd, rn, rn, InvertCondition(cond));
790 const Register& rn,
794 VIXL_ASSERT(rd.GetSizeInBits() == rn.GetSizeInBits());
796 Emit(SF(rd) | op | Rm(rm) | Cond(cond) | Rn(rn) | Rd(rd));
800 void Assembler::ccmn(const Register& rn,
804 ConditionalCompare(rn, operand, nzcv, cond, CCMN);
808 void Assembler::ccmp(const Register& rn,
812 ConditionalCompare(rn, operand, nzcv, cond, CCMP);
817 const Register& rn,
821 Emit(SF(rd) | op | Rm(rm) | Ra(ra) | Rn(rn) | Rd(rd));
898 const Register& rn,
900 VIXL_ASSERT(AreSameSizeAndType(rd, rn, rm));
901 DataProcessing3Source(rd, rn, rm, AppropriateZeroRegFor(rd), MADD);
906 const Register& rn,
909 DataProcessing3Source(rd, rn, rm, ra, MADD);
914 const Register& rn,
916 VIXL_ASSERT(AreSameSizeAndType(rd, rn, rm));
917 DataProcessing3Source(rd, rn, rm, AppropriateZeroRegFor(rd), MSUB);
922 const Register& rn,
925 DataProcessing3Source(rd, rn, rm, ra, MSUB);
979 const Register& rn,
981 VIXL_ASSERT(rd.GetSizeInBits() == rn.GetSizeInBits());
983 Emit(SF(rd) | SDIV | Rm(rm) | Rn(rn) | Rd(rd));
1004 const Register& rn,
1006 VIXL_ASSERT(rd.GetSizeInBits() == rn.GetSizeInBits());
1008 Emit(SF(rd) | UDIV | Rm(rm) | Rn(rn) | Rd(rd));
1012 void Assembler::rbit(const Register& rd, const Register& rn) {
1013 DataProcessing1Source(rd, rn, RBIT);
1017 void Assembler::rev16(const Register& rd, const Register& rn) {
1018 DataProcessing1Source(rd, rn, REV16);
1028 void Assembler::rev(const Register& rd, const Register& rn) {
1029 DataProcessing1Source(rd, rn, rd.Is64Bits() ? REV_x : REV_w);
1033 void Assembler::clz(const Register& rd, const Register& rn) {
1034 DataProcessing1Source(rd, rn, CLZ);
1038 void Assembler::cls(const Register& rd, const Register& rn) {
1039 DataProcessing1Source(rd, rn, CLS);
2075 const Register& rn) {
2077 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2078 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero() && !rs.IsZero());
2080 Emit(0x1d800400 | Rd(rd) | Rn(rn) | Rs(rs));
2085 const Register& rn) {
2087 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2088 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero() && !rs.IsZero());
2090 Emit(0x1d80c400 | Rd(rd) | Rn(rn) | Rs(rs));
2095 const Register& rn) {
2097 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2098 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero() && !rs.IsZero());
2100 Emit(0x1d808400 | Rd(rd) | Rn(rn) | Rs(rs));
2105 const Register& rn) {
2107 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2108 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero() && !rs.IsZero());
2110 Emit(0x1d804400 | Rd(rd) | Rn(rn) | Rs(rs));
2115 const Register& rn) {
2117 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2118 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero() && !rs.IsZero());
2120 Emit(0x19800400 | Rd(rd) | Rn(rn) | Rs(rs));
2125 const Register& rn) {
2127 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2128 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero() && !rs.IsZero());
2130 Emit(0x1980c400 | Rd(rd) | Rn(rn) | Rs(rs));
2135 const Register& rn) {
2137 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2138 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero() && !rs.IsZero());
2140 Emit(0x19808400 | Rd(rd) | Rn(rn) | Rs(rs));
2145 const Register& rn) {
2147 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2148 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero() && !rs.IsZero());
2150 Emit(0x19804400 | Rd(rd) | Rn(rn) | Rs(rs));
2155 const Register& rn) {
2157 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2158 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero() && !rs.IsZero());
2160 Emit(0x19400400 | Rd(rd) | Rn(rn) | Rs(rs));
2165 const Register& rn) {
2167 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2168 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero() && !rs.IsZero());
2170 Emit(0x1940c400 | Rd(rd) | Rn(rn) | Rs(rs));
2175 const Register& rn) {
2177 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2178 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero() && !rs.IsZero());
2180 Emit(0x19408400 | Rd(rd) | Rn(rn) | Rs(rs));
2185 const Register& rn) {
2187 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2188 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero() && !rs.IsZero());
2190 Emit(0x19404400 | Rd(rd) | Rn(rn) | Rs(rs));
2195 const Register& rn) {
2197 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2198 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero() && !rs.IsZero());
2200 Emit(0x19000400 | Rd(rd) | Rn(rn) | Rs(rs));
2205 const Register& rn) {
2207 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2208 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero() && !rs.IsZero());
2210 Emit(0x1900c400 | Rd(rd) | Rn(rn) | Rs(rs));
2215 const Register& rn) {
2217 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2218 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero() && !rs.IsZero());
2220 Emit(0x19008400 | Rd(rd) | Rn(rn) | Rs(rs));
2225 const Register& rn) {
2227 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2228 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero() && !rs.IsZero());
2230 Emit(0x19004400 | Rd(rd) | Rn(rn) | Rs(rs));
2235 const Register& rn) {
2237 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2238 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero() && !rs.IsZero());
2240 Emit(0x1d400400 | Rd(rd) | Rn(rn) | Rs(rs));
2245 const Register& rn) {
2247 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2248 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero() && !rs.IsZero());
2250 Emit(0x1d40c400 | Rd(rd) | Rn(rn) | Rs(rs));
2255 const Register& rn) {
2257 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2258 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero() && !rs.IsZero());
2260 Emit(0x1d408400 | Rd(rd) | Rn(rn) | Rs(rs));
2265 const Register& rn) {
2267 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2268 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero() && !rs.IsZero());
2270 Emit(0x1d404400 | Rd(rd) | Rn(rn) | Rs(rs));
2275 const Register& rn) {
2277 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2278 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero() && !rs.IsZero());
2280 Emit(0x1d000400 | Rd(rd) | Rn(rn) | Rs(rs));
2285 const Register& rn) {
2287 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2288 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero() && !rs.IsZero());
2290 Emit(0x1d00c400 | Rd(rd) | Rn(rn) | Rs(rs));
2295 const Register& rn) {
2297 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2298 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero() && !rs.IsZero());
2300 Emit(0x1d008400 | Rd(rd) | Rn(rn) | Rs(rs));
2305 const Register& rn) {
2307 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2308 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero() && !rs.IsZero());
2310 Emit(0x1d004400 | Rd(rd) | Rn(rn) | Rs(rs));
2314 const Register& rn,
2317 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2318 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero());
2320 Emit(0x19c08400 | Rd(rd) | Rn(rn) | Rs(rs));
2324 const Register& rn,
2327 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2328 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero());
2330 Emit(0x19c0a400 | Rd(rd) | Rn(rn) | Rs(rs));
2334 const Register& rn,
2337 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2338 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero());
2340 Emit(0x1dc08400 | Rd(rd) | Rn(rn) | Rs(rs));
2344 const Register& rn,
2347 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2348 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero());
2350 Emit(0x1dc0a400 | Rd(rd) | Rn(rn) | Rs(rs));
2354 const Register& rn,
2357 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2358 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero());
2360 Emit(0x1dc04400 | Rd(rd) | Rn(rn) | Rs(rs));
2364 const Register& rn,
2367 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2368 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero());
2370 Emit(0x1dc06400 | Rd(rd) | Rn(rn) | Rs(rs));
2374 const Register& rn,
2377 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2378 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero());
2380 Emit(0x1dc00400 | Rd(rd) | Rn(rn) | Rs(rs));
2384 const Register& rn,
2387 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2388 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero());
2390 Emit(0x1dc02400 | Rd(rd) | Rn(rn) | Rs(rs));
2394 const Register& rn,
2397 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2398 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero());
2400 Emit(0x19c04400 | Rd(rd) | Rn(rn) | Rs(rs));
2404 const Register& rn,
2407 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2408 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero());
2410 Emit(0x19c06400 | Rd(rd) | Rn(rn) | Rs(rs));
2414 const Register& rn,
2417 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2418 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero());
2420 Emit(0x19c00400 | Rd(rd) | Rn(rn) | Rs(rs));
2424 const Register& rn,
2427 VIXL_ASSERT(!AreAliased(rd, rn, rs));
2428 VIXL_ASSERT(!rd.IsZero() && !rn.IsZero());
2430 Emit(0x19c02400 | Rd(rd) | Rn(rn) | Rs(rs));
2433 void Assembler::abs(const Register& rd, const Register& rn) {
2435 VIXL_ASSERT(rd.IsSameSizeAndType(rn));
2437 Emit(0x5ac02000 | SF(rd) | Rd(rd) | Rn(rn));
2440 void Assembler::cnt(const Register& rd, const Register& rn) {
2442 VIXL_ASSERT(rd.IsSameSizeAndType(rn));
2444 Emit(0x5ac01c00 | SF(rd) | Rd(rd) | Rn(rn));
2447 void Assembler::ctz(const Register& rd, const Register& rn) {
2449 VIXL_ASSERT(rd.IsSameSizeAndType(rn));
2451 Emit(0x5ac01800 | SF(rd) | Rd(rd) | Rn(rn));
2462 const Register& rn, \
2464 VIXL_ASSERT(rd.IsSameSizeAndType(rn)); \
2465 Instr i = SF(rd) | Rd(rd) | Rn(rn); \
3321 void Assembler::fmov(const VRegister& vd, const Register& rn) {
3325 VIXL_ASSERT((vd.GetSizeInBits() == rn.GetSizeInBits()) || vd.Is1H());
3330 op = rn.Is64Bits() ? FMOV_hx : FMOV_hw;
3338 Emit(op | Rd(vd) | Rn(rn));
3353 void Assembler::fmov(const VRegister& vd, int index, const Register& rn) {
3355 VIXL_ASSERT((index == 1) && vd.Is1D() && rn.IsX());
3357 Emit(FMOV_d1_x | Rd(vd) | Rn(rn));
3804 void Assembler::scvtf(const VRegister& vd, const Register& rn, int fbits) {
3810 Emit(SF(rn) | FPType(vd) | SCVTF | Rn(rn) | Rd(vd));
3812 Emit(SF(rn) | FPType(vd) | SCVTF_fixed | FPScale(64 - fbits) | Rn(rn) |
3818 void Assembler::ucvtf(const VRegister& vd, const Register& rn, int fbits) {
3824 Emit(SF(rn) | FPType(vd) | UCVTF | Rn(rn) | Rd(vd));
3826 Emit(SF(rn) | FPType(vd) | UCVTF_fixed | FPScale(64 - fbits) | Rn(rn) |
5056 void Assembler::dup(const VRegister& vd, const Register& rn) {
5059 VIXL_ASSERT(vd.Is2D() == rn.IsX());
5061 Emit(q | NEON_DUP_GENERAL | ImmNEON5(VFormat(vd), 0) | Rn(rn) | Rd(vd));
5111 void Assembler::ins(const VRegister& vd, int vd_index, const Register& rn) {
5120 VIXL_ASSERT(rn.IsW());
5124 VIXL_ASSERT(rn.IsW());
5128 VIXL_ASSERT(rn.IsW());
5132 VIXL_ASSERT(rn.IsX());
5140 Emit(NEON_INS_GENERAL | ImmNEON5(format, vd_index) | Rn(rn) | Rd(vd));
5144 void Assembler::mov(const VRegister& vd, int vd_index, const Register& rn) {
5146 ins(vd, vd_index, rn);
5975 const Register& rn,
5979 VIXL_ASSERT(rd.GetSizeInBits() == rn.GetSizeInBits());
5985 ImmAddSub(static_cast<int>(immediate)) | dest_reg | RnSP(rn));
5997 if (rn.IsSP() || rd.IsSP()) {
6000 rn,
6005 DataProcShiftedRegister(rd, rn, operand, S, AddSubShiftedFixed | op);
6009 DataProcExtendedRegister(rd, rn, operand, S, AddSubExtendedFixed | op);
6015 const Register& rn,
6019 VIXL_ASSERT(rd.GetSizeInBits() == rn.GetSizeInBits());
6022 Emit(SF(rd) | op | Flags(S) | Rm(operand.GetRegister()) | Rn(rn) | Rd(rd));
6046 const Register& rn,
6049 VIXL_ASSERT(rd.GetSizeInBits() == rn.GetSizeInBits());
6067 LogicalImmediate(rd, rn, n, imm_s, imm_r, op);
6076 DataProcShiftedRegister(rd, rn, operand, LeaveFlags, dp_op);
6082 const Register& rn,
6091 Rn(rn));
6095 void Assembler::ConditionalCompare(const Register& rn,
6110 Emit(SF(rn) | ccmpop | Cond(cond) | Rn(rn) | Nzcv(nzcv));
6115 const Register& rn,
6117 VIXL_ASSERT(rd.GetSizeInBits() == rn.GetSizeInBits());
6118 Emit(SF(rn) | op | Rn(rn) | Rd(rd));
6192 const Register& rn,
6197 lsl(rd, rn, shift_amount);
6200 lsr(rd, rn, shift_amount);
6203 asr(rd, rn, shift_amount);
6206 ror(rd, rn, shift_amount);
6215 const Register& rn,
6218 VIXL_ASSERT(rd.GetSizeInBits() >= rn.GetSizeInBits());
6221 Register rn_ = Register(rn.GetCode(), rd.GetSizeInBits());
6241 VIXL_ASSERT(rn.GetSizeInBits() == kXRegSize);
6257 const Register& rn,
6262 VIXL_ASSERT(rn.Is64Bits() ||
6263 (rn.Is32Bits() && IsUint5(operand.GetShiftAmount())));
6266 Rn(rn) | Rd(rd));
6271 const Register& rn,
6278 ImmExtendShift(operand.GetShiftAmount()) | dest_reg | RnSP(rn));