Lines Matching refs:index
2492 // The immediate post index addressing mode is indicated by rm = 31.
2507 // index by immediate of the size of the register list, or post index by a
2870 // Lane size is encoded in the opcode field. Lane index is encoded in the Q,
3353 void Assembler::fmov(const VRegister& vd, int index, const Register& rn) {
3355 VIXL_ASSERT((index == 1) && vd.Is1D() && rn.IsX());
3356 USE(index);
3361 void Assembler::fmov(const Register& rd, const VRegister& vn, int index) {
3363 VIXL_ASSERT((index == 1) && vn.Is1D() && rd.IsX());
3364 USE(index);
5003 int index) {
5007 VIXL_ASSERT((0 <= index) && (index < vd.GetLanes()));
5008 Emit(VFormat(vd) | NEON_EXT | Rm(vm) | ImmNEONExt(index) | Rn(vn) | Rd(vd));
6582 // We find the lowest set bit (as an actual power-of-2 value, not its index)